Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20040140513 A1
Publication typeApplication
Application numberUS 10/754,842
Publication dateJul 22, 2004
Filing dateJan 9, 2004
Priority dateAug 22, 2002
Also published asCN1689143A, CN100359640C, EP1532669A1, US7351628, US20040036129, US20050032342, US20050179097, WO2004019394A1
Publication number10754842, 754842, US 2004/0140513 A1, US 2004/140513 A1, US 20040140513 A1, US 20040140513A1, US 2004140513 A1, US 2004140513A1, US-A1-20040140513, US-A1-2004140513, US2004/0140513A1, US2004/140513A1, US20040140513 A1, US20040140513A1, US2004140513 A1, US2004140513A1
InventorsLeonard Forbes, Kie Ahn
Original AssigneeMicron Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Atomic layer deposition of CMOS gates with variable work functions
US 20040140513 A1
Abstract
According to one aspect, a CMOS device includes a PMOS transistor and an NMOS transistor, where each transistor includes a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator. The gate of the PMOS transistor includes a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a first composition having a first work function. The gate of the NMOS transistor includes a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a second composition having a second work function such that the NMOS transistor and the PMOS transistor have threshold voltages of approximately the same magnitude. At least one of the gates includes a ternary metal conductor formed by atomic layer deposition.
Images(6)
Previous page
Next page
Claims(32)
What is claimed is:
1. A method for forming a CMOS device, comprising:
identifying a desired first gate composition having a desired first work function to provide a desired first threshold voltage for a PMOS transistor and a desired second gate composition having a desired second work function to provide a desired second threshold voltage for an NMOS transistor such that the first and second threshold voltages have approximately equal magnitudes;
forming the PMOS transistor, including forming a first gate using atomic layer deposition to provide the desired first gate composition; and
forming the NMOS transistor, including forming a second gate using atomic layer deposition to provide the desired second gate composition,
wherein at least one of forming a first gate and forming a second gate includes forming a ternary metallic conductor using atomic layer deposition.
2. The method of claim 1, wherein forming a ternary metallic conductor includes forming Tantalum Aluminum Nitride (TaAlN) using atomic layer deposition.
3. The method of claim 1, wherein forming a ternary metallic conductor includes forming Titanium Aluminum Nitride (TiAlN) using atomic layer deposition.
4. The method of claim 1, wherein forming a ternary metallic conductor includes forming Titanium Silicon Nitride (TiSiN) using atomic layer deposition.
5. The method of claim 1, wherein forming a ternary metallic conductor includes forming Tungsten Aluminum Nitride (WAlN) using atomic layer deposition.
6. The method of claim 1, further comprising forming a refractory metal on the ternary metallic conductor.
7. The method of claim 1, further comprising forming a conductive silicon layer on the ternary metallic conductor.
8. A method for forming a CMOS device, comprising:
identifying a desired first gate composition having a desired first work function to provide a desired first threshold voltage for a PMOS transistor and a desired second gate composition having a desired second work function to provide a desired second threshold voltage for an NMOS transistor such that the first and second threshold voltages have approximately equal magnitudes;
forming the PMOS transistor, including forming a first gate using atomic layer deposition to provide the desired first gate composition; and
forming the NMOS transistor, including forming a second gate using atomic layer deposition to provide the desired second gate composition,
wherein one of forming a first gate and forming a second gate includes forming a ternary metallic conductor using atomic layer deposition, and the other of forming a first gate and forming a second gate includes forming a binary metallic conductor using atomic layer deposition, and
wherein the binary metallic conductor includes Tantalum Nitride (TaN) and the ternary metallic conductor includes Tantalum Aluminum Nitride (TaAlN).
9. The method of claim 8, further comprising forming a refractory metal on the ternary metallic conductor.
10. The method of claim 8, further comprising forming a conductive silicon layer on the ternary metallic conductor.
11. A method for forming a CMOS device, comprising:
identifying a desired first gate composition having a desired first work function to provide a desired first threshold voltage for a PMOS transistor and a desired second gate composition having a desired second work function to provide a desired second threshold voltage for an NMOS transistor such that the first and second threshold voltages have approximately equal magnitudes;
forming the PMOS transistor, including forming a first gate using atomic layer deposition to provide the desired first gate composition; and
forming the NMOS transistor, including forming a second gate using atomic layer deposition to provide the desired second gate composition,
wherein one of forming a first gate and forming a second gate includes forming a ternary metallic conductor using atomic layer deposition, and the other of forming a first gate and forming a second gate includes forming a binary metallic conductor using atomic layer deposition, and
wherein the binary metallic conductor includes Titanium Nitride (TiN) and the ternary metallic conductor includes Titanium Aluminum Nitride (TiAlN).
12. The method of claim 11, further comprising forming a refractory metal on the ternary metallic conductor.
13. The method of claim 11, further comprising forming a conductive silicon layer on the ternary metallic conductor.
14. A method for forming a CMOS device, comprising:
identifying a desired first gate composition having a desired first work function to provide a desired first threshold voltage for a PMOS transistor and a desired second gate composition having a desired second work function to provide a desired second threshold voltage for an NMOS transistor such that the first and second threshold voltages have approximately equal magnitudes;
forming the PMOS transistor, including forming a first gate using atomic layer deposition to provide the desired first gate composition; and
forming the NMOS transistor, including forming a second gate using atomic layer deposition to provide the desired second gate composition,
wherein one of forming a first gate and forming a second gate includes forming a ternary metallic conductor using atomic layer deposition, and the other of forming a first gate and forming a second gate includes forming a binary metallic conductor using atomic layer deposition, and
wherein the binary metallic conductor includes Tungsten Nitride (WN) and the ternary metallic conductor includes Tungsten Aluminum Nitride (WAlN).
15. The method of claim 14, further comprising forming a refractory metal on the ternary metallic conductor.
16. The method of claim 14, further comprising forming a conductive silicon layer on the ternary metallic conductor.
17. A CMOS device, comprising:
a PMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a first composition having a first work function; and
an NMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a second composition having a second work function such that the NMOS transistor and the PMOS transistor have threshold voltages of approximately the same magnitude,
wherein at least one of the gate for the PMOS transistor and the gate for the NMOS transistor includes a ternary metal conductor formed by atomic layer deposition.
18. The CMOS device of claim 17, wherein the ternary metallic conductor includes Tantalum Aluminum Nitride (TaAlN).
19. The CMOS device of claim 17, wherein the ternary metallic conductor includes Titanium Aluminum Nitride (TiAlN).
20. The CMOS device of claim 17, wherein the ternary metallic conductor includes Titanium Silicon Nitride (TiSiN).
21. The CMOS device of claim 17, wherein the ternary metallic conductor includes Tungsten Aluminum Nitride (WAlN).
22. The CMOS device of claim 17, further comprising a refractory metal on the ternary metallic conductor.
23. The CMOS device of claim 17, further comprising a conductive silicon layer on the ternary metallic conductor.
24. A CMOS device, comprising:
a PMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a first composition having a first work function; and
an NMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate having a second composition and a second work function such that the NMOS transistor and the PMOS transistor have threshold voltages of approximately the same magnitude,
wherein one of the gate for the PMOS transistor and the gate for the NMOS transistor includes Tantalum Aluminum Nitride (TaAlN) formed by atomic layer deposition and the other one of the gate for the PMOS transistor and the gate for the NMOS transistor includes Tantalum Nitride (TaN) formed by atomic layer deposition.
25. The CMOS device of claim 24, further comprising a refractory metal on the ternary metallic conductor.
26. The CMOS device of claim 24, further comprising a conductive silicon layer on the ternary metallic conductor.
27. A CMOS device, comprising:
a PMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a first composition having a first work function; and
an NMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a second composition having a second work function such that the NMOS transistor and the PMOS transistor have threshold voltages of approximately the same magnitude,
wherein one of the gate for the PMOS transistor and the gate for the NMOS transistor includes Titanium Aluminum Nitride (TiAlN) formed by atomic layer deposition and the other one of the gate for the PMOS transistor and the gate for the NMOS transistor includes Titanium Nitride (TiN) formed by atomic layer deposition.
28. The CMOS device of claim 27, further comprising a refractory metal on the ternary metallic conductor.
29. The CMOS device of claim 27, further comprising a conductive silicon layer on the ternary metallic conductor.
30. A CMOS device, comprising:
a PMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a first composition having a first work function; and
an NMOS transistor, including a source, a drain, a channel region between the source and the drain, and a gate separated from the channel region by a gate insulator, the gate including a metallic conductor formed by atomic layer deposition and engineered to provide the gate with a second composition having a second work function such that the NMOS transistor and the PMOS transistor have threshold voltages of approximately the same magnitude,
wherein one of the gate for the PMOS transistor and the gate for the NMOS transistor includes Tungsten Aluminum Nitride (WAlN) formed by atomic layer deposition and the other one of the gate for the PMOS transistor and the gate for the NMOS transistor includes Tungsten Nitride (WN) formed by atomic layer deposition.
31. The CMOS device of claim 30, further comprising a refractory metal on the ternary metallic conductor.
32. The CMOS device of claim 30, further comprising a conductive silicon layer on the ternary metallic conductor.
Description
    CROSS REFERENCE TO RELATED APPLICATION(S)
  • [0001]
    This application is a continuation-in-part of U.S. patent application Ser. No. 10/225,605, filed Aug. 22, 2002, the specification of which is incorporated herein by reference.
  • FIELD OF THE INVENTION
  • [0002]
    The present invention relates generally to semiconductor integrated circuits and, more particularly, to atomic layer deposition of CMOS gates with variable work functions.
  • BACKGROUND OF THE INVENTION
  • [0003]
    Conventional n-type doped polysilicon gate electrodes in CMOS technology have two problems. Firstly, the polysilicon is conductive but there can still be a surface region which can be depleted of carriers under bias conditions. This appears as an extra gate insulator thickness and is commonly referred to as gate depletion and contributes to the equivalent oxide thickness. While this region is thin, in the order of a few angstroms (Å), it becomes appreciable as gate oxide thicknesses are reduced below 2 nm or 20 Å. Another problem is that the work function is not optimum for both n-MOS and p-MOS devices, historically this was compensated for by threshold voltage adjustment implantations. However, as the devices become smaller, with channel lengths of less than 1000 Å and consequently surface space charge regions of less than 100 Å, it becomes more and more difficult to do these implantations. Threshold voltage control becomes an important consideration as power supplies are reduced to the range of one volt. Optimum threshold voltages for both PMOS and NMOS transistors need to have a magnitude of around 0.3 Volts.
  • [0004]
    A solution to the polysilicon gate depletion problem is to replace the semiconducting gate material with a metal or highly conductive metallic nitrides. As with any new circuit material, the gate electrode must be chemically and thermally compatible with both the transistor and the process. Different metals can be employed or the properties of the conductive nitride modified to provide an optimum work function.
  • [0005]
    The work function of the gate electrode—the energy needed to extract an electron—must be compatible with the barrier height of the semiconductor material. For PMOS transistors, the required work function is about 5.0 eV. Achieving the lower work function needed by NMOS transistors, about 4.1 eV, has been more difficult. FIGS. 1A and 1B illustrate the desired energy band diagrams and work functions for NMOS and PMOS transistors respectively. Refractory metals like titanium (Ti) and tantalum (Ta) oxidize rapidly under typical process conditions. One proposed solution to the problem relies on a “tuned” ruthenium-tantalum (Ru—Ta) alloy, which is stable under process conditions. When the Ta concentration is below 20 percent, the alloy's electrical properties resemble Rhubidium (Ru), a good PMOS gate electrode. When the Ta concentration is between 40 percent and 54 percent, the alloy is a good NMOS gate electrode.
  • [0006]
    Promising candidates include metallic nitrides, such as tantalum nitride (TaN) and titanium nitride (TiN). Tantalum nitride, titanium nitride, and tungsten nitride are mid-gap work function metallic conductors commonly described for use in CMOS devices. The use of a mid-gap work function makes the threshold voltages of NMOS and PMOS devices symmetrical in that the magnitudes of the threshold voltages will be the same, but both will have a magnitude larger than that which is optimum with low power supply voltages.
  • [0007]
    Recently physical deposition, evaporation, has been used to investigate the suitability of some ternary metallic nitrides for use as gate electrodes, these included TiAlN and TaSiN. However, these were deposited by physical deposition not atomic layer deposition and only capacitor structures were fabricated, not transistors with gate structures.
  • [0008]
    Thus, there is an ongoing need for improved CMOS transistor design.
  • SUMMARY OF THE INVENTION
  • [0009]
    The above mentioned problems CMOS transistor design as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. This disclosure describes the use of atomic layer deposition of ternary metallic conductors where the composition and work function are varied to control the threshold voltage of both the NMOS and PMOS transistors in CMOS technology to provide optimum performance.
  • [0010]
    In particular, an embodiment of the present invention includes a transistor having a source region a drain region and a channel therebetween. A gate is separated from the channel region by a gate insulator. The gate includes a ternary metallic conductor formed by atomic layer deposition. In one embodiment the ternary metallic conductor includes Tantalum Aluminum Nitride (TaAlN). In one embodiment the ternary metallic conductor includes Titanium Aluminum Nitride (TiAlN). In one embodiment the ternary metallic conductor includes Titanium Silicon Nitride (TiSiN). In one embodiment the ternary metallic conductor includes Tungsten Aluminum Nitride (WAlN). In some embodiments the gate further includes a refractory metal formed on the ternary metallic conductor.
  • [0011]
    These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0012]
    [0012]FIGS. 1A and 1B illustrate the desired energy band diagrams and work functions for NMOS and PMOS transistors respectively.
  • [0013]
    [0013]FIG. 2 is a graph which plots electron affinity versus the energy bandgap for various metallic nitrides employed in various embodiments of the present invention.
  • [0014]
    [0014]FIG. 3 illustrates an embodiment of a transistor structure formed according to the teachings of the present invention.
  • [0015]
    [0015]FIG. 4 illustrates an embodiment of a memory device, utilizing ternary metallic gates formed by atomic layer deposition, according to embodiments of the present invention.
  • [0016]
    [0016]FIG. 5 is a block diagram of an electrical system, or processor-based system, utilizing ternary metallic gates formed by atomic layer deposition, according to embodiments of the present invention.
  • DETAILED DESCRIPTION
  • [0017]
    In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.
  • [0018]
    The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
  • [0019]
    This disclosure describes the use of atomic layer deposition of ternary metallic conductors where the composition is varied and work function varied, see FIG. 2, to control the threshold voltage of both the NMOS and PMOS transistors in CMOS technology to provide optimum performance. In the several embodiments, these include the use of TaAlN, TiAlN, TiSiN, and WAlN as the ternary metallic conductors. Conventional highly doped polysilicon or refractory metals as W, Ta, Ti are deposited over the metallic conductors to give the gate structure shown in FIG. 3. As shown in FIG. 3, the transistor 301 structure includes a source region 302, a drain region 304, and a channel 306 therebetween. A gate 310 is separated from the channel region by a gate insulator 308. According to the teachings of the present invention, the gate 310 includes a ternary metallic conductor formed by atomic layer deposition. In one embodiment the ternary metallic conductor includes Tantalum Aluminum Nitride (TaAlN). In one embodiment the ternary metallic conductor includes Titanium Aluminum Nitride (TiAlN). In one embodiment the ternary metallic conductor includes Titanium Silicon Nitride (TiSiN). In one embodiment the ternary metallic conductor includes Tungsten Aluminum Nitride (WAlN). As shown in FIG. 3, in some embodiments the gate further includes a layer of highly conductive polysilicon 312, or alternatively a refractory metal layer 312, formed on the ternary metallic conductor 310. In embodiments having a refractory metal layer, the layer 312 includes for example, and not by way of limitation, refractory metals such as tantalum, titanium and tungsten.
  • [0020]
    Methods of Formation
  • [0021]
    Atomic Layer Deposition developed in the early 70s is a modification of CVD and can also be called as “alternately pulsed-CVD”. In this technique, gaseous precursors are introduced one at a time to the substrate surface, and between the pulses the reactor is purged with an inert gas or evacuated. In the first reaction step the precursor is saturatively chemisorbed at the substrate surface, and during the subsequent purging the precursor is removed from the reactor. In the second step, other precursor is introduced on the substrate and the desired films growth reaction takes place. After that the reaction byproducts and the precursor excess are purged out from the reactor. When the precursor chemistry is favorable, i.e. the precursor adsorb and react with each other aggressively, one ALD cycle can be preformed in less than one second in the properly designed flow type reactors.
  • [0022]
    The striking feature of ALD is the saturation of all the reaction and purging steps which makes the growth self-limiting. This brings the large area uniformity and conformality, the most important properties of ALD, as shown in very different cases, viz. planar substrates, deep trenches, and in the extreme cases of porous silicon and high surface area silica and alumina powers. Also the control of the film thickness is straightforward and can be made by simply calculating the growth cycles. ALD was originally developed to manufacture luminescent and dielectric films needed in electroluminescent displays, and a lot of effort has been put to the growth of doped zinc sulfide and alkaline earth metal sulfide films. Later ALD has been studied for the growth of different epitaxial II-V and II-VI films, nonepitaxial crystalline or amorphous oxide and nitride films are their multilayer structures.
  • [0023]
    There has been considerable interest towards the ALD growth of silicon and germanium films but due to the difficult precursor chemistry the results have not been very successful.
  • [0024]
    Reaction sequence ALD (RS-ALD) films have several unique and unmatched advantages:
  • [0025]
    Continuity at the interface avoiding poorly defined nucleating regions that are typical for CVD (<20 Å) and PVD (<50 Å) films. To achieve this continuity, the substrate surface must be activated to react directly with the first exposure of RS-ALD precursor.
  • [0026]
    Unmatched conformality over toughest substrate topologies with robust processes that can only be achieved with a layer-by-layer deposition technique.
  • [0027]
    Typically, low temperature and mildly oxidizing processes. This is thought to be a major advantage for gate insulator processing where deposition of non-silicon based dielectrics without oxidizing the substrate (with the oxidation-precursor) is a major concern.
  • [0028]
    RS-ALD ability to engineer multilayer laminate films, possibly down to monolayer resolution, as well as alloy composite films appear to be unique. This ability comes from the combination of being able to control deposition with monolayer precision and the ability to deposit continuous monolayers of amorphous films (that is unique to RS-ALD).
  • [0029]
    Unprecedented process robustness. RS-ALD processes are free of first wafer effects and the chamber dependence. Accordingly, RS-ALD processes will be easier to transfer from development to production and from 200 to 300 mm wafer size.
  • [0030]
    Thickness depends solely on the number of cycles. Thickness can be “dialed in” as a simple recipe change bearing no need for additional process development upon technology generation advance.
  • [0031]
    Atomic Layer Deposition of Nitrides
  • [0032]
    Ta—N: Plasma-enhanced atomic layer deposition (PEALD) of tantalum nitride (Ta—N) thin films at a deposition temperature of 260 C. using hydrogen radicals as a reducing agent for Tertbutylimidotris(diethylamido) tantalum have been described. The PEALD yields superior Ta—N films with an electric resistivity of 400 μΩcm and no aging effect under exposure to air. The film density is higher than that of Ta—N films formed by typical ALD, in which NH3 is used instead of hydrogen radicals. In addition, the as-deposited films are not amorphous, but rather polycrystalline structure of cubit TaN. The density and crystallinity of the films increases with the pulse time of hydrogen plasma. The films are Ta-rich in composition and contain around 15 atomic % of carbon impurity. In the PEALD of Ta—N films, hydrogen radicals are used a reducing agent instead of NH3, which is used as a reactant gas in typical Ta—N ALD. Films are deposited on SiO2 (100 nm)/Si wafers at a deposition temperature of 260 C. and a deposition pressure of 133 Pa in a cold-walled reactor using (Net2)3 Ta=Nbut [tertbutylimidotris(diethylamido)tantalum, TBTDET] as a precursor of Ta. The liquid precursor is contained in a bubbler heated at 70 C. and carried by 35 sccm argon. One deposition cycle consist of an exposure to a metallorganic precursor of TBTDET, a purge period with Ar, and an exposure to hydrogen plasma, followed by another purge period with Ar. The Ar purge period of 15 seconds instead between each reactant gas pulse isolates the reactant gases from each other. To ignite and maintain the hydrogen plasma synchronized with the deposition cycle, a rectangular shaped electrical power is applied between the upper and lower electrode. The showerhead for uniform distribution of the reactant gases in the reactor, capacitively coupled with an rf (13.56 MHz) plasma source operated at a power of 100 W, is used as the upper electrode. The lower electrode, on which a wafer resides, is grounded. Film thickness and morphology were analyzed by field emission scanning electron microscopy.
  • [0033]
    Ta (Al)N(C): Technical work on thin films have been studied using TaCl5 or TaBr5 and NH3 as precursors and Al(CH3)3 as an additional reducing agent. The deposition temperature is varied between 250 and 400 C. The films contained aluminum, carbon, and chlorine impurities. The chlorine content decreased drastically as the deposition temperature is increased. The film deposited at 400 C. contained less than 4 atomic % chlorine and also had the lowest resistivity, 1300 μΩcm. Five different deposition processes with the pulsing orders TaCl5-TMA-NH3, TMA-TaCl5—NH3, TaBr5—NH3, TaBr5—Zn—NH3, and TaBr5-TMA-NH3 are used. TaCl5, TaBr5, and Zn are evaporated from open boats held inside the reactor. The evaporation temperatures for TaCl4, TaBr5, and Zn are 90, 140, 380 C., respectively. Ammonia is introduced into the reactor through a mass flowmeter, a needle valve, and a solenoid valve. The flow rate is adjusted to 14 sccm during a continuous flow. TMA is kept at a constant temperature of 16 C. and pulsed through the needle and solenoid valve. Pulse times are 0.5 s for TaCl5, TaBr5, NH3, and Zn whereas the pulse length of TMA is varied between 0.2 and 0.8 s. The length of the purge pulse is always 0.3 s. Nitrogen gas is used for the transportation of the precursor and as a purging gas. The flow rate of nitrogen is 400 sccm.
  • [0034]
    TiN: Atomic layer deposition (ALD) of amorphous TiN films on SiO2 between 170 C. and 210 C. has been achieved by the alternate supply of reactant sources, Ti[N(C2H5CH3)2]4 [tetrakis(ethylmethylamino)titanium: TEMAT] and NH3. These reactant sources are injected into the reactor in the following order: TEMAT vapor pulse, Ar gas pulse, NH3 gas pulse and Ar gas pulse. Film thickness per cycle saturated at around 1.6 monolayers per cycle with sufficient pulse times of reactant sources at 200 C. The results suggest that film thickness per cycle could exceed 1 ML/cycle in ALD, and are explained by the rechemisorption mechanism of the reactant sources. An ideal linear relationship between number of cycles and film thickness is confirmed.
  • [0035]
    TiAlN: Koo et al published paper on the study of the characteristics of TiAlN thin film deposited by atomic layer deposition method. The series of metal-Si—N barriers have high resistivity above 1000 μΩcm. They proposed another ternary diffusion barrier of TiAlN. TiAlN film exhibited a NaCl structure in spite of considerable Al contents. TiAlN films are deposited using the TiCl4 and dimethylaluminum hydride ethypiperdine (DMAH-EPP) as the titanium and aluminum precursors, respectively. TiCl4 is vaporized from the liquid at 13-15 C. and introduced into the ALD chamber, which is supplied by a bubbler using the Ar carrier gas with a flow rate of 30 sccm. The DMAH-EPP precursor is evaporated at 60 C. and introduced into the ALD chamber with the same flow rate of TiCl4. The NH3 gas is also used as a reactant gas and its flow rate is about 60 sccm. Ar purging gas is introduced for the complete separation of the source and reactant gases. TiAlN films are deposited at the temperatures between 350 and 400 C. and total pressure is kept constant to be two torr.
  • [0036]
    TiSiN: Metal-organic atomic-layer deposition (MOALD) achieves near-perfect step coverage step and control precisely the thickness and composition of grown thin films. A MOALD technique for ternary Ti—Si—N films using a sequential supply of Ti[N(CH3)2]4 [tetrakis (dimethylamido) titanium: TDMAT], silane (SiH4), and ammonia (NH3), has been developed and evaluated the Cu diffusion barrier characteristics of a 10 mn Ti—Si—N film with high-frequency C-V measurements. At 180 C. deposition temperature, silane is supplied separately in the sequence of the TDMAT pulse, silane pulse, and the ammonia pulse. The silicon content is the deposited films and the deposition thickness per cycle remained almost constant at 18 at. % and 0.22 nm/cycle, even though the silane partial pressure varied from 0.27 to 13.3 Pa. Especially, the Si content dependence is strikingly different from the conventional chemical-vapor deposition. Step coverage is approximately 100% even on the 0.3 μm diameter hole with slightly negative slope and 10:1 aspect ratio.
  • [0037]
    WN: Tungsten nitride films have been deposited with the atomic layer control using sequential surface reactions. The tungsten nitride film growth is accomplished by separating the binary reaction 2WF6+NH3→W2N+3HF+9/2F2 into two half-reactions. Successive application of the WF6 and NH3 half-reactions in an ABAB . . . sequence produced tungsten nitride deposition at substrate temperatures between 600 and 800 K. Transmission Fourier transform infrared (FTIR) spectroscopy monitored the coverage of WF6* and NHy* surface species on high surface area particles during the WF6 and NH3 half-reactions. The FTIR spectroscope results demonstrated the WF6 and NH3 half-reactions are complete and self-limiting at temperatures >600 K. In situ spectroscopic ellipsometry monitored the film growth on Si(100) substrate vs. temperature and reactant exposure. A tungsten nitride deposition rate of 2.55 Å/AB cycle is measured at 600-800 K for WF6 and NH3 reactant exposure >3000 L and 10,000 L, respectively. X-ray photoelectron spectroscopy depth-profiling experiments determined that the films had a W2N stoichiometry with low C and O impurity concentrations. X-ray diffraction investigations revealed that the tungsten nitride films are microcrystalline. Atomic force microscopy measurements of the deposited films observed remarkably flat surface indicating smooth film growth. These smooth tungsten nitride films deposited with atomic layer control should be used as diffusion control for Cu on contact and via holes.
  • [0038]
    AlN: Aluminum nitride (AlN) has been grown on porous silica by atomic layer chemical vapor deposition (ALCVD) from trimethylaluminum (TMA) and ammonia precursors. The ALCVD growth is based on alternating, separated, saturating reactions of the gaseous precursors with the solid substrates. TMA and ammonia are reacted at 423 and 623 Kelvin (K), respectively, on silica which has been dehydroxylated at 1023 K pretreated with ammonia at 823 K. The growth in three reaction cycles is investigated quantitatively by elemental analysis, and the surface reaction products are identified by IR and solid state and Si NMR measurements. Steady growth of about 2 aluminum atoms/nm2 silica/reaction cycle is obtained. The growth mainly took place through (I) the reaction of TMA which resulted in surface Al—Me and Si—Me groups, and (II) the reaction of ammonia which replaced aluminium-bonded methyl groups with amino groups. Ammonia also reacted in part with the silicon-bonded methyl groups formed in the dissociated reaction of TMA with siloxane bridges. TMA reacted with the amino groups, as it did with surface silanol groups and siloxane bridges. In general, the Al—N layer interacted strongly with the silica substrates, but in the third reaction cycle AlN-type sites may have formed.
  • [0039]
    Devices
  • [0040]
    In FIG. 4 a memory device is illustrated according to the teachings of the present invention. The memory device 440 contains a memory array 442, row and column decoders 444, 448 and a sense amplifier circuit 446. The memory array 442 consists of a number of transistor cells 400, having ternary metallic gates formed by atomic layer deposition, whose word lines 480 and bit lines 460 are commonly arranged into rows and columns, respectively. The bit lines 460 of the memory array 442 are connected to the sense amplifier circuit 446, while its word lines 480 are connected to the row decoder 444. Address and control signals are input on address/control lines 461 into the memory device 440 and connected to the column decoder 448, sense amplifier circuit 446 and row decoder 444 and are used to gain read and write access, among other things, to the memory array 442.
  • [0041]
    The column decoder 448 is connected to the sense amplifier circuit 446 via control and column select signals on column select lines 462. The sense amplifier circuit 446 receives input data destined for the memory array 442 and outputs data read from the memory array 442 over input/output (I/O) data lines 463. Data is read from the cells of the memory array 442 by activating a word line 480 (via the row decoder 444), which couples all of the memory cells corresponding to that word line to respective bit lines 460, which define the columns of the array. One or more bit lines 460 are also activated. When a particular word line 480 and bit lines 460 are activated, the sense amplifier circuit 446 connected to a bit line column detects and amplifies the conduction sensed through a given transistor cell and transferred to its bit line 460 by measuring the potential difference between the activated bit line 460 and a reference line which may be an inactive bit line. Again, in the read operation the source region of a given cell is couple to a grounded sourceline or array plate (not shown). The operation of Memory device sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.
  • [0042]
    [0042]FIG. 5 is a block diagram of an electrical system, or processor-based system, 500 utilizing transistor cells having ternary metallic gates formed by atomic layer deposition according to the teachings of the present invention. For example, by way of example and not by way of limitation, memory 512 is constructed in accordance with the present invention to have transistor cells having ternary metallic gates formed by atomic layer deposition. However, the invention is not so limited and the same can apply to transistors in the CPU, etc. The processor-based system 500 may be a computer system, a process control system or any other system employing a processor and associated memory. The system 500 includes a central processing unit (CPU) 502, e.g., a microprocessor, that communicates with the memory 512 and an I/O device 508 over a bus 520. It must be noted that the bus 520 may be a series of buses and bridges commonly used in a processor-based system, but for convenience purposes only, the bus 520 has been illustrated as a single bus. A second I/O device 510 is illustrated, but is not necessary to practice the invention. The processor-based system 500 can also includes read-only memory (ROM) 514 and may include peripheral devices such as a floppy disk drive 504 and a compact disk (CD) ROM drive 506 that also communicates with the CPU 502 over the bus 520 as is well known in the art.
  • [0043]
    It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the processor-based system 500 has been simplified to help focus on the invention.
  • [0044]
    It will be understood that the embodiment shown in FIG. 5 illustrates an embodiment for electronic system circuitry in which the novel ternary metallic gate transistor cells, formed by atomic layer deposition, are used. The illustration of system 500, as shown in FIG. 5, is intended to provide a general understanding of one application for the structure and circuitry of the present invention, and is not intended to serve as a complete description of all the elements and features of an electronic system using the novel ternary metallic gate transistor cells, formed by atomic layer deposition. Further, the invention is equally applicable to any size and type of system 500 using the novel ternary metallic gate transistor cells, formed by atomic layer deposition, and is not intended to be limited to that described above. As one of ordinary skill in the art will understand, such an electronic system can be fabricated in single-package processing units, or even on a single semiconductor chip, in order to reduce the communication time between the processor and the memory device.
  • [0045]
    Applications containing the novel ternary metallic gate transistor cells, formed by atomic layer deposition as described in this disclosure, include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others.
  • Conclusion
  • [0046]
    This disclosure describes the use of atomic layer deposition of ternary metallic conductors as transistor gates. The composition is varied and work function varied to control the threshold voltage of both the NMOS and PMOS transistors in CMOS technology to provide optimum performance.
  • [0047]
    It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4811078 *Dec 5, 1986Mar 7, 1989Texas Instruments IncorporatedIntegrated circuit device and process with tin capacitors
US4814854 *Dec 5, 1986Mar 21, 1989Texas Instruments IncorporatedIntegrated circuit device and process with tin-gate transistor
US4897709 *May 26, 1988Jan 30, 1990Hitachi, Ltd.Titanium nitride film in contact hole with large aspect ratio
US4931411 *Dec 20, 1988Jun 5, 1990Texas Instruments IncorporatedIntegrated circuit process with TiN-gate transistor
US5042011 *May 22, 1989Aug 20, 1991Micron Technology, Inc.Sense amplifier pulldown device with tailored edge input
US5280205 *Apr 16, 1992Jan 18, 1994Micron Technology, Inc.Fast sense amplifier
US5589413 *Nov 27, 1995Dec 31, 1996Taiwan Semiconductor Manufacturing CompanyMethod of manufacturing self-aligned bit-line during EPROM fabrication
US5610099 *Jun 28, 1994Mar 11, 1997Ramtron International CorporationProcess for fabricating transistors using composite nitride structure
US5627785 *Mar 15, 1996May 6, 1997Micron Technology, Inc.Memory device with a sense amplifier
US5828113 *Mar 28, 1997Oct 27, 1998Macronix International Co., Ltd.Double density MROM array structure
US6020024 *Aug 4, 1997Feb 1, 2000Motorola, Inc.Method for forming high dielectric constant metal oxides
US6107656 *Oct 28, 1997Aug 22, 2000Oki Electric Industry Co., Ltd.Ferroelectric transistors, semiconductor storage devices, method of operating ferroelectric transistors and method of manufacturing ferromagnetic transistors
US6203613 *Oct 19, 1999Mar 20, 2001International Business Machines CorporationAtomic layer deposition with nitrate containing precursors
US6204172 *Sep 3, 1998Mar 20, 2001Micron Technology, Inc.Low temperature deposition of barrier layers
US6214662 *Jul 3, 2000Apr 10, 2001Taiwan Semiconductor Manufacturing CompanyForming self-align source line for memory array
US6218293 *Nov 13, 1998Apr 17, 2001Micron Technology, Inc.Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride
US6277693 *Feb 29, 2000Aug 21, 2001Taiwan Semiconductor Manufacturing Co., Ltd.Self-aligned process for forming source line of ETOX flash memory
US6278150 *Feb 21, 1997Aug 21, 2001Mitsubishi Denki Kabushiki KaishaConductive layer connecting structure and method of manufacturing the same
US6284646 *Aug 19, 1998Sep 4, 2001Samsung Electronics Co., LtdMethods of forming smooth conductive layers for integrated circuit devices
US6297539 *Jul 6, 2000Oct 2, 2001Sharp Laboratories Of America, Inc.Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same
US6325017 *Aug 25, 1999Dec 4, 2001Micron Technology, Inc.Apparatus for forming a high dielectric film
US6365519 *Apr 16, 2001Apr 2, 2002Micron Technology, Inc.Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride
US6399491 *Apr 6, 2001Jun 4, 2002Samsung Electronics Co., Ltd.Method of manufacturing a barrier metal layer using atomic layer deposition
US6410432 *Apr 27, 1999Jun 25, 2002Tokyo Electron LimitedCVD of integrated Ta and TaNx films from tantalum halide precursors
US6420279 *Jun 28, 2001Jul 16, 2002Sharp Laboratories Of America, Inc.Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate
US6423619 *Nov 30, 2001Jul 23, 2002Motorola, Inc.Transistor metal gate structure that minimizes non-planarity effects and method of formation
US6448192 *Apr 16, 2001Sep 10, 2002Motorola, Inc.Method for forming a high dielectric constant material
US6485988 *Dec 19, 2000Nov 26, 2002Texas Instruments IncorporatedHydrogen-free contact etch for ferroelectric capacitor formation
US6486047 *May 31, 2001Nov 26, 2002Electronics And Telecommunications Research InstituteApparatus for forming strontium-tantalum-oxide thin film
US6495436 *Feb 9, 2001Dec 17, 2002Micron Technology, Inc.Formation of metal oxide gate dielectric
US6531192 *Oct 28, 2001Mar 11, 2003Micron Technology, Inc.Chemical vapor deposition process for depositing titanium nitride films from an organo-metallic compound
US6537901 *Jun 25, 2001Mar 25, 2003Hynix Semiconductor Inc.Method of manufacturing a transistor in a semiconductor device
US6548405 *Apr 2, 2002Apr 15, 2003Micron Technology, Inc.Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride
US6599781 *Sep 27, 2000Jul 29, 2003Chou H. LiSolid state device
US6603328 *Oct 10, 2001Aug 5, 2003Texas Instruments IncorporatedSemiconductor integrated circuit
US6614079 *Jul 19, 2001Sep 2, 2003International Business Machines CorporationAll-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS
US6617634 *Feb 12, 2002Sep 9, 2003Micron Technology, Inc.RuSixOy-containing adhesion layers and process for fabricating the same
US6656282 *Oct 11, 2001Dec 2, 2003Moohan Co., Ltd.Atomic layer deposition apparatus and process using remote plasma
US6674109 *Sep 28, 2000Jan 6, 2004Rohm Co., Ltd.Nonvolatile memory
US6723642 *Feb 27, 2003Apr 20, 2004Electronics And Telecommunications Research InstituteMethod for forming nitrogen-containing oxide thin film using plasma enhanced atomic layer deposition
US6770521 *Apr 29, 2002Aug 3, 2004Texas Instruments IncorporatedMethod of making multiple work function gates by implanting metals with metallic alloying additives
US6784515 *Sep 27, 2000Aug 31, 2004Chou H LiSemiconductor integrated circuit device
US6800173 *Jul 9, 2001Oct 5, 2004Novellus Systems, Inc.Variable gas conductance control for a process chamber
US6873020 *Feb 22, 2002Mar 29, 2005North Carolina State UniversityHigh/low work function metal alloys for integrated circuit electrodes
US6919273 *Dec 9, 1999Jul 19, 2005Tokyo Electron LimitedMethod for forming TiSiN film, diffusion preventive film comprising TiSiN film, semiconductor device and its production method, and apparatus for forming TiSiN film
US6921702 *Jul 30, 2002Jul 26, 2005Micron Technology Inc.Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US6967154 *Aug 26, 2002Nov 22, 2005Micron Technology, Inc.Enhanced atomic layer deposition
US7118942 *Jul 29, 2003Oct 10, 2006Li Chou HMethod of making atomic integrated circuit device
US7208779 *Aug 10, 2004Apr 24, 2007Kabushiki Kaisha ToshibaSemiconductor device
US7351628 *Aug 30, 2004Apr 1, 2008Micron Technology, Inc.Atomic layer deposition of CMOS gates with variable work functions
US20020004299 *Aug 31, 2001Jan 10, 2002Schuele Paul J.Method of fabricating a contract structure having a composite barrier layer between a platinium layer and a polysilicon plug
US20020089023 *Jan 5, 2001Jul 11, 2002Motorola, Inc.Low leakage current metal oxide-nitrides and method of fabricating same
US20020195683 *Mar 27, 2000Dec 26, 2002Kim Yeong-KwanSemiconductor device and method for manufacturing the same
US20030162342 *Feb 23, 2002Aug 28, 2003Taiwan Semiconductor Manufacturing Co., Ltd.Method for fabricating metal gates in deep sub-micron devices
US20040164362 *Feb 23, 2004Aug 26, 2004Conley John F.Reactive gate electrode conductive barrier
US20040214399 *Apr 22, 2003Oct 28, 2004Micron Technology, Inc.Atomic layer deposited ZrTiO4 films
US20040217410 *May 26, 2004Nov 4, 2004Micron Technology, Inc.Enhanced atomic layer deposition
US20040238859 *Jun 18, 2004Dec 2, 2004Igor PolishchukDual work function CMOS gate technology based on metal interdiffusion
US20050042373 *Aug 18, 2003Feb 24, 2005Kraus Brenda D.Atomic layer deposition methods of forming conductive metal nitride comprising layers
US20050064636 *Sep 24, 2003Mar 24, 2005Cyril CabralMethod and apparatus for fabricating CMOS field effect transistors
US20050127461 *Nov 24, 2004Jun 16, 2005Dey Sandwip K.Molecular modifications of metal/dielectric interfaces
US20060011949 *Jun 24, 2005Jan 19, 2006Chih-Wei YangMetal-gate cmos device and fabrication method of making same
US20060113603 *Dec 1, 2004Jun 1, 2006Amberwave Systems CorporationHybrid semiconductor-on-insulator structures and related methods
US20060113605 *Dec 1, 2004Jun 1, 2006Amberwave Systems CorporationHybrid fin field-effect transistor structures and related methods
US20060134870 *Dec 20, 2004Jun 22, 2006Hongfa LuanTransistor device and method of manufacture thereof
US20060237796 *Apr 21, 2005Oct 26, 2006International Business Machines CorporationUsing metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices
US20070020923 *Jul 20, 2005Jan 25, 2007Micron Technology, Inc.ALD formed titanium nitride films
US20070111448 *Nov 15, 2005May 17, 2007Hong-Jyh LiSemiconductor devices and methods of manufacture thereof
US20070141797 *Dec 16, 2005Jun 21, 2007Hong-Jyh LiSemiconductor devices and methods of manufacture thereof
US20070164367 *Jan 18, 2006Jul 19, 2007Micron Technology, Inc.CMOS gates with solid-solution alloy tunable work functions
US20070200243 *Apr 30, 2007Aug 30, 2007Micron Technology, Inc.Ald formed titanium nitride films
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6970053May 22, 2003Nov 29, 2005Micron Technology, Inc.Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection
US7030001Apr 19, 2004Apr 18, 2006Freescale Semiconductor, Inc.Method for forming a gate electrode having a metal
US7154354Feb 22, 2005Dec 26, 2006Micron Technology, Inc.High permeability layered magnetic films to reduce noise in high speed interconnection
US7662729Feb 16, 2010Micron Technology, Inc.Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US7670646Mar 2, 2010Micron Technology, Inc.Methods for atomic-layer deposition
US7687409Mar 30, 2010Micron Technology, Inc.Atomic layer deposited titanium silicon oxide films
US7709402Feb 16, 2006May 4, 2010Micron Technology, Inc.Conductive layers for hafnium silicon oxynitride films
US7719065Aug 29, 2005May 18, 2010Micron Technology, Inc.Ruthenium layer for a dielectric layer containing a lanthanide oxide
US7867919Dec 8, 2006Jan 11, 2011Micron Technology, Inc.Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer
US7915174Jul 22, 2008Mar 29, 2011Micron Technology, Inc.Dielectric stack containing lanthanum and hafnium
US8067794May 3, 2010Nov 29, 2011Micron Technology, Inc.Conductive layers for hafnium silicon oxynitride films
US8071476Dec 6, 2011Micron Technology, Inc.Cobalt titanium oxide dielectric films
US8076249Mar 24, 2010Dec 13, 2011Micron Technology, Inc.Structures containing titanium silicon oxide
US8084370Oct 19, 2009Dec 27, 2011Micron Technology, Inc.Hafnium tantalum oxynitride dielectric
US8084808May 20, 2008Dec 27, 2011Micron Technology, Inc.Zirconium silicon oxide films
US8237216Aug 7, 2012Micron Technology, Inc.Apparatus having a lanthanum-metal oxide semiconductor device
US8278225Oct 2, 2012Micron Technology, Inc.Hafnium tantalum oxide dielectrics
US8399365Dec 12, 2011Mar 19, 2013Micron Technology, Inc.Methods of forming titanium silicon oxide
US8455959Dec 5, 2011Jun 4, 2013Micron Technology, Inc.Apparatus containing cobalt titanium oxide
US8466016Dec 20, 2011Jun 18, 2013Micron Technolgy, Inc.Hafnium tantalum oxynitride dielectric
US8501563Sep 13, 2012Aug 6, 2013Micron Technology, Inc.Devices with nanocrystals and methods of formation
US8524618Sep 13, 2012Sep 3, 2013Micron Technology, Inc.Hafnium tantalum oxide dielectrics
US8558325May 17, 2010Oct 15, 2013Micron Technology, Inc.Ruthenium for a dielectric containing a lanthanide
US8633110Nov 14, 2011Jan 21, 2014Micron Technology, Inc.Titanium nitride films
US8759170Jun 11, 2013Jun 24, 2014Micron Technology, Inc.Hafnium tantalum oxynitride dielectric
US8785312Nov 28, 2011Jul 22, 2014Micron Technology, Inc.Conductive layers for hafnium silicon oxynitride
US8786031Feb 28, 2011Jul 22, 2014Canon Anelva CorporationMetal nitride film, semiconductor device using the metal nitride film, and manufacturing method of semiconductor device
US8895442Jun 3, 2013Nov 25, 2014Micron Technology, Inc.Cobalt titanium oxide dielectric films
US8907486Oct 11, 2013Dec 9, 2014Micron Technology, Inc.Ruthenium for a dielectric containing a lanthanide
US8921914Aug 5, 2013Dec 30, 2014Micron Technology, Inc.Devices with nanocrystals and methods of formation
US20040036129 *Aug 22, 2002Feb 26, 2004Micron Technology, Inc.Atomic layer deposition of CMOS gates with variable work functions
US20040233010 *May 22, 2003Nov 25, 2004Salman AkramAtomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection
US20050140462 *Feb 22, 2005Jun 30, 2005Micron Technology, Inc.High permeability layered magnetic films to reduce noise in high speed interconnection
US20050179097 *Jan 20, 2005Aug 18, 2005Micron Technology, Inc.Atomic layer deposition of CMOS gates with variable work functions
US20050233562 *Apr 19, 2004Oct 20, 2005Adetutu Olubunmi OMethod for forming a gate electrode having a metal
US20060111147 *May 20, 2005May 25, 2006Nextel Communications, Inc.Sim card data transfer system and methods
US20070049054 *Aug 31, 2005Mar 1, 2007Micron Technology, Inc.Cobalt titanium oxide dielectric films
US20070164323 *Jan 18, 2006Jul 19, 2007Micron Technology, Inc.CMOS gates with intermetallic compound tunable work functions
US20110210405 *Sep 1, 2011Canon Anelva CorporationMetal nitride film, semiconductor device using the metal nitride film, and manufacturing method of semiconductor device
WO2005106938A1 *Mar 22, 2005Nov 10, 2005Freescale Semiconductor, Inc.Method for forming a gate electrode having a metal
Classifications
U.S. Classification257/407, 257/E21.171, 257/E29.16, 257/E21.204, 257/E21.635
International ClassificationH01L29/49, H01L27/092, H01L21/285, H01L21/28, H01L27/10, H01L29/423, H01L21/8238, H01L29/78
Cooperative ClassificationH01L21/28088, H01L21/28562, H01L29/4966, H01L21/823828
European ClassificationH01L21/8238G, H01L21/285B4H2, H01L21/28E2B6, H01L29/49E
Legal Events
DateCodeEventDescription
Jan 9, 2004ASAssignment
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FORBES, LEONARD;AHN, KIE Y.;REEL/FRAME:014897/0046;SIGNING DATES FROM 20031231 TO 20040102