Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20040142523 A1
Publication typeApplication
Application numberUS 10/754,276
Publication dateJul 22, 2004
Filing dateJan 8, 2004
Priority dateAug 16, 2000
Also published asUS6696726
Publication number10754276, 754276, US 2004/0142523 A1, US 2004/142523 A1, US 20040142523 A1, US 20040142523A1, US 2004142523 A1, US 2004142523A1, US-A1-20040142523, US-A1-2004142523, US2004/0142523A1, US2004/142523A1, US20040142523 A1, US20040142523A1, US2004142523 A1, US2004142523A1
InventorsIzak Bencuya, Brian Mo, Ashok Challa
Original AssigneeIzak Bencuya, Mo Brian Sze-Ki, Ashok Challa
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method of forming vertical mosfet with ultra-low on-resistance and low gate charge
US 20040142523 A1
Abstract
A vertical trench double-diffused metal-oxide-semiconductor (DMOS) field effect transistor characterized by a reduced drain-to-source resistance and a lower gate charge and providing a high transconductance and an enhanced frequency response.
Images(10)
Previous page
Next page
Claims(22)
What is claimed is:
1. A method of forming a field effect transistor, comprising:
providing a silicon substrate of a first conductivity type;
forming a substrate cap layer of the first conductivity type over the silicon substrate;
epitaxially forming a body layer of a second conductivity type over the substrate cap layer;
forming a trench extending through the body layer and the substrate cap layer, the trench having a bottom and sidewalls; and
forming a source region of the first conductivity type in the body layer adjacent the trench,
wherein a substrate out-diffusion region of the first conductivity type is formed between the substrate cap layer and the source regions such that a spacing between each source region and the substrate out-diffusion region defines a channel length of the field effect transistor.
2. The method of claim 1 further comprising:
lining the sidewalls and bottom of the trench with a dielectric material; and
lining the dielectric material with a conductive material and substantially filling the trench with the conductive material.
3. The method of claim 2 wherein a thickness of the dielectric material at the bottom of the trench is thicker than a thickness of the dielectric material on the sidewalls of the trench.
4. The method of claim 2 further comprising:
forming a dielectric plug at the bottom of each trench using high density plasma chemical vapor deposition.
5. The method of claim 2 further comprising:
forming a dielectric plug at the bottom of each trench using sub-atmospheric chemical vapor deposition.
6. The method of claim 2 wherein:
the trench extends through the substrate out-diffusion region, and
the conductive material in the trench extends through a substantial depth of the substrate out-diffusion region.
7. The method of claim 1 wherein the trench extends partially into the silicon substrate.
8. The method of claim 1 wherein the substrate out-diffusion region has a graded doping concentration decreasing from a surface of the substrate out-diffusion region at an interface between the substrate out-diffusion region and the substrate cap layer to an opposing surface of the substrate out-diffusion region.
9. The method of claim 1 wherein the substrate cap layer has a lower doping concentration than that of the silicon substrate.
10. The method of claim 1 wherein the channel length extends vertically along a sidewall of the trench.
11. The method of claim 1 further comprising:
administering a channel implant to change a threshold voltage of the field effect transistor.
12. A method of forming a field effect transistor, comprising:
providing a silicon substrate of a first conductivity type;
forming a substrate cap layer of the first conductivity type over the silicon substrate;
epitaxially forming a body layer of a second conductivity type over the substrate cap layer;
forming a plurality of trenches each extending through the body layer and the substrate cap layer, each trench having a bottom and sidewalls;
lining the sidewalls and bottom of each trench with a dielectric material;
lining the dielectric material with a conductive material and substantially filling each trench with the conductive material; and
forming a plurality of source regions of the first conductivity type in the body layer adjacent the plurality of trenches,
wherein a substrate out-diffusion region of the first conductivity type is formed such that a spacing between each source region and the substrate out-diffusion region defines a channel length of the field effect transistor, the channel length extending vertically along a sidewall of each trench.
13. The method of claim 12 wherein:
the plurality of trenches extend through the substrate out-diffusion region, and
the conductive material in each trench extends through a substantial depth of the substrate out-diffusion region.
14. The method of claim 12 wherein the dielectric material in each trench is thicker along the bottom of each trench than along the sidewalls of each trench.
15. The method of claim 12 further comprising:
forming a dielectric plug along the bottom of each trench so that each trench has a thicker dielectric material along its bottom than along its sidewalls.
16. The method of claim 15 wherein the dielectric plug in each trench is formed using high density plasma chemical vapor deposition.
17. The method of claim 16 wherein the dielectric plug in each trench is formed using sub-atmospheric chemical vapor deposition.
18. The method of claim 12 wherein the substrate out-diffusion region has a graded doping concentration decreasing from a surface of the substrate out-diffusion region at an interface between the substrate out-diffusion region and the substrate cap layer to an opposing surface of the substrate out-diffusion region.
19. The method of claim 18 wherein the substrate cap layer has a lower doping concentration than that of the silicon substrate.
20. The method of claim 12 wherein each trench extends partially into the silicon substrate.
21. The method of claim 12 wherein the substrate out-diffusion region has a thickness of less than or equal to one micrometer.
22. The method of claim 12 further comprising:
administering a channel implant to change a threshold voltage of the field. effect transistor.
Description
    CROSS-REFERENCES TO RELATED APPLICATIONS
  • [0001]
    This application is a divisional of U.S. application Ser. No. 09/640,955, filed Aug. 16, 2000, now U.S. Pat. No. ______, entitled “Vertical MOSFET with Ultra-low Resistance and Low Gate Charge”, which disclosure is incorporated herein by reference. A first related application is U.S. application Ser. No. 09/640,954 in the names of Henry W. Hurst et al., and entitled “A Method of Creating Thick Oxide on the Bottom Surface of a Trench Structure in Silicon” and assigned to the present assignee. A second related application is U.S. application Ser. No. 09/640,496 in the name of James J. Murphy, and entitled “Selective Oxide Deposition in the Bottom of a Trench” and assigned to the present assignee. Both of these applications are incorporated by reference for all purposes.
  • STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
  • [0002]
    NOT APPLICABLE
  • REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAM LISTING APPENDIX SUBMITTED ON A COMPACT DISK
  • [0003]
    NOT APPLICABLE
  • BACKGROUND OF THE INVENTION
  • [0004]
    The present invention relates to field effect transistors (FETs) and, in particular, to trench double-diffused metal-oxide-semiconductor (DMOS) transistors and methods of fabricating the same.
  • [0005]
    Power Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are well known in the semiconductor industry. One type of MOSFET is a double-diffused trench MOSFET, or what is known as a “trench DMOS” transistor. A cross-sectional view of a portion of a typical n-channel trench DMOS transistor 10 is shown in FIG. 1. It should be pointed out that the relative thickness of the various layers are not necessarily drawn to scale.
  • [0006]
    The trench DMOS transistor 10, shown in FIG. 1, includes an n-type substrate 100 over which a substrate out-diffusion layer 101 is formed. An n-type epitaxial layer 102 is formed over substrate out-diffusion layer 101 and a p-type body layer 108 covers epitaxial layer 102. One or more trenches 109 extend through the body layer 108 and a portion of the epitaxial layer 102. Gate oxide layer 104 lines the sidewalls and bottom of each trench 109 and a conductive material 106, typically doped polysilicon, lines gate oxide layer 104 and fills each trench 109. N+ source regions 110 flank each trench 109 and extend a predetermined distance into body layer 108. Heavy body regions 112 are positioned within body layer 108, between source regions 110, and extend a predetermined distance into body layer 108. Finally, dielectric caps 114 cover the filled trenches 109 and also partially cover source regions 110. Note that trench DMOS transistor 10 also typically includes one or more metal layers, which contact source regions 110, with adjacent metal layers separated by an insulating material. These metal layers are not shown in FIG. 1.
  • [0007]
    [0007]FIG. 2 shows a doping concentration profile, taken along a cross-section labeled “xx” in FIG. 1. Cross section xx is representative of the resistance path 116 that a drain-to-source current, IDS, encounters as charge carriers travel from source region 110 to the drain of trench DMOS transistor 10, when trench DMOS transistor is on. The various regions that comprise path 116 are source region 110, body region 108, epitaxial layer 102, substrate out-diffusion layer 101 and substrate 100.
  • [0008]
    The resistance encountered by IDS due to the presence of these various regions is typically quantified as the drain-to-source resistance, RDS(on). A high drain-to-source resistance, i.e. RDS(on), limits certain performance characteristics of the transistor. For example, both the transconductance, gm, of the device, which is a measure of the current carrying capability of the device (given a certain gate voltage) and the frequency response of the device, which characterizes the speed of the device, are reduced the higher RDS(on) is. Another factor that limits the speed of the trench DMOS transistor is the gate oxide charge, Qg. The higher Qg is the larger the gate-to-drain overlap capacitance becomes and, consequently, the lower the switching capability of the device becomes.
  • [0009]
    Because the drain-source voltage is dropped almost entirely across the channel region, which comprises the body and epitaxial layers, the channel length, channel resistance and channel concentration profile are critical characteristics that affect the operating performance of a trench MOSFET. Whereas the absolute values of these characteristics are important, so too is the controllability of their variation. Wide device-to-device variations negatively affect the reproducibility of a device having desired performance capabilities.
  • BRIEF SUMMARY OF THE INVENTION
  • [0010]
    Generally, according to an exemplary embodiment of the present invention a trench DMOS transistor and its method of manufacture is provided. The trench DMOS transistor is characterized by an ultra-low on resistance (i.e., RDS(on)) and a low gate charge. The method of manufacture minimizes variations in the transistor characteristics by controlling out-diffusion from the substrate.
  • [0011]
    In a first aspect of the invention, a trench DMOS transistor is disclosed. In an exemplary embodiment the trench DMOS transistor comprises a substrate having a first conductivity type that embodies a drain layer of the transistor, the substrate having a substrate doping concentration; a substrate out-diffusion layer formed over the substrate, the substrate out-diffusion layer having a first major surface closest to the substrate that has a doping concentration approximately equal to that of the substrate doping concentration and a second major surface having a lower concentration than the substrate doping concentration; a body region having a second conductivity type, which is epitaxially formed over the substrate; at least one trench having a bottom and sidewalls, each trench extending through the substrate out-diffusion layer and the body region; a dielectric material lining the sidewalls and bottom of the at least one trench; a conductive material lining the dielectric material and substantially filling the trenches; and source regions having the first conductivity type positioned next to each trench within the body region.
  • [0012]
    In a second aspect of the invention, a substrate cap layer is positioned between the substrate and the substrate out-diffusion layer in the trench DMOS transistor described in reference to the first aspect of the invention.
  • [0013]
    In a third aspect of the invention, the thickness of the dielectric material at the bottom of the trenches is thicker than a thickness of the dielectric material on the sidewalls of the trenches so that improved gate charge performance is realized.
  • [0014]
    In a fourth aspect of the invention, a method of fabricating a trench DMOS transistor is disclosed. The method comprises providing a substrate having a first conductivity type that embodies a drain layer of the transistor, the substrate having a substrate doping concentration; forming a substrate out-diffusion layer over the substrate, the substrate out-diffusion layer having a first major surface closest to the substrate that has a doping concentration approximately equal to that of the substrate doping concentration and a second major surface having a lower concentration than the substrate doping concentration; forming a body region having a second conductivity type over the substrate; forming one or more trenches through the substrate out-diffusion layer and the body region, each trench having a bottom and sidewalls; forming a dielectric plug at the bottom of each trench; lining the sidewalls and bottom of each trench with a dielectric material; lining the dielectric material with a conductive material and substantially filling the trenches with the conductive material; and forming source regions having the first conductivity type positioned next to each trench within the body region.
  • [0015]
    In a fifth aspect of the invention, the dielectric plug described in reference to the fourth aspect of the invention is formed either by high density plasma chemical vapor deposition or sub-atmospheric chemical vapor deposition.
  • [0016]
    A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0017]
    [0017]FIG. 1 shows a cross-sectional view of a conventional trench DMOS transistor;
  • [0018]
    [0018]FIG. 2 shows a doping concentration profile, taken along a cross-section labeled “xx” in FIG. 1, of the trench DMOS transistor shown in FIG. 1;
  • [0019]
    [0019]FIG. 3 shows a cross-sectional view of an exemplary n-channel trench DMOS transistor 30 according to one embodiment of the present invention;
  • [0020]
    [0020]FIG. 4 shows an exemplary doping concentration profile, taken along a cross-section labeled “yy” in FIG. 3, of the trench DMOS transistor shown in FIG. 3;
  • [0021]
    [0021]FIG. 5 shows an exemplary process flow, according to another aspect of the invention, for fabricating the trench DMOS transistor shown in FIG. 3; and
  • [0022]
    FIGS. 6A-6K show cross-sectional views of the formation of the trench DMOS transistor according to the process flow shown in FIG. 5.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0023]
    The present invention is directed at a trench MOSFET device, and its method of manufacture, that can be used in applications such as cellular phone power supplies, battery switching. The trench MOSFET of the present invention is defined by a structure having a low drain-to-source resistance, low gate charge and a method of fabrication that minimizes device-to-device variations in operating characteristics by controlling out-diffusion from the transistor substrate.
  • [0024]
    [0024]FIG. 3 shows a cross-sectional illustration of an exemplary n-channel trench DMOS transistor 30 according to one embodiment of the present invention. Trench DMOS transistor 30 includes an n-type substrate 300, which has a resistivity of, for example, 1-5 mΩ-cm, over which a substrate cap layer 301 is formed. Substrate cap layer 301 is heavily doped and has a resistivity of, for example, 1 mΩ-cm. Substrate cap layer 301 functions to provide a more constant resistivity range than what substrate vendors typically guarantee. For example, substrate vendors typically guarantee that the resistivity of an Arsenic n-type substrate be only somewhere within the range of 1-5 mΩ-cm. As explained below, the more precisely controlled resistivity of substrate cap layer 301, relative to substrate resistivities, ensures a more predictable and stable channel length.
  • [0025]
    A substrate out-diffusion layer 302 is formed over substrate cap layer 301. Substrate cap layer 301 functions to better control and reduce the channel length of trench DMOS transistor 30 by inhibiting substrate out-diffusion. Better control of the channel length leads to a more predictable and reproducible RDS(on), Qg and breakdown voltage. A p-type body 308 is formed over substrate out-diffusion layer 302. The thickness and resistivity of p-type body are, for example, 4 μm and 0.1 Ω-cm, respectively. One or more trenches 309 extend through the body layer 308, substrate out-diffusion layer 302, substrate cap layer 301 and, preferably, a portion of substrate 300. Gate oxide layer 304 lines the sidewalls and bottom of each trench 309 and a conductive material 306, for example, doped polysilicon, lines gate oxide layer 304 and fills each trench 309. The thickness of gate oxide layer 304 is preferably thicker at the bottom of each trench 309 than on the sidewalls of the trench 309.
  • [0026]
    N+ source regions 310 flank each trench 309 and extend a predetermined distance into body layer 308. Heavy body regions 312 are positioned within body layer 308, between source regions 310, and extend a predetermined distance into body layer 308. Finally, dielectric caps 314 cover the filled trenches 309 and also partially cover source regions 310.
  • [0027]
    Trench DMOS transistor 30 also includes one or more metal layers, which contact source regions 310, with adjacent metal layers separated by an insulating material. These metal layers are not shown in FIG. 3.
  • [0028]
    Comparing trench DMOS transistor 30 to the trench DMOS transistor 10 in FIG. 1 reveals some important distinctions. First, as was described above, it is preferred that the thickness of gate oxide layer 304 be larger at the bottoms of each trench 309 than on the sidewalls of each trench 309. The reason for this is that a thicker gate oxide at the bottom trenches 309 alleviates high electric fields in the vicinity of the bottom of trenches 309, thereby providing a higher breakdown voltage, BVdss. The relatively greater thickness also has the effect of reducing the drain overlap capacitance, so that the gate charge, Qg, is reduced.
  • [0029]
    Second, trench DMOS transistor 30 does not incorporate an n-type epitaxial layer as trench DMOS transistor 10 does (see, layer 102 in FIG. 1). The primary purpose of the epitaxial layer is to provide a region for depletion to avoid reach through. However, while not necessarily limited to, the trench DMOS transistor of the present invention is envisioned to be mainly for low voltage applications. A benefit of the absence of any n-type epitaxial layer in trench DMOS transistor 30 is that a reduced current path is realized so that RDS(on) is lowered. As explained above, a lower RDS(on) improves certain performance capabilities of the device, which are characterized by, for example, a higher transconductance, gm, and an improved frequency response.
  • [0030]
    Finally, body 308 is formed by epitaxial deposition, as compared to an implant/diffusion process as used in the manufacture of the trench DMOS transistor shown in FIG. 1. The diffusion step in the manufacture of a trench DMOS is typically performed at high temperature and operates to drive all junctions, including the substrate out-diffusion layer 102, for example, in the trench DMOS transistor shown in FIG. 1. A typical diffusion cycle used in the manufacture of the trench DMOS transistor 10 of FIG. 1 can result in a substrate out-diffusion layer thickness of over 2 μm. Because a diffusion cycle is not required for forming body 308 of trench DMOS transistor 30, the thickness of substrate out-diffusion layer 302 can be made much thinner, for example approximately less than or equal to 1 μm. Moreover, for a given channel length, channel 318 can hold more charge than that of a conventional trench DMOS transistor having a body formed using an implant/diffusion process. Because the channel 318 of trench DMOS transistor 30 can hold more charge, it is less likely that drain-to-source punch-through will occur. Hence, the channel length of channel 318 of trench DMOS 30 can be reduced. The reduction in length of channel 318 and substrate out-diffusion layer 302, reduce the overall distance of the drain/source path, so that a lower RDS(on) is realized.
  • [0031]
    Referring now to FIG. 4, there is shown an exemplary doping concentration profile, taken along a cross-section labeled “yy,” for the trench DMOS transistor 30 shown in FIG. 3. Comparing this doping profile to the doping profile of a conventional trench DMOS transistor, shows that (1) there is no n-type epitaxial layer used in the trench DMOS transistor 30 of the present invention; (2) the channel length of the trench DMOS transistor 30 of the present invention is shorter; and (3) the substrate out-diffusion layer is shorter and has a steeper concentration gradient for the trench DMOS transistor 30 of the present invention. All of these characteristics have the effect of reducing the overall drain to source current path, thereby making RDS(on) smaller.
  • [0032]
    Referring now to FIG. 5, there is shown an exemplary process flow, according to another aspect of the invention, for fabricating a trench DMOS transistor. This process flow can be used, for example, to fabricate the trench DMOS transistor shown in FIG. 3. The process flow shown in FIG. 5 will now be described in reference to FIGS. 6A through 6K.
  • [0033]
    The first step, 500, a substrate 300, having a resistivity of, for example 1 to 5 mΩ-cm is provided. This is shown in FIG. 6A. Next, in step 502, a substrate cap layer 301 is formed over the substrate 300. Substrate cap layer 301 has a resistivity of, for example less than or approximately equal to 1 mΩ-cm and a thickness of approximately 1 μm. The structure following step 502 is shown in FIG. 6B.
  • [0034]
    Following formation of cap layer 301 in step 502 a substrate out-diffusion layer 302 is formed over substrate cap layer 301. This is shown in FIG. 6C. In an alternative embodiment, an out-diffusion layer is formed coincidentally as various high-temperature processing steps (e.g. steps 530 and 532 in FIG. 5) performed later in the fabrication process. In step 504 a p-type body region 308 is formed over substrate out-diffusion layer 302. Body region is formed, for example, using an implant and drive in process, using boron as the dopant with a dose of about 1E12 to 1E15 cm-2. Following the drive in, body region 308 has a depth of approximately 4 μm. The structure following step 504 is shown in FIG. 6D. Next, in step 506 an initial oxide layer is formed over the p-type body region 308, over which an active area of transistor 30 is defined using, for example, standard photolithography.
  • [0035]
    After the active area has been defined, in step 508 trenches 309 are formed. Preferably, an anisotropic etch is used to create trenches 309. The anisotropic etch is in the form of a plasma, which is an almost neutral mixture of energetic molecules, ions and electrons that have been excited in a radio-frequency electric field. Different gases are used depending on the material to be etched. The principal consideration is that the reaction products must be volatile. For etching silicon, the reactants may be, for example, He:O2, NF3 and HBr the pressure may be, for example, 140 mTorr and the duration of the etch may be approximately 3 minutes. In this example, the trenches have a depth of approximately 2.5 μm. As shown in FIG. 6E, each trench 309 extends vertically downward from an exposed surface of body region 308, into and through body region 308, through substrate out-diffusion layer 302, through substrate cap layer 301 and partially into substrate 300.
  • [0036]
    Next in the process, an oxide plug 303 is formed at the bottom of each trench 309. These oxide plugs 303 can be formed in a variety of ways. In a first embodiment of the invention to this regard, in step 510, sub-atmospheric chemical vapor deposition (SA-CVD) is used to deposit oxide on the sidewalls, bottom and over the upper and lower corners of each trench 309. Then, in step 512, the oxide is etched back so that only an oxide plug 303 remains at the bottom of each trench 309. At this stage in the process a sacrificial oxide, having a thickness of about 500 Å may be deposited (step 514) and then stripped (step 516) to prepare the trench sidewalls for a gate oxide. These sacrificial oxide and strip steps are optional. The oxide plug 303 can be alternatively formed using a process known as high-density plasma chemical vapor deposition (HDP-CVD). Using this process, in step 520, oxide is deposited on the sidewalls, bottom and over the upper and lower corners of each trench 309. Then, in step 522, the oxide is etched back using a wet etch to leave an oxide plug 303 at the bottom of each trench 309. The structure following formation of oxide plugs 303 is shown in FIG. 6F.
  • [0037]
    Next, in optional step 526, the threshold voltage of the structure can be adjusted by administering a p-type implant having, for example, an energy and dose of 70 keV and 3E13 cm-2, respectively.
  • [0038]
    After trenches 309 are formed with the oxide plugs 303, a gate oxide 304 is formed on the sidewalls of trenches 309 as is shown in FIG. 6G. The thickness of gate oxide 304 in this example, is preferably about 200 Å. Following formation of gate oxide 304, in step 528, trenches 309 are lined and filled with polysilicon and then doped using, for example, an n-type implant or by administering a conventional POCL3 doping process. Doping can also be performed using an in-situ process, i.e., as the polysilicon is deposited. The structure following step 528 is shown in FIG. 6H.
  • [0039]
    Next in another optional step 530, a p+ heavy body region 312 can be formed between adjacent trenches 309. In this example, a surface through which heavy body region 312 is to be formed is defined using, for example, conventional photolithography. Through this surface, two separate p-type (e.g., boron) implants are performed, although in some applications a single implant may be sufficient. In this example, a first implant is performed at a dose and energy of, for example, 2E15 cm-2 and 135 keV, respectively and a second implant is performed at a dose and energy of 5E14 cm-2 and 70 keV, respectively. The primary purpose of the first implant is to bring the depth of heavy body region 312 as deep as is necessary to compensate for the n+ source region, which is formed later in the process. The second implant has a low energy but a high dose. The purpose of this implant is to extend high concentration of the p+ heavy body from the first implant to the surface so that an ohmic contact can be formed. The dose is made high enough to accomplish this but not so high as to overcompensate the n+ source region, which is formed later in the process. In an alternative embodiment, heavy body region can be formed following a contact defining step (step 536), which is performed later in the process.
  • [0040]
    In step 532 a source region 310 is formed. Similar to formation of heavy body region 312, in this example a double implant is used. In this example, a surface through which source region 310 is to be formed is defined using, for example, conventional photolithography. Through this surface, two separate n-type implants are performed, although in some applications a single implant may be sufficient. In this example, a first implant of arsenic is performed at a dose and energy of, for example, 8E15 cm-2 and 80 keV, respectively and a second implant of phosphorous is performed at a dose and energy of 5E15 cm-2 and 60 keV, respectively. The purpose of the first implant is to form a source region 310 and the purpose of the second implant is to extend source region 310 to the surface so that a source contact can be formed. The structure following formation of source region 310 is shown in FIG. 6J.
  • [0041]
    Whereas the above description described formation of heavy body region 312 prior to the formation of source region 310, in an alternative embodiment the source region could be formed before formation of the heavy body region.
  • [0042]
    Next, in step 534, an insulating layer, e.g., borophosphosilicate glass, having a thickness in the range of about 5 to 15 kÅ is deposited over the exposed surface of the entire structure. Then the insulating layer is densified or “flowed”.
  • [0043]
    In step 536, the insulating layer is patterned and etched using, for example, standard photolithography, to define electrical contact areas for the trench DMOS structure. As shown in FIG. 6K, the etch is controlled to preserve insulating caps 314 over trenches 309. Following step 536, metallization and passivation steps are performed, although they are not shown in the process diagramed in FIGS. 5 and 6. One skilled in the art would understand, however, what is necessary to perform these steps.
  • [0044]
    Although the invention has been described in terms of a specific process and structure, it will be obvious to those skilled in the art that many modifications and alterations may be made to the disclosed embodiment without departing from the invention. For example, one of skill in the art would understand that one could begin with a p-type substrate to manufacture a p-channel trench DMOS, which has silicon layer with complementary doping relative to the trench DMOS structure shown in FIG. 3. Also, all of the numbers provided for dimensions, temperatures, doping concentrations, etc. are for illustrative purposes only and may be varied to refine and/or enhance particular performance characteristics of the trench DMOS transistor. Hence, these modifications and alterations are intended to be within the spirit and scope of the invention as defined by the appended claims.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3497777 *Jun 11, 1968Feb 24, 1970Stanislas TesznerMultichannel field-effect semi-conductor device
US3564356 *Oct 24, 1968Feb 16, 1971Tektronix IncHigh voltage integrated circuit transistor
US3660697 *Feb 16, 1970May 2, 1972Bell Telephone Labor IncMonolithic semiconductor apparatus adapted for sequential charge transfer
US4002511 *Apr 16, 1975Jan 11, 1977Ibm CorporationMethod for forming masks comprising silicon nitride and novel mask structures produced thereby
US4003072 *Nov 1, 1974Jan 11, 1977Sony CorporationSemiconductor device with high voltage breakdown resistance
US4326332 *Jul 28, 1980Apr 27, 1982International Business Machines Corp.Method of making a high density V-MOS memory array
US4445202 *Nov 2, 1981Apr 24, 1984International Business Machines CorporationElectrically switchable permanent storage
US4579621 *Jun 25, 1984Apr 1, 1986Mitsubishi Denki Kabushiki KaishaSelective epitaxial growth method
US4636281 *Jun 13, 1985Jan 13, 1987Commissariat A L'energie AtomiqueProcess for the autopositioning of a local field oxide with respect to an insulating trench
US4638344 *Apr 15, 1982Jan 20, 1987Cardwell Jr Walter TJunction field-effect transistor controlled by merged depletion regions
US4639761 *Oct 25, 1985Jan 27, 1987North American Philips CorporationCombined bipolar-field effect transistor resurf devices
US4746630 *Sep 17, 1986May 24, 1988Hewlett-Packard CompanyMethod for producing recessed field oxide with improved sidewall characteristics
US4801986 *Apr 3, 1987Jan 31, 1989General Electric CompanyVertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method
US4821095 *Mar 12, 1987Apr 11, 1989General Electric CompanyInsulated gate semiconductor device with extra short grid and method of fabrication
US4823176 *Apr 3, 1987Apr 18, 1989General Electric CompanyVertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junction exhibiting increased safe operating area
US4893160 *Nov 13, 1987Jan 9, 1990Siliconix IncorporatedMethod for increasing the performance of trenched devices and the resulting structure
US4914058 *Dec 29, 1987Apr 3, 1990Siliconix IncorporatedGrooved DMOS process with varying gate dielectric thickness
US4990463 *Jun 29, 1989Feb 5, 1991Kabushiki Kaisha ToshibaMethod of manufacturing capacitor
US4992390 *Jul 6, 1989Feb 12, 1991General Electric CompanyTrench gate structure with thick bottom oxide
US5079608 *Nov 6, 1990Jan 7, 1992Harris CorporationPower MOSFET transistor circuit with active clamp
US5105243 *Aug 25, 1989Apr 14, 1992Kabushiki Kaisha ToshibaConductivity-modulation metal oxide field effect transistor with single gate structure
US5111253 *Aug 28, 1990May 5, 1992General Electric CompanyMulticellular FET having a Schottky diode merged therewith
US5275965 *Nov 25, 1992Jan 4, 1994Micron Semiconductor, Inc.Trench isolation using gated sidewalls
US5294824 *Jul 31, 1992Mar 15, 1994Motorola, Inc.High voltage transistor having reduced on-resistance
US5298761 *Jun 16, 1992Mar 29, 1994Nikon CorporationMethod and apparatus for exposure process
US5298781 *Jul 8, 1992Mar 29, 1994Siliconix IncorporatedVertical current flow field effect transistor with thick insulator over non-channel areas
US5300447 *Sep 29, 1992Apr 5, 1994Texas Instruments IncorporatedMethod of manufacturing a minimum scaled transistor
US5389815 *Apr 20, 1993Feb 14, 1995Mitsubishi Denki Kabushiki KaishaSemiconductor diode with reduced recovery current
US5405794 *Jun 14, 1994Apr 11, 1995Philips Electronics North America CorporationMethod of producing VDMOS device of increased power density
US5418376 *Feb 28, 1994May 23, 1995Toyo Denki Seizo Kabushiki KaishaStatic induction semiconductor device with a distributed main electrode structure and static induction semiconductor device with a static induction main electrode shorted structure
US5519245 *May 5, 1993May 21, 1996Nippondenso Co., Ltd.Insulated gate bipolar transistor with reverse conducting current
US5592005 *Mar 31, 1995Jan 7, 1997Siliconix IncorporatedPunch-through field effect transistor
US5595927 *Mar 17, 1995Jan 21, 1997Taiwan Semiconductor Manufacturing Company Ltd.Method for making self-aligned source/drain mask ROM memory cell using trench etched channel
US5597765 *Apr 17, 1995Jan 28, 1997Siliconix IncorporatedMethod for making termination structure for power MOSFET
US5605852 *May 18, 1995Feb 25, 1997Siliconix IncorporatedMethod for fabricating high voltage transistor having trenched termination
US5616945 *Oct 13, 1995Apr 1, 1997Siliconix IncorporatedMultiple gated MOSFET for use in DC-DC converter
US5623152 *Nov 21, 1995Apr 22, 1997Mitsubishi Denki Kabushiki KaishaInsulated gate semiconductor device
US5629543 *Aug 21, 1995May 13, 1997Siliconix IncorporatedTrenched DMOS transistor with buried layer for reduced on-resistance and ruggedness
US5705409 *Sep 28, 1995Jan 6, 1998Motorola Inc.Method for forming trench transistor structure
US5710072 *May 2, 1995Jan 20, 1998Siemens AktiengesellschaftMethod of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells
US5714781 *Apr 26, 1996Feb 3, 1998Nippondenso Co., Ltd.Semiconductor device having a gate electrode in a grove and a diffused region under the grove
US5719409 *Jun 6, 1996Feb 17, 1998Cree Research, Inc.Silicon carbide metal-insulator semiconductor field effect transistor
US5877528 *Mar 3, 1997Mar 2, 1999Megamos CorporationStructure to provide effective channel-stop in termination areas for trenched power transistors
US5879971 *Sep 28, 1995Mar 9, 1999Motorola Inc.Trench random access memory cell and method of formation
US5879994 *Apr 15, 1997Mar 9, 1999National Semiconductor CorporationSelf-aligned method of fabricating terrace gate DMOS transistor
US5895951 *Apr 5, 1996Apr 20, 1999Megamos CorporationMOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches
US5895952 *Aug 21, 1996Apr 20, 1999Siliconix IncorporatedTrench MOSFET with multi-resistivity drain to provide low on-resistance
US5897343 *Mar 30, 1998Apr 27, 1999Motorola, Inc.Method of making a power switching trench MOSFET having aligned source regions
US5897360 *Oct 17, 1997Apr 27, 1999Nec CorporationManufacturing method of semiconductor integrated circuit
US5900663 *Feb 7, 1998May 4, 1999Xemod, Inc.Quasi-mesh gate structure for lateral RF MOS devices
US5906680 *Dec 24, 1996May 25, 1999International Business Machines CorporationMethod and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
US6011298 *Dec 31, 1996Jan 4, 2000Stmicroelectronics, Inc.High voltage termination with buried field-shaping region
US6015727 *Jun 8, 1998Jan 18, 2000Wanlass; Frank M.Damascene formation of borderless contact MOS transistors
US6020250 *Apr 1, 1998Feb 1, 2000International Business Machines CorporationStacked devices
US6034415 *Apr 8, 1999Mar 7, 2000Xemod, Inc.Lateral RF MOS device having a combined source structure
US6037202 *Jul 18, 1997Mar 14, 2000Motorola, Inc.Method for growing an epitaxial layer of material using a high temperature initial growth phase and a low temperature bulk growth phase
US6037628 *Jun 30, 1997Mar 14, 2000Intersil CorporationSemiconductor structures with trench contacts
US6037632 *Nov 5, 1996Mar 14, 2000Kabushiki Kaisha ToshibaSemiconductor device
US6040600 *Aug 11, 1997Mar 21, 2000Mitsubishi Denki Kabushiki KaishaTrenched high breakdown voltage semiconductor device
US6048772 *May 4, 1998Apr 11, 2000Xemod, Inc.Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection
US6049108 *Aug 28, 1997Apr 11, 2000Siliconix IncorporatedTrench-gated MOSFET with bidirectional voltage clamping
US6057558 *Mar 4, 1998May 2, 2000Denson CorporationSilicon carbide semiconductor device and manufacturing method thereof
US6168983 *Feb 5, 1999Jan 2, 2001Power Integrations, Inc.Method of making a high-voltage transistor with multiple lateral conduction layers
US6168996 *Aug 20, 1998Jan 2, 2001Hitachi, Ltd.Method of fabricating semiconductor device
US6171935 *May 24, 1999Jan 9, 2001Siemens AktiengesellschaftProcess for producing an epitaxial layer with laterally varying doping
US6174773 *Aug 27, 1999Jan 16, 2001Fuji Electric Co., Ltd.Method of manufacturing vertical trench misfet
US6174785 *Jun 18, 1998Jan 16, 2001Micron Technology, Inc.Method of forming trench isolation region for semiconductor device
US6184545 *Sep 14, 1998Feb 6, 2001Infineon Technologies AgSemiconductor component with metal-semiconductor junction with low reverse current
US6184555 *Jan 30, 1997Feb 6, 2001Siemens AktiengesellschaftField effect-controlled semiconductor component
US6188104 *Mar 27, 1998Feb 13, 2001Samsung Electronics Co., LtdTrench DMOS device having an amorphous silicon and polysilicon gate
US6188105 *Apr 1, 1999Feb 13, 2001Intersil CorporationHigh density MOS-gated power device and process for forming same
US6190978 *Apr 16, 1999Feb 20, 2001Xemod, Inc.Method for fabricating lateral RF MOS devices with enhanced RF properties
US6191447 *May 28, 1999Feb 20, 2001Micro-Ohm CorporationPower semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same
US6194741 *Nov 3, 1998Feb 27, 2001International Rectifier Corp.MOSgated trench type power semiconductor with silicon carbide substrate and increased gate breakdown voltage and reduced on-resistance
US6198127 *May 19, 1999Mar 6, 2001Intersil CorporationMOS-gated power device having extended trench and doping zone and process for forming same
US6201278 *Feb 24, 1998Mar 13, 2001Advanced Micro Devices, Inc.Trench transistor with insulative spacers
US6201279 *Oct 22, 1999Mar 13, 2001Infineon Technologies AgSemiconductor component having a small forward voltage and high blocking ability
US6204097 *Mar 1, 1999Mar 20, 2001Semiconductor Components Industries, LlcSemiconductor device and method of manufacture
US6207994 *Feb 5, 1999Mar 27, 2001Power Integrations, Inc.High-voltage transistor with multi-layer conduction region
US6222233 *Oct 4, 1999Apr 24, 2001Xemod, Inc.Lateral RF MOS device with improved drain structure
US6337499 *Aug 17, 1998Jan 8, 2002Infineon Technologies AgSemiconductor component
US6346464 *Jun 27, 2000Feb 12, 2002Kabushiki Kaisha ToshibaManufacturing method of semiconductor device
US6346469 *Jan 3, 2000Feb 12, 2002Motorola, Inc.Semiconductor device and a process for forming the semiconductor device
US6351018 *Feb 26, 1999Feb 26, 2002Fairchild Semiconductor CorporationMonolithically integrated trench MOSFET and Schottky diode
US6353252 *Jul 28, 2000Mar 5, 2002Kabushiki Kaisha ToshibaHigh breakdown voltage semiconductor device having trenched film connected to electrodes
US6359308 *Jul 24, 2000Mar 19, 2002U.S. Philips CorporationCellular trench-gate field-effect transistors
US6362112 *Nov 8, 2000Mar 26, 2002Fabtech, Inc.Single step etched moat
US6362505 *Jul 27, 2000Mar 26, 2002Siemens AktiengesellschaftMOS field-effect transistor with auxiliary electrode
US6365462 *Nov 29, 2000Apr 2, 2002Micro-Ohm CorporationMethods of forming power semiconductor devices having tapered trench-based insulating regions therein
US6365930 *Jun 1, 2000Apr 2, 2002Stmicroelectronics S.R.L.Edge termination of semiconductor devices for high voltages with resistive voltage divider
US6368920 *Jun 11, 1998Apr 9, 2002Fairchild Semiconductor CorporationTrench MOS gate device
US6368921 *Sep 28, 2000Apr 9, 2002U.S. Philips CorporationManufacture of trench-gate semiconductor devices
US6376314 *Nov 6, 1998Apr 23, 2002Zetex Plc.Method of semiconductor device fabrication
US6376878 *Feb 11, 2000Apr 23, 2002Fairchild Semiconductor CorporationMOS-gated devices with alternating zones of conductivity
US6376890 *Dec 8, 1999Apr 23, 2002Siemens AktiengesellschaftHigh-voltage edge termination for planar structures
US20020009832 *Jan 19, 2001Jan 24, 2002Blanchard Richard A.Method of fabricating high voltage power mosfet having low on-resistance
US20020014658 *May 4, 2001Feb 7, 2002Blanchard Richard A.High voltage power mosfet having low on-resistance
US20020027243 *Dec 13, 1999Mar 7, 2002Zhiqiang WuMethods of forming field effect transistors
US20030060013 *Sep 24, 1999Mar 27, 2003Bruce D. MarchantMethod of manufacturing trench field effect transistors with trenched heavy body
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8101484Jun 23, 2010Jan 24, 2012Fairchild Semiconductor CorporationMethod of forming a FET having ultra-low on-resistance and low gate charge
US8372708 *Oct 4, 2011Feb 12, 2013Anup BhallaDevice structure and manufacturing method using HDP deposited using deposited source-body implant block
US8710584Jan 5, 2012Apr 29, 2014Fairchild Semiconductor CorporationFET device having ultra-low on-resistance and low gate charge
US8907412 *Sep 16, 2013Dec 9, 2014Maxpower Semiconductor Inc.Semiconductor device
US9570570 *Jul 17, 2013Feb 14, 2017Cree, Inc.Enhanced gate dielectric for a field effect device with a trenched gate
US20120018793 *Oct 4, 2011Jan 26, 2012Anup BhallaDevice structure and manufacturing method using HDP deposited using deposited source-body implant block
US20140070308 *Sep 16, 2013Mar 13, 2014Maxpower Semiconductor, Inc.Semiconductor device
US20150021623 *Jul 17, 2013Jan 22, 2015Cree, Inc.Enhanced gate dielectric for a field effect device with a trenched gate
Classifications
U.S. Classification438/197, 257/E29.04, 438/268, 438/270, 257/E29.133, 438/289
International ClassificationH01L29/423, H01L29/08, H01L29/78, H01L21/336
Cooperative ClassificationH01L29/7813, H01L29/42368, H01L29/0847
European ClassificationH01L21/336B2T, H01L29/78B2T