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Publication numberUS20040153982 A1
Publication typeApplication
Application numberUS 10/762,790
Publication dateAug 5, 2004
Filing dateJan 23, 2004
Priority dateJan 27, 2003
Also published asUS7448003, US20070006103
Publication number10762790, 762790, US 2004/0153982 A1, US 2004/153982 A1, US 20040153982 A1, US 20040153982A1, US 2004153982 A1, US 2004153982A1, US-A1-20040153982, US-A1-2004153982, US2004/0153982A1, US2004/153982A1, US20040153982 A1, US20040153982A1, US2004153982 A1, US2004153982A1
InventorsPengfei Zhang, Xisheng Zhang, Yuping Wu
Original AssigneePengfei Zhang, Xisheng Zhang, Yuping Wu
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Signal flow driven circuit analysis and partition technique
US 20040153982 A1
Abstract
A signal flow driven circuit analysis and partition technique are provided for mixed signal circuit performance optimization, yield enhancement and layout optimization. The inventive device includes automatic partition of mixed signal integrated circuits based on functional blocks, automatic identification of critical signal path in analog/RF circuits, automatic identification of fundamental unit circuits, automatic identification of matching and symmetry requirement. Circuit partition automatically partitions a mixed signal circuit into blocks based on their functionality. Identification of signal flow is achieved by automatically tracing the signal flow and identifies the critical path based a set of rules. Various building blocks of known characteristics and optimization requirement can also be automatically obtained. By tracing the signal path, matching and symmetry requirement and parasitic loading requirement at critical circuit nodes can also be automatically generated.
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Claims(11)
1. A signal flow driven circuit analysis technique by tracing circuit signal flow so that, analyzing a circuit, and partitioning a circuit based on functionality and criticality, and generating multitude circuit layout constraints are done by software program automatically.
2. The signal flow driven circuit analysis technique of claim 1 comprising:
(a) Providing a memory that is able to store a series of rules in said memory; and
(b) Storing said series of rules in said memory; and
(c) Providing a memory that is able to store a circuit netlist employing input/output pin, any other terminal pins, power/ground terminals, active device elements, and passive device elements; and
(d) Storing said circuit netlist in said memories; and
(e) Utilizing said series of rules to trace signal flow information and perform automatic circuit analysis of said circuit netlist; and
(f) Storing said signal flow information in said memory.
3. The signal flow driven circuit analysis technique of claim 2 further including a partition technique comprising:
(a) Utilizing the signal flow driven circuit analysis technique of claim 2 wherein said signal flow information to partition the circuit netlist of claim 2 into two parts: digital part and analog/RF part; and
(b) Providing a memory that is able to store a series of critical signal flow requirements; and
(c) Storing said series of critical signal flow requirements in said memory; and
(d) Utilizing said series of critical signal flow requirements to partition said analog/RF part in two parts: a biasing circuit part and a core signal flow path; and
(e) Utilizing said series of critical signal flow requirements to identify an unit circuit of current mirror, an unit circuit of differential pairs, an unit circuit of voltage reference, unite circuit of current reference, and an unite circuit of amplifier [etc.]; and
(f) Utilizing said series of critical signal flow requirements to identify multitude critical nodes, multitude critical nets, and multitude critical components in the circuit netlist of claim 2; and
(g) Providing a memory that is able to store said critical nodes, said critical nets, and said critical components; and
(h) Storing said critical nodes, said critical nets, and said critical components in said memory.
4. The signal flow driven circuit analysis technique of claim 1 further including a physical layout constraint generation technique comprising:
(a) Proving a memory that is able to store a series of physical requirement rules; and
(b) Storing said series of physical requirement rules in said memory; and
(c) Utilizing the signal flow driven circuit analysis technique of claim 2 wherein said signal flow information, and the signal flow driven circuit partition technique of claim 3 wherein said critical nodes, said critical nets, said critical components, and said physical requirement rules to generate multitude circuit physical layout constraints of matching, abutment, symmetry, and parasitic loading; and
Whereby an engineer can layout an analog circuit, a mixed signal circuit, and a RF circuit automatically.
5. A mean of circuit performance assessment utilizing:
(a) The signal flow driven circuit analysis technique of claim 2 wherein said signal flow information; and
(b) The signal flow driven circuit partition technique of claim 3 wherein said critical nodes, and said critical nets, said critical components; and
(c) The physical layout constraint generation technique of claim 4 wherein said physical requirement rules.
6. A mean of circuit yield enhancement utilizing:
(a) The signal flow driven circuit analysis technique of claim 2 wherein said signal flow information; and
(b) The signal flow driven circuit partition technique of claim 3 wherein said critical nodes, and said critical nets, and said critical components; and
(c) The physical layout constraint generation technique of claim 4 wherein said physical requirement rules to increase yield of analog circuit, and of mixed signal circuit, and of RF circuit.
7. A circuit hierarchy regeneration technique comprising:
(a) The signal flow driven circuit analysis technique of claim 2 wherein said signal flow information; and
(b) The signal flow driven circuit partition technique of claim 3 wherein said digital part, and said analog/RF part, and biasing circuit part, and said core signal flow path, and said unit circuit; and
(c) The physical layout constraint generation technique of claim 4 wherein said circuit physical layout constraints of matching, abutment, symmetry, and parasitic loading; and
Whereby an engineer can improve an analog circuit, mixed signal circuit, and RF circuit simulation speed.
8. A circuit performance optimization technique utilizing
(a) The signal flow driven circuit analysis technique of claim 2 wherein said signal flow information; and
(b) The signal flow driven circuit partition technique of claim 3 wherein said digital part, and said analog/RF part, and biasing circuit part, and said core signal flow path, and said unit circuit; and
(c) The physical layout constraint generation technique of claim 4 wherein said circuit physical layout constraints of matching, abutment, symmetry, and parasitic loading to optimize performance of an analog circuit, and of a mixed signal circuit, and of a RF circuit.
9. A circuit physical layout optimization technique utilizing
(a) The signal flow driven circuit analysis technique of claim 2 wherein said signal flow information; and
(b) The signal flow driven circuit partition technique of claim 3 wherein said digital part, and said analog/RF part, and biasing circuit part, and said core signal flow path, and said unit circuit; and
(c) The physical layout constraint generation technique of claim 4 wherein said circuit physical layout constraints of matching, abutment, symmetry, and parasitic loading to optimize a layout of analog circuit, and of mixed signal circuit, and RF circuit.
10. A mean of circuit physical layout floor planning utilizing:
(a) The signal flow driven circuit analysis technique of claim 2 wherein said signal flow information; and
(b) The signal flow driven circuit partition technique of claim 3 wherein said digital part, and said analog/RF part, and biasing circuit part, and said core signal flow path, and said unit circuit; and
(c) The physical layout constraint generation technique of claim 4 wherein said circuit physical layout constraints of matching, abutment, symmetry, and parasitic loading to optimize a layout of analog circuit, and of mixed signal circuit, and RF circuit.
11. A mean of extracting Intellectual Property circuit cell utilizing:
(a) The signal flow driven circuit analysis technique of claim 2 wherein said signal flow information; and
(b) The signal flow driven circuit partition technique of claim 3 wherein said digital part, and said analog/RF part, and biasing circuit part, and said core signal flow path, said unit circuit; and
(c) The physical layout constraint generation technique of claim 4 wherein said circuit physical layout constraints of matching, abutment, symmetry, and parasitic loading to reuse an Intellectual Property circuit cell.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of the filing date of provisional patent application Serial No. 60/442,306 filed Jan. 27, 2003.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates generally to circuit analysis and partition and more specifically, it relates to a signal flow driven circuit analysis and partition technique for mixed-signal circuit performance optimization, yield enhancement and layout optimization.

[0004] 2. Description of the Related Art

[0005] It can be appreciated that circuit analysis and partition have been in use for years. Typically, circuit analysis and partition are comprised of manual partition of circuit blocks based on their functionality and physical requirement during the circuit design and layout stages. For RF/Analog circuit blocks, identifying the critical signal flow is either not performed or implicitly identified at the layout stages manually by layout designers. Circuit optimization is commonly performed by trial-and-error with heavy-duty emulators like SPICE or Spectre.

[0006] The main problem with conventional circuit analysis and partition are that the mixed signal circuit designs often suffer sub-optimal block level partition or no partition at all due to lack of an automated solution. This results in either compromised performance of the product or excessive physical area of the layout. Another problem with conventional circuit analysis and partition are that massive numerical simulations are needed in optimizing the performance of the circuit. Simulation can be prohibitively time and/or computation power intensive, that performance optimization may not be feasible for certain scale of circuits. Another problem with conventional circuit analysis and partition are that it is difficult to assure high quality layout, as it is up to the layout designer to manually identify the critical signal path during layout stage, which is largely dependent on designers' experience level and extremely error prone.

[0007] While these devices may be suitable for the particular purpose to which they address, they are not as suitable for mixed signal circuit performance optimization, yield enhancement and layout optimization. The main problem with conventional circuit analysis and partition are that the mixed signal circuit designs often suffer sub-optimal block level partition or no partition at all due to lack of an automated solution. This results in either compromised performance of the product or excessive physical area of the layout. Another problem is that massive numerical simulations are needed in optimizing the performance of the circuit. Simulation can be prohibitively time and/or computation power intensive, that performance optimization may not be feasible for certain scale of circuits. Also, another problem is that it is difficult to assure high quality layout, as it is up to the layout designer to manually identify the critical signal path during layout stage, which is largely dependent on designers' experience level and extremely error prone.

[0008] In these respects, the signal flow driven circuit analysis and partition technique according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of mixed signal circuit performance optimization, yield enhancement and layout optimization.

SUMMARY OF THE INVENTION

[0009] In view of the foregoing disadvantages inherent in the known types of circuit analysis and partition now present in the prior art, the present invention provides a new signal flow driven circuit analysis and partition technique construction wherein the same can be utilized for mixed signal circuit performance optimization, yield enhancement and layout optimization.

[0010] The general purpose of the present invention, which will be described subsequently in greater detail, is to provide a new signal flow driven circuit analysis and partition technique that has many of the advantages of the circuit analysis and partition mentioned heretofore and many novel features that result in a new signal flow driven circuit analysis and partition technique which is not anticipated, rendered obvious, suggested, or even implied by any of the prior art circuit analysis and partition, either alone or in any combination thereof.

[0011] To attain this, the present invention generally comprises automatic partition of mixed signal integrated circuits based on functional blocks, automatic identification of critical signal path in analog/RF circuits, automatic identification of fundamental unit circuits, automatic identification of matching and symmetry requirement. Circuit partition automatically partitions a mixed signal circuit into blocks based on their functionality. Identification of signal flow is achieved by automatically tracing the signal flow and identification of the critical path is based on a set of rules. Various building blocks of known characteristics and optimization requirement can also be automatically obtained. By tracing the signal path, matching and symmetry requirement and parasitic loading requirement at critical circuit nodes can also be automatically generated.

[0012] There has thus been outlined, rather broadly, the more important features of the invention in order that the detailed description thereof may be better understood, and in order that the present contribution to the art may be better appreciated. There are additional features of the invention that will be described hereinafter.

[0013] In this respect, before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not limited in its application to the details of construction and to the arrangements of the components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of the description and should not be regarded as limiting.

[0014] A primary object of the present invention is to provide a signal flow driven circuit analysis and partition technique that will overcome the shortcomings of the prior art devices.

[0015] An object of the present invention is to provide a signal flow driven circuit analysis method by tracing signal flow.

[0016] An object of the present invention is to provide automatic circuit partition technique based on functionality and criticality.

[0017] An object of the present invention is to provide automatic circuit analysis to identify critical nodes, critical nets, critical components for performance assessment, yield enhancement, layout constrains generation, and circuit physical layout floor planning.

[0018] An object of the present invention is to provide a signal flow driven circuit analysis and partition technique for mixed signal circuit performance optimization, yield enhancement and layout optimization.

[0019] Another object is to provide a signal flow driven circuit analysis and partition technique that automatically identifies the critical signal path in the RF/Analog integrated circuits.

[0020] Another object is to provide a signal flow driven circuit analysis and partition technique that automatically identifies fundamental circuit units such as current mirrors, differential pairs, voltage or current references and stages of amplifiers etc.

[0021] Another object is to provide a signal flow driven circuit analysis and partition technique that automatically partitions a mixed signal circuit into digital (logic) section and analog/RF section.

[0022] Another object is to provide a signal flow driven circuit analysis and partition technique that automatically identifies matching devices and symmetry requirement for layout purposes.

[0023] Another object is to provide a signal flow driven circuit analysis and partition technique that automatically partition the analog/RF circuit section to critical signal path section and biasing circuit section for layout and/or circuit optimization purposes.

[0024] Other objects and advantages of the present invention will become obvious to the reader and it is intended that these objects and advantages within the scope of the present invention.

[0025] To the accomplishment of the above and related objects, this invention may be embodied in the form illustrated in the accompanying drawings, attention being called to the fact, however, that the drawings are illustrative only, and that changes may be made in the specific construction illustrated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Various other objects, features and attendant advantages of the present invention will become fully appreciated as the same becomes better understood when considered in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the several views, and wherein:

[0027]FIG. 1 Signal Flow Driven Circuit Analysis and Partition Flow Chart

[0028]FIG. 2 Means of Circuit Performance Assessment and Circuit Yield Enhancement Flow Chart

[0029]FIG. 3 Means of Circuit Hierarchy Regeneration, Performance Optimization, Physical Layout Optimization, floor Planning, and Extracting Intellectual Property Circuit Cell Flow Chart

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Turning now descriptively to the drawings, in which similar reference characters denote similar elements throughout the several views, the attached figures illustrate a signal flow driven circuit analysis and partition technique, which comprises automatic partition of mixed signal integrated circuits based on functional blocks, automatic identification of critical signal path in analog/RF circuits, automatic identification of fundamental unit circuits, automatic identification of matching and symmetry requirement. Circuit partition automatically partitions a mixed signal circuit into blocks based on their functionality. Identification of signal flow is achieved by automatically tracing the signal flow and identifies the critical path based a set of rules. Various building blocks of known characteristics and optimization requirement can also be automatically obtained. By tracing the signal path, matching and symmetry requirement and parasitic loading requirement at critical circuit nodes can also be automatically generated.

[0031] Circuit partition automatically partitions a mixed signal circuit into blocks based on their functionality. Circuit partition is performed by tracing the input/output signals of the circuit according to a set of “tracing rules”: if a digital (analog) signal presents at the GATE of a MOSFET, then the SOURCE and DRAIN of this transistor is a digital (analog) node, unless it is terminated to supply rails (VCC or GND), denoted as: GATE—>SOURCE/DRAIN. We thus have: SOURCE—>DRAIN, DRAIN—>SOURCE, but not SOURCE or DRAIN—>GATE. On the other hand: resistors are transparent for both digital and analog signals, capacitors are transparent for analog signals but are open for digital, and inductors are mostly used as tuning load in RF circuits and rarely found in digital integrated circuits. Upon finishing of the tracing, circuit partition is obtained. Circuit partition rules can be changed to accommodate other circuit topologies or requirement.

[0032] Identification of signal flow is achieved by automatically tracing the signal flow and identifies the critical path based a set of rules. The signal flow trackers does trace signal paths in RF/analog bock based on the rules: source to drain, drain to source, gate to drain, gate to source, but not drain to gate, not source to gate, and the termination is PWR/GND pin and other signal pins. Critical signal path is thus identified as those related to the critical input and/or output pins. With modified tracing rules, other circuit topologies can be accommodated.

[0033] Various building blocks of known characteristics and optimization requirement can also be automatically obtained. Automatically identifies the fundamental unit circuit based on structure representation by signal flow analysis, unit circuits include, but not limited to, various configurations of single stage amplifiers, current mirrors, differential pairs and voltage and current references. Unit circuit identification can also be achieved with pattern matching. Unit circuit can be expanded to some more complex sub-circuits.

[0034] By tracing the signal path, matching and symmetry requirement and parasitic loading requirement at critical circuit nodes can also be automatically generated. Automatically generates physical constraints such as matching, abutment and parasitic loading by a set of rule files as defined in the operation descriptions. It is possible to perform some simple numerical circuit simulation to enhance the constraints generation.

[0035] All components in this invention can be performed in series or in parallel. Depending on the application, they each can be performed separately if so desired: signal flow tracing and circuit partition in a numerical simulator, signal flow tracing and circuit partition in a circuit synthesizer, stand-alone signal flow driven circuit partition tool.

[0036] A signal flow tracker starts from the input terminals, and traces the signals as the following: For MOSFET, gate—>drain/source, drain—>source, source—>drain; for resistor, one terminal—>another terminal; for capacitor and inductor, same as for resistor; the terminations of signal path is PWR/GND or output ports. The unit circuit explorer works in two steps: first, unit circuit characterized structure generator produces the characteristic structure information, and the structure explorer search the matched structures for specified unit circuit. The matching explorer has three modules, differential pair explorer, current source explorer, and signal-path matching explorer. The differential pair explorer tries to find the differential pair based on the differential signal path. The two sides of differential pair must be matched. The current source explorer searches for the current sources and current mirrors, where the matched transistors are identified. The signal path matching explorer searches for matched signal flow paths based on the signal flow tracing.

[0037] The non-critical device explorer has three modules, the logic signal tracker, the logic-driven-gate MOS explorer, and the capacitor-connected MOS explorer. The logic signal flow tracker traces the logic according to the given rules. The logic-driven-gate MOS explorer searches the MOSFETs whose gates are driven by the logic signals. The capacitor-connected MOS explorer searches for the MOSFETs connected as capacitors.

[0038] The bias circuit explorer has four modules, the unit circuit explorer, matching explorer, not critical device explorer, and the bias circuit re-builder. The unit circuit explorer tries to dig out all the unit circuits, to make the bias circuit hierarchy. Matching explorer tries to dig out the matching in the bias circuit. The not critical device explorer tries to dig out all the not critical devices in the bias circuit. The bias circuit re-builder tries to re-build the bias circuit with the identified unit circuit as a sub-circuit.

[0039] In the core circuit explorer, the signal flow tracker tries to separate the signal path for each critical signal; the zipper cell explorer tries to dig out the common part of the two or more signal paths, the signal path matching explorer tries to dig out the matching between two signal paths, the unit circuit explorer tries to dig out the unit circuits in the core circuit, the core circuit re-builder tries to re-build the core circuit, with the zipper cell as a sub-circuit, the un-shared part of the signal path as a sub-circuit, the unit circuit of the signal path regarded as the sub-circuit in the signal path sub-circuit, so that the core circuit is re-organized as a hierarchy circuit.

[0040] In the logic and analog/RF explorer, the signal flow tracker spread the logic signals or analog/RF signals from the input based on the given rules; the devices with all terminals driven by logic signal are partitioned into logic circuits. Others are classified into the analog/RF circuit. The logic circuit builder tries to build the logic sub-circuit; the analog circuit builder tries to build the analog/RF sub-circuit; and the whole circuit reorganized as the instantiation of the logic sub-circuit and the analog/RF sub-circuit. The logic sub-circuit will further handled by logic circuit explorer that is out of this invention.

[0041] The analog/RF circuit will be further handled by bias and core circuit partitioner. The bias and core circuit partitioner tries to partition the analog/RF circuit into bias circuit and core circuit based on the critical signal tracing. The analog/RF circuit re-organized as the instantiations of bias sub-circuit and core sub-circuit. The bias sub-circuit will be further handled by the bias circuit explorer and the core sub-circuit will be further handled by the core circuit explorer. Therefore, a circuit will be re-organized as a new hierarchy circuit with logic and analog/RF partitioned, bias and core partitioned, signal path partitioned, unit circuit identified, symmetry and matching identified, etc., which will be potentially used for speeding up circuit simulation, circuit optimization, yield improvement, efficiently controlling layout synthesis, circuit physical layout floor panning, and extracting Intellectual Property circuit cell for reuse, etc.

[0042] As to a further discussion of the manner of usage and operation of the present invention, the same should be apparent from the above description. Accordingly, no further discussion relating to the manner of usage and operation will be provided.

[0043] With respect to the above description then, it is to be realized that the optimum dimensional relationships for the parts of the invention, to include variations in size, materials, shape, form, function and manner of operation, assembly and use, are deemed readily apparent and obvious to one skilled in the art, and all equivalent relationships to those illustrated in the drawings and described in the specification are intended to be encompassed by the present invention.

[0044] Therefore, the foregoing is considered as illustrative only of the principles of the invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation shown and described, and accordingly, all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7418683 *Sep 21, 2005Aug 26, 2008Cadence Design Systems, IncConstraint assistant for circuit design
US7434183 *Aug 17, 2005Oct 7, 2008Cadence Design Systems, Inc.Method and system for validating a hierarchical simulation database
US7653524 *Aug 22, 2005Jan 26, 2010Carnegie Mellon UniversityAnalog and radio frequency (RF) system-level simulation using frequency relaxation
US7665054 *Sep 19, 2005Feb 16, 2010Cadence Design Systems, Inc.Optimizing circuit layouts by configuring rooms for placing devices
US7739646 *Aug 15, 2007Jun 15, 2010Springsoft, Inc.Analog and mixed signal IC layout system
US8024679Dec 6, 2007Sep 20, 2011International Business Machines CorporationStructure for apparatus for reduced loading of signal transmission elements
US8040813Jun 2, 2005Oct 18, 2011International Business Machines CorporationApparatus and method for reduced loading of signal transmission elements
US8527928 *Dec 23, 2009Sep 3, 2013Cadence Design Systems, Inc.Optimizing circuit layouts by configuring rooms for placing devices
US20120011483 *Jul 6, 2010Jan 12, 2012Lsi CorporationMethod of characterizing regular electronic circuits
Classifications
U.S. Classification716/115, 716/124, 716/135, 716/122
International ClassificationG06F17/50
Cooperative ClassificationG06F17/5045
European ClassificationG06F17/50D