Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20040164807 A1
Publication typeApplication
Application numberUS 10/321,222
Publication dateAug 26, 2004
Filing dateFeb 24, 2003
Priority dateFeb 24, 2003
Also published asUS6784749
Publication number10321222, 321222, US 2004/0164807 A1, US 2004/164807 A1, US 20040164807 A1, US 20040164807A1, US 2004164807 A1, US 2004164807A1, US-A1-20040164807, US-A1-2004164807, US2004/0164807A1, US2004/164807A1, US20040164807 A1, US20040164807A1, US2004164807 A1, US2004164807A1
InventorsStephen Cove
Original AssigneeCove Stephen E.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Limiting amplifier with active inductor
US 20040164807 A1
Abstract
According to some embodiments, a circuit includes a limiting amplifier, the limiting amplifier including an output node. The circuit also includes an active inductor coupled to the output node, and may exhibit a zero approximately at a frequency at which the active inductor begins to exhibit substantially inductive characteristics.
Images(6)
Previous page
Next page
Claims(20)
What is claimed is:
1. A circuit comprising:
a limiting amplifier, the limiting amplifier comprising a gain stage; and
an active inductor coupled to the gain stage.
2. A circuit according to claim 1, wherein the active inductor comprises:
a transistor; and
a resistor.
3. A circuit according to claim 2, wherein a drain of the transistor is coupled to a supply voltage, wherein a source of the transistor is coupled to an output node of the limiting amplifier, wherein a first contact point of the resistor is coupled to the supply voltage, and wherein a second contact point of the resistor is coupled to a gate of the transistor.
4. A circuit according to claim 2, wherein a value of the resistor is to establish a zero approximately at a frequency at which the active inductor begins to substantially exhibit inductive characteristics.
5. A circuit according to claim 1, wherein the gain stage includes an output node, and wherein the active inductor is coupled to the output node.
6. A circuit according to claim 1, wherein the limiting amplifier comprises:
a transconductance stage; and
a transimpedance stage,
wherein the transimpedance stage comprises the gain stage.
7. A circuit according to claim 1,
wherein the circuit is to exhibit a zero approximately at a frequency at which the active inductor begins to exhibit substantially inductive characteristics.
8. A circuit comprising:
a limiting amplifier, the limiting amplifier comprising an output node; and
an active inductor coupled to the output node.
9. A circuit according to claim 8, wherein the active inductor comprises:
a transistor; and
a resistor.
10. A circuit according to claim 9, wherein a drain of the transistor is coupled to a supply voltage, wherein a source of the transistor is coupled to the output node, wherein a first contact point of the resistor is coupled to the supply voltage, and wherein a second contact point of the resistor is coupled to a gate of the transistor.
11. A circuit according to claim 9, wherein a value of the resistor is to establish a zero approximately at a frequency at which the active inductor begins to exhibit substantially inductive characteristics.
12. A circuit according to claim 8,
wherein the circuit is to exhibit a zero approximately at a frequency at which the active inductor begins to substantially exhibit inductive characteristics.
13. A module comprising:
a limiting amplifier, the limiting amplifier comprising:
an output node; and
an active inductor coupled to the output node; and
an optical interface coupled to the limiting amplifier to receive optical signals, to convert the optical signals to electrical signals, and to transmit the electrical signals to the limiting amplifier.
14. A module according to claim 13, further comprising:
a deserializer coupled to the limiting amplifier; and
a framer coupled to the deserializer.
15. A module according to claim 13, wherein the active inductor comprises:
a transistor; and
a resistor, and
wherein a drain of the transistor is coupled to a supply voltage, wherein a source of the transistor is coupled to the output node, wherein a first contact point of the resistor is coupled to the supply voltage, and wherein a second contact point of the resistor is coupled to a gate of the transistor.
16. A circuit according to claim 13,
wherein the circuit is to exhibit a zero approximately at a frequency at which the active inductor begins to exhibit substantially inductive characteristics.
17. A module comprising:
a limiting amplifier comprising:
a gain stage; and
an active inductor coupled to the gain stage; and
an optical interface coupled to the limiting amplifier to receive optical signals, to convert the optical signals to electrical signals, and to transmit the electrical signals to the limiting amplifier.
18. A module according to claim 17, further comprising:
a deserializer coupled to the limiting amplifier; and
a framer coupled to the deserializer.
19. A module according to claim 17, wherein the active inductor comprises:
a transistor; and
a resistor, and
wherein a drain of the transistor is coupled to a supply voltage, wherein a source of the transistor is coupled to an output node of the gain stage, wherein a first contact point of the resistor is coupled to the supply voltage, and wherein a second contact point of the resistor is coupled to a gate of the transistor.
20. A circuit according to claim 19,
wherein the circuit is to exhibit a zero approximately at a frequency at which the active inductor begins to exhibit substantially inductive characteristics.
Description
BACKGROUND

[0001] Amplifiers can be generally classified as operational amplifiers or limiting amplifiers. An operational amplifier receives an input signal and generates a signal that has an amplitude different from the amplitude of the input signal. The frequency components of the generated signal are substantially identical to the frequency components of the input signal.

[0002] In contrast, a limiting amplifier receives an input signal and generates a signal having a specified peak-to-peak amplitude. The specified amplitude is identical for any input signal that is within the operating range of the limiting amplifier. In a limiting amplifier, the frequency components of the output signal may differ from the frequency components of the input signal.

[0003] Some applications require an amplifier to provide a particular gain over a particular bandwidth. In the case of a limiting amplifier, the particular gain may be represented by a minimum input signal that must be amplified to a specific peak-to-peak amplitude over the particular bandwidth. A conventional limiting amplifier is unable to suitably satisfy these requirements for some existing applications. One such application is described in the OC-192 10 Gb/s optical signaling specification.

[0004] Conventional limiting amplifiers may present other drawbacks. A conventional limiting amplifier consumes significant die space when fabricated as an integrated circuit. Moreover, the gain provided by some existing limiting amplifiers varies unacceptably with process.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005]FIG. 1a is a diagram of a limiting amplifier according to some embodiments.

[0006]FIG. 1b is a plot of a gain function of an amplifier according to some embodiments.

[0007]FIGS. 2a through 2 c comprise diagrams of active inductors according to some embodiments.

[0008]FIG. 3 is a diagram of a limiting amplifier according to some embodiments.

[0009]FIG. 4 is a diagram of a limiting amplifier according to some embodiments.

[0010]FIG. 5 is a diagram illustrating a module according to some embodiments.

DETAILED DESCRIPTION

[0011]FIG. 1a illustrates limiting amplifier 1 according to some embodiments. Limiting amplifier 1 receives two input signals, each of which is a component of a differential input signal, and generates two output signals, each of which is a component of a differential output signal. The input signals are present on the signal lines labeled IN_P and IN_N in FIG. 1. Similarly, the output signals are provided by the signal lines labeled OUT_N and OUT_P.

[0012] As shown, the input signals are applied to gates of n-channel metal-oxide semiconductor (NMOS) transistors 11 and 12. Sources of transistors 11 and 12 are coupled to one another, and are also coupled to a drain of NMOS transistor 13. A source of transistor 13 is coupled to ground, and a gate of transistor 13 receives bias voltage Vbias. Transistor 13 thereby provides a current source to limiting amplifier 1.

[0013] Active inductors 14 and 15 are coupled to a gain stage of limiting amplifier 1. In particular, active inductor 14 is coupled to output node 16 and active inductor 15 is coupled to output node 17. Active inductor 14 includes NMOS transistor 18 and resistor 19. A drain of transistor 18 is coupled to a supply voltage, and a source of transistor 18 is coupled to output node 16. A gate of transistor 18 is coupled to a first contact point of resistor 19, and a second contact point of resistor 19 is coupled to the supply voltage. Active inductor 15 is configured similarly to active inductor 14. Active inductor 15 therefore includes NMOS transistor 20 and resistor 21, with a drain of transistor 20 coupled to the supply voltage, and a source coupled to output node 17. A first contact point of resistor 21 is coupled to a gate of transistor 20, and a second contact point of resistor 21 is coupled to the supply voltage. According to some embodiments, any other type of currently- or hereafter-known active inductors may be substituted for one or both of active inductors 14 and 15.

[0014]FIG. 1b shows gain function 22 of limiting amplifier 1. Function 22 reflects the theoretical gain of limiting amplifier 1, or Vo=Vin(gmZ1), where Vin=IN_P−IN_N and Vo=OUT_P−OUT_N. Actual values represented by gain function 22 depend upon the specific components used in limiting amplifier 1 as well as the value of Vbias. As shown, values of Vo are limited to a particular value for all values of Vin that are greater than a certain value. The operating range of limiting amplifier 1 therefore includes Vin values that are greater than the certain value. For Vin values that are less than the certain value, limiting amplifier 1 provides linear amplification such as that described in the above Background section.

[0015] In some embodiments, active inductors 14 and 15 increase the bandwidth of limiting amplifier 1 over traditional limiting amplifier arrangements that include resistive loads, and consume less die space than passive inductors. Values of resistors 19 and 21 may be determined so as to set a zero at a frequency at which the transistor source impedance of their respective inductor begins to exhibit substantially inductive characteristics. For example, an impedance looking into the source of active inductor 14 is determined by R(j2π+1/RCgs)/(j2π+gm/Cgs). Some embodiments may thereby provide an inductive peak to a frequency response of limiting amplifier 1 at or before a frequency that would otherwise reflect the −3 dB bandwidth of amplifier 1. Such embodiments may allow for more stages of amplification and therefore smaller input signals than current limiting amplifiers, while maintaining bandwidth required by a particular application.

[0016] Any type of currently- or hereafter-known active inductors may be used in conjunction with some embodiments. An active device is a device that requires a source of energy for its operation. An inductor is a device characterized by the relationship Z=j2πL. Accordingly, an active inductor is a device that requires a source of energy for its operation and that substantially exhibits characteristics governed by Z=j2πL over some frequency range. These characteristics need not be exhibited over all frequency ranges.

[0017]FIGS. 2a through 2 c illustrate non-exclusive examples of active inductors that may be used in conjunction with some embodiments of the invention. In one specific arrangement, any of active inductors 30 through 32 may be substituted for one or both of active inductors 14 and 15 of limiting amplifier 1.

[0018] Active inductor 30 is a VHF integrated active inductor. Input impedance Zin of active inductor 30 is equal to (gds1+j2π(Cgs2+Cgd1+Cgd2)/(gds1+gm1+j2πCgd2)(gm2+j2πCgs2+Cgd1). Inductor 31 of FIG. 2c represents a simple enhancement of inductor 30. The input impedance of inductor 31 is given by by [(gds1+j2π(Cgs2+Cgd1+Cgd2))(gm3+j2πCgs2)]/[(gds1+gm1+j2πCgd2)(gm2+j2πCgs2+Cgd1)(gm1+j2πCgd3)]. Active inductor 32, in turn, provides an input impedance Zin that is equal to (1+j2πCgs1R)/(gm1+j2π[Cgs1−Cgs2+2π2Cgs2(Cgs1Cgs2/gm1gm2)]).

[0019] Any currently- or hereafter-known limiting amplifier may be used in conjunction with some embodiments. Amplifier 40 of FIG. 3 is one example of a limiting amplifier including an active inductor within a gain stage. Amplifier 40 consists of transconductance stage 50 and transimpedance stage 60, and is therefore considered a Cherry-Hooper type amplifier.

[0020] Transconductance stage 50 receives an input voltage and provides a slightly amplified output current to transimpedance stage 60. The input voltage is a differential signal carried by the signal lines labeled IN_P and IN_N. These lines are respectively coupled to the gates of NMOS transistors 51 and 52. Sources of transistors 51 and 52 are coupled together and to a drain of NMOS transistor 53. Transistor 53 functions as a current source to stage 50, with a source of transistor 53 coupled to ground and a gate thereof to receive bias voltage Vbias. Stage 50 is loaded by resistors 54 and 55 and the above-mentioned output current is provided at nodes 56 and 57.

[0021] Transimpedance stage 60 receives the output current and outputs an amplified voltage. As described above, the output voltage is limited to a particular value for any input signal within the operating range of amplifier 40. Transimpedance stage 60 comprises two stages, each of which is constructed similarly to amplifier 1 of FIG. 1a. In particular, elements 61 through 71 of a first stage and elements 72 through 82 of a second stage are coupled together as described with respect to respective elements 11 through 21 of amplifier 1. Output signals at output nodes 66 and 67 are provided to input terminals of the second stage, and output nodes 81 and 82 provide output signals of amplifier 40. In addition, each output signal is fed back to a respective input signal line of transimpedance stage 60 through one of resistors 83 and 84.

[0022]FIG. 4 illustrates limiting amplifier 100 according to some embodiments. Input stage 110 of amplifier 100 performs offset correction on a differential input signal that is represented by signals IN_P and IN_N. The corrected signal is amplified by two instances of amplifier 40 of FIG. 3 connected in series. Amplifier 120 further amplifies the amplified signal. Amplifier 120 is identical to amplifier 40 except that a resistor is substituted for each of active inductors 75 and 76. Such a configuration has been found to reduce jitter in some implementations.

[0023] Output buffer 140 is a unity gain amplifier that receives an output signal from amplifier 120 and outputs the output of amplifier 100 on the signal lines labeled OUT_P and OUT_N. Output buffer 140 sets the output impedance of amplifier 100 to a value required by its specification. Each amplifier of FIG. 4 receives a bias voltage from bias block 150. The bias voltage provided by bias block 150 is controlled by a Bias control signal.

[0024] The differential signal output from amplifier 120 is fed back to input stage 110 through low-pass filter 130. Low-pass filter 130 filters out components of the output signal having frequencies greater than 200 kHz. The remaining components of the output signal are used by input stage 110 to perform offset correction.

[0025]FIG. 5 is a block diagram of a module according to some embodiments. Module 200 includes optical interface 210, also known as a transimpedance amplifier, for receiving optical signals via an optical medium coupled thereto. Limiting amplifier 220 is coupled to optical interface 210 and comprises a limiting amplifier with an active inductor load such as limiting amplifier 100. Module 200 also includes deserializer 230 for converting the amplified serial data clocked at a first speed and 16-bit parallel data clocked at a second, lower speed. The parallel data is transmitted to digital framer 240, which may be coupled to backplane interface 250 for communicating with a backplane (not shown). Module 200 may be an element of a line card used to transmit and receive data to and from an optical medium.

[0026] Some implementations of active inductors may be significantly smaller than passive inductors. Accordingly, some embodiments provide size advantages over conventional limiting amplifiers. Some embodiments may provide one or more of a gain function that is substantially invariant with process, and a gain-bandwidth product that cannot be efficiently achieved by conventional systems.

[0027] The several embodiments described herein are solely for the purpose of illustration. Embodiments may include any currently or hereafter-known current sources, transistors, amplifiers and/or active inductors. Therefore, persons skilled in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7388436Jan 25, 2006Jun 17, 2008Marvell World Trade LtdHigh-bandwidth high-gain amplifier
US7397306Sep 27, 2006Jul 8, 2008Marvell World Trade Ltd.High-bandwidth high-gain amplifier
US7397310Sep 27, 2006Jul 8, 2008Marvell World Trade Ltd.High-bandwidth high-gain amplifier
US7417575Sep 27, 2006Aug 26, 2008Marvell World Trade Ltd.High-bandwidth high-gain amplifier
US7551024 *Jul 28, 2006Jun 23, 2009Marvell World Trade Ltd.Nested transimpedance amplifier
US7626453Jul 9, 2008Dec 1, 2009Marvell World Trade Ltd.Nested transimpedance amplifier
US7760029Jul 8, 2008Jul 20, 2010Marvell World Trade Ltd.High-bandwidth high-gain amplifier
EP1783898A2 *Oct 31, 2006May 9, 2007Marvell World Trade Ltd.High-bandwidth high-gain amplifier
EP1783899A2 *Nov 2, 2006May 9, 2007Marvell World Trade Ltd.High-bandwidth high-gain amplifier
WO2007034141A1 *Sep 13, 2006Mar 29, 2007Bookham Technology PlcRadio frequency signal device biasing circuit
Classifications
U.S. Classification330/308
International ClassificationH03F1/08, H03F3/45, H03F1/10, H03F1/48
Cooperative ClassificationH03F3/45475, H03F1/10, H03F2200/36, H03F1/08, H03F2203/45652, H03F3/45183, H03F1/486, H03F2203/45528
European ClassificationH03F1/48I, H03F3/45S1K, H03F3/45S1B1, H03F1/10, H03F1/08
Legal Events
DateCodeEventDescription
Sep 21, 2011FPAYFee payment
Year of fee payment: 8
Mar 10, 2008REMIMaintenance fee reminder mailed
Feb 28, 2008FPAYFee payment
Year of fee payment: 4
Dec 17, 2002ASAssignment
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:COVE, STEPHEN E.;REEL/FRAME:013588/0217
Effective date: 20021211
Owner name: INTEL CORPORATION 2200 MISSION COLLEGE BLVD.SANTA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:COVE, STEPHEN E. /AR;REEL/FRAME:013588/0217