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Publication numberUS20040169752 A1
Publication typeApplication
Application numberUS 10/752,218
Publication dateSep 2, 2004
Filing dateJan 7, 2004
Priority dateJul 29, 1999
Also published asUS6693670
Publication number10752218, 752218, US 2004/0169752 A1, US 2004/169752 A1, US 20040169752 A1, US 20040169752A1, US 2004169752 A1, US 2004169752A1, US-A1-20040169752, US-A1-2004169752, US2004/0169752A1, US2004/169752A1, US20040169752 A1, US20040169752A1, US2004169752 A1, US2004169752A1
InventorsMoshe Stark
Original AssigneeMoshe Stark
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Multi-photodetector unit cell
US 20040169752 A1
Abstract
A multi-cell cluster which includes a plurality of light-detecting unit cells and a single charge-integration and readout circuitry. Typically, each of the cells produces charge representative of the detected light. The circuit may be shared by the plurality of unit cells, and used to read-out the charge in real-time. The cluster may also include a switch associated with each unit cell, such that each switch connects its associated unit cell to the circuit. The switch may also be controlled in a time-multiplexing manner. Each unit cell may include a photodetector, a photodiode, or a photogate. The circuit may include a shared storage device, a shared reset circuit, or a readout circuit. Typically, the shared storage device may be for accumulating the charge in the focal plane. The here-above described apparatus facilitates either static or dynamic, either local or global image resolution/sensitivity tradeoffs.
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Claims(21)
1. A multi-cell cluster comprising:
a plurality of light detecting unit cells, each said cell producing charge representative of said detected light; and
a circuit shared by said plurality of unit cells, said circuit for reading-out said charge in generally real-time.
2. A cluster according to claim 1, and also comprising a switch associated with each said unit cell, each said switch connecting its associated unit cell to said circuit, each said switch being controlled in a time-multiplexing manner.
3. A cluster according to claim 1, wherein each said unit cell comprises one of the following: a photodetector, a photodiode, or a photogate.
4. A cluster according to claim 1, wherein said circuit comprises a shared storage device for accumulating said charge in the focal plane.
5. A cluster according to claim 1, wherein said circuit also comprises a shared reset circuit.
6. A cluster according to claim 1, wherein said circuit also comprises a shared readout circuit.
7. A sensing array comprising:
a multiplicity of clusters, said clusters comprising:
a plurality of unit cells for detecting light and producing charge representative of said light; and
a circuit shared by said unit cells for controlling the operation of said unit cells and accumulating said charge;
sampling lines each connected to a row of clusters for sampling said accumulated charge in said row; and
sensing lines each connected to a column of clusters for sensing said sampled charge present in said columns.
8. An array according to claim 7, wherein said lines carry programming signals for controlling said plurality of unit cells.
9. A method for operating an image sensor, the method comprising the steps of:
integrating charge from one or more unit cells of a cluster;
during said step of integrating, summing charge in a focal plane, said charge being from said at least one of unit cell; and
reading out said summed charge.
10. A method according to claim 9, wherein said one or more unit cells are preprogrammed unit cells.
11. A method according to claim 9, wherein the step of reading out comprises reading out said summed charge in real time.
12. A method according to claim 9, wherein the step of integrating comprises the step of integrating in a time-multiplexing manner.
13. A method according to claim 9, wherein said step of integrating comprises the step of integrating charge from each said unit cell separately.
14. A method according to claim 9, wherein said step of integrating comprises the step of substantially simultaneously integrating charge from two or more of said unit cells.
15. A method according to claim 9, wherein said step of integrating comprises the step of substantially simultaneously integrating charge from all of said unit cells in said cluster.
16. A method according to claim 9, further comprising the step of combining said readout into a single image.
17. A method according to claim 9, further comprising the step of dynamically controlling selection of the number of said one or more unit cells for said step of charge integrating.
18. A method according to claim 17, wherein said step of dynamically controlling comprises the step of selecting said number of one or more unit cells depending on light conditions.
19. A method according to claim 17, and wherein all of said steps are performed in generally real-time
20. A method according to claim 9, further comprising the step of:
improving the signal to noise ratio of said image sensor by increasing the number of said one or more cells in said step of integrating.
21. A method according to claim 9, further comprising the step of:
improving the resolution of said image sensor by decreasing the number of said one or more cells in said step of integrating; and
reading said cell separately in a time-multiplexing manner.
Description
FIELD OF THE INVENTION

[0001] The present invention relates to image sensor cell array architecture generally and, in particular, to a multi-photodetector unit cell and control thereof.

BACKGROUND OF THE INVENTION

[0002] Image sensors have traditionally used either photodiodes, either alone or in combination with active transistor element, or charge couple device (CCD) technology. For the last thirty years CCD has been the dominant image sensor technology.

[0003] The CCDs have many advantages, such as small pixel size, high sensitivity, and the ability to generate high-fidelity images. They also have many disadvantages, such as special manufacturing process requirements, high power dissipation, inability to integrate on the same chip additional functionality such as driving the processing, and complicated control circuitry. Furthermore, CCDs are manufactured by just a few manufacturers, and are not broadly accessible by independent design houses.

[0004] One of the emerging competing technologies, Complementary Metal Oxide Semiconductor (CMOS)-process-based active pixel sensor (APS) technology, promises low power, ability to integrate on the same chip the sensor and control circuitry, ability to form huge sensor arrays etc. One of the main goals to be accomplished in the APS design is a small pixel, comparable in size to the one accomplished with CCDs, with a high signal to noise ratio. This is difficult since the APS unit cell incorporates several active transistors. The signal-to-noise ratio requirement dictates the collection of as many photon-generated electrons as possible over the integration capacitor. This requires long integration time for weak photocurrents, and sizable capacity pixel-space-consuming capacitors.

[0005] Considerable research efforts have been directed towards reduction of the APS pixel size, and improvements in fill factor and quantum efficiency. Example of such are described in D. Scheffer et al., “Random addressable 20482048 active pixel image sensor,” IEEE Trans. Elec. Dev. Vol. 44, no. 10, October 1997, pp. 1716-1720, and in Y. Iida et al., “A %-inch 330 k square pixel progressive scan CMOS active pixel image sensor,” IEEE JSSC, Vol. 32, no. 11, November 1997, pp. 2042-2047.

[0006] The following is a partial listing of non-standard and standard technology alternatives used to achieve the above mentioned improvements.

[0007] Non-Standard Technologies

[0008] Because standard technology fails to support special new applications, ample of research effort has been put in to the development of non-standard technology.

[0009] Amorphous silicon photoconductor, photodiode, or phototransistor: This endeavor produces a reduced unit cell size and improved fill factor through photodetector vertical integration on top of the active readout circuit. The quantum efficiency is close to 100%, and the dark current is lower in comparison to the dark current accomplished with the single-crystal material. However, due to material charge trapping and structure irregularities, the amorphous silicon based photodetectors suffer from high fixed pattern noise (FPN). Backside-illuminated photodetectors: In this technology, whether CCDs or APS-based, the sampling and readout is located on the front side, and the photodetector occupies the backside of the image sensor. The image sensor is illuminated from its backside. Therefore, the fill factor, and quantum efficiency of nearly 100%, can be accomplished.

[0010] However, in order to produce the backside-illuminated photodetector, a process known as wafer thinning is required, which is a complex, expensive process. Therefore, backside-illuminated image sensors are employed for very specialized scientific and aerospace cost-insensitive applications. Furthermore, wafer thinning results in substantial crystalline irregularities nearby the wafer's surface and in a substantial excess noise due to surface recombination. Charge modulation devices (CMD): The CMD is distinguished by its simple structure. Due to its simple structure (a single transistor) very small pixels are achievable. This facilitates the implementation of huge-format arrays. However, the CMD image sensors are less sensitive to shorter wavelengths of light and require a specialized fabrication process.

[0011] Standard CMOS Processes

[0012] A lot of effort goes into research directed at the implementation of high-performance image sensors using a standard CMOS process for fabrication. This direction is of primary importance, since it promises low fabrication costs for on-chip cameras with readily available technology. Constructing high-quality APS image sensors takes the following directions:

[0013] Passive photodiode-detector image sensors: These image sensors use photodiodes as the sensing elements. Passive photodiode-based pixel elements were investigated in the 1960s. These pixels are very simple; they incorporate a single diode and a single transistor. The passive pixel design allows the highest fill factor for a given pixel size, or the smallest pixel size for a given fill factor.

[0014] However, this approach is limited by the relatively high readout noise. Also, the passive unit cell directly drives a full column-capacitance in the image sensor array. Since this capacitance is directly proportional to the number of column pixels, this limits the readout speed and results in significant readout noise. Therefore, the passive pixel approach is not well suited to the design of large-format image sensors.

[0015] Active-pixel photodiode-based image sensors: Photodiode-based APS image sensors feature a high quantum efficiency for the red, the green and even for the blue-wavelength photons. The name “active pixel sensor” originates from its having at least one active transistor incorporated in every unit cell. The transistor performs an amplification or buffering function.

[0016] There are many types of active circuits. The simple ones incorporate up to three transistors in the unit cell. The APS photodetectors are limited in their fill factor per fixed unit cell size, or are limited in the minimum cell size per fixed fill factor. It is a major objective to reduce the overall unit cell complexity, to accomplish high-resolution, a high fill factor and a high quantum efficiency.

[0017] Interestingly enough, small pixels result in a reduced readout noise and speed improvement, due to a reduced column capacitance. Although designs with a minimal number of transistors and very small pixels have been reported (5.65.6 μm), these designs also feature a very small fill factor (15.8%).

[0018] Active-pixel photogate-type image sensors: The basic concept behind this circuit is to combine the sensing and charge storage functions. The front-side light-illuminated transistor collects charge proportional to light-intensity below the gate. At the readout time, the charge collected and stored below the photogate is transferred to the floating diffusion node. The floating diffusion is tied to the source follower circuit input. The source follower buffers the floating diffusion from the high capacitance array column.

[0019] Overall, the photogate pixel design incorporates five transistors including the photogate sensing/charge-storage device. The low readout noise and lack of image lag demonstrated by the photogate structure have stirred a lot of interest and have resulted in significant research effort directed at the improvement of the photogate-based design. Relatively small pixels have been developed (1010 μm using the 0.5 μm CMOS process technology). However, this approach demonstrates however low quantum efficiency for the blue light wavelength photons, which are absorbed by the polysilicon-plated photogate.

[0020] In order to overcome this problem, some engineering compromises are made and APS-based sensors that combine the photogate and the photodiode design have been invented. This design uses photogate sites to collect the red and the green wavelength photons and photodiode sites to collect the blue wavelength photons.

[0021] Multi-Resolution

[0022] The ability to modify the image sensor's resolution is defined as multi-resolution. The application of multi-resolution has been justified by the ability to trade high resolution for the increase of the video frame rate and the image processing. Far more important, the multi-resolution approach makes it possible to trade the resolution for signal-to-noise ratio. This is especially crucial in low light conditions, when the electrical signal proportional to the light intensity may be quite weak. This results in a noisy, low-quality image. Sometimes it is preferable to get a lower resolution but less-noisy image.

[0023] One of the methods used, as described by S. Kemeny et al: “CMOS Active Pixel Sensor Array with Programmable Multiresolution Readout”, JPL, California Institute of Technology, Pasadena Calif. 91109 USA, 1994, and by R. Paniacci et al: “Programmable multiresolution CMOS active-pixel sensor”, SPIE Vol. 2654, trades resolution for speed. The method is based upon pixel signal block averaging. The described method is complicated, and does not yield a better signal-to-noise ratio.

[0024] The second method, as described by Zhimin Zhou et al: “Frame-Transfer CMOS Active Pixel Sensor with Pixel Binning”, IEEE Trans. Elec. Dev., Vol. 44, No. 16, October 1997, pp. 1764-1768, enables the summation of the accumulated charge in several pixels. The accumulated charge summation is performed first by sampling the charge accumulated during charge integration into a memory cell, and second, by summing up the transferred charge on vertical and horizontal charge integration amplifiers (CIAs).

[0025] Since, the charge summation is linear, while the noise sums up as a square root of the noise energies, the pixel charge summation yields an improvement in the signal-to-noise ratio.

SUMMARY

[0026] It is an objective of the present invention to provide a CMOS image sensor architecture that produces a substantially optimal combination of sensitivity and signal-to-noise ratio, along with relatively high fill factor.

[0027] There is therefore provided, in accordance with an embodiment of the present invention, a multi-cell cluster that may include a plurality of light-detecting unit cells and a circuit. Typically, each of the cells produces charge representative of the detected light. The circuit may be shared by the plurality of unit cells, and used to read-out the charge in real-time.

[0028] The cluster may also include a switch associated with each unit cell, such that each switch connects its associated unit cell to the circuit. The switch may also be controlled in a time-multiplexing manner. Each unit cell may include either a photodetector, a photodiode, or a photogate. The circuit may include a shared storage device, a shared reset circuit, or a readout circuit. Typically, the shared storage device may be for accumulating the charge in the focal plane

[0029] There is further provided, in accordance with an embodiment of the present invention, a sensing array including a multiplicity of clusters, sampling lines and sensing lines. The clusters may include a plurality of unit cells and a circuit. The unit cells may detect light, and produce charge representative of that light. The circuit may be shared by the unit cells and may control the operation of the unit cells. The circuit may also accumulate the charge. Each sampling line may be connected to a row of clusters for sampling the accumulated charge in the row. Each sensing line may be connected to a column of clusters for sensing the sampled charge present in the columns. The sampling and the sensing lines may also carry programming signals for controlling the plurality of unit cells.

[0030] There is also provided, in accordance with an embodiment of the present invention, a method for operating an image sensor. The method includes the steps of integrating charge from one or more unit cells of a cluster and, during the step of integrating, summing charge from at least one of the unit cells in the focal plane. The method may also include reading out the summed charge. One or more of the unit cells may be preprogrammed unit cells, and the step of reading out may include reading out the summed charge in real time.

[0031] The step of integrating may include the step of integrating in a time-multiplexing manner, or may include the step of integrating charge from each unit cell separately. Alternatively, the step of integrating may include the step of simultaneously integrating charge from two or more of the unit cells, or may include the step of simultaneously integrating charge from all of the unit cells in the cluster. The method may include the step of combining the readout into a single image.

[0032] The method may further include the step of dynamically controlling selection of the number of unit cells for the step of charge integrating, and this step of dynamically controlling may include the step of selecting the number of unit cells depending on the light conditions. All of the steps may be performed in real-time.

[0033] Also included in the method may be the step of improving the signal-to-noise ratio of the image sensor by increasing the number of cells in the step of charge integrating. This is done in order to linearly increase the amount of summed charge while the noise increases moderately as a square root function. The method may further include a step of improving the resolution of the image sensor by reading-out each cell separately, in a time-multiplexing manner.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the appended drawings in which:

[0035]FIG. 1 illustrates an active pixel sensor (APS) image sensor architecture implemented on a monolithic piece of a semiconductor material, constructed and operative in accordance with a preferred embodiment of the present invention;

[0036]FIG. 2 is a schematic illustration of a four-photodetector unit cell based upon a direct injection (DI) circuit and is used with the architecture of FIG. 1;

[0037]FIG. 3 is a schematic illustration of a four-photodetector unit cell similar to that of FIG. 2 and operational with opposite polarity signals;

[0038]FIG. 4 is a schematic illustration of an alternative four-photodetector unit cell based upon N-channel type photogate transistors;

[0039]FIG. 5 is a timing diagram of individual control signal timing sequences when implemented with the architecture illustrated in FIG. 1;

[0040]FIG. 6 is a timing diagram of control signal timing sequence for simultaneously sampled horizontal photodetector pairs;

[0041]FIG. 7 is a timing diagram of control signal timing sequence for simultaneously sampled vertical photodetector pairs; and

[0042]FIG. 8 is a timing diagram of control signal timing sequence for simultaneously sampled photodetector quadrants.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0043] The present invention discloses a multi-resolution sensor, which utilizes time multiplexing to vary charge summation of a cluster of unit cells. The clusters are supported by shared simple circuitry, which implements the charge collection and time multiplexing, thus eliminating the need for complicated charge summation circuitry. The novel multi-resolution sensor enables implementation of smaller pixel size and improved pixel fill factor. Furthermore, the present method enables selection of a per-scene-illumination optimal compromise between the image sensor's resolution on the one hand and signal-to-noise and sensitivity on the other.

[0044] Structure of Sensor 10

[0045] Reference is now made to FIG. 1, an illustration of an active pixel sensor (APS) 10 comprising an array 8, a line decoder 16, and a sense amplifiers/readout multiplexer 18. Array 8 comprises a multitude of multi-photodetector clusters 12. Each cluster 12 comprises n unit cells 14.

[0046] Array 8 further comprises a multitude of column-sense lines, designated ColSense 1 to H, and a multitude of read-row lines, designated RdRw 1 to V. Each line carries associated signals, i.e. the read-row lines RdRw carry read-row signals RdRw. Charge integration, or exposure, of unit cells 14 is controlled by an associated integration signal Int carried by an integration line, designated Int. The clusters 12 are arranged in array 8 in H-columns by V-rows.

[0047] In the embodiment illustrated, the read-row line RdRw is shared between the unit cells 14 in adjacent rows, such as in rows i, and i+1, and is therefore double-indexed. Similarly, the column-sense line ColSensej,j+1 is shared between photodetector cells connected to columns j and j+1, and is also double-indexed. This pairing of elements provides additional space saving benefits.

[0048] Structure of the Clusters 12

[0049] Reference is made to FIG. 2, a schematic diagram of one possible embodiment for cluster 12 and useful in understanding the present invention. Each unit cell 14 comprises an associated photodetector 22 and an associated transistor 24. Typically the operations of cluster 12 are based on direct injection circuitry.

[0050] In the exemplary description herein, clusters 12 comprise four unit cells 14, generally designated 14A to 14D. However, it is noted that clusters 12 could comprise alternative pluralities of unit cells 14, such as 8 or 16 pixels, and still comply with the principles of the present invention. For purposes of clarity herein, unit cells 14A to 14D and their associated elements are designated A-D, accordingly.

[0051] Via the present novel architecture, the integration charge as accumulated by the group of unit cells 14 is summed up either individually or in any combination, thus offering the ability to select an optimal balance between resolution and signal-to-noise ratio/sensitivity. Operation of cluster 12 is described hereinbelow.

[0052] Within cluster 12, all of the four unit cells 14 are clustered to share a single reset/readout circuit 27. Circuit 27 comprises a reset transistor 26, an integration capacitor 28, and a readout transistor 30. This reduces on average by a factor of four the number of readout transistors per single transistor 24, and contributes to a smaller pixel pitch, and/or a greater fill factor per unit cell 14, and/or a larger integration capacitor.

[0053] It is thus noted that clusters 12 provide the advantage of being relatively simple with space savings resulting from two measures: shared charge-integration/readout circuitry and shared readout/sense lines.

[0054] The present novel architecture can be used in conjunction with other nonstandard and standard technologies and circuit design techniques. Furthermore, photodetector clustering can be applied to any type of APS type image sensor any type of an active circuit, which results in a pixel pitch reduction and fill factor improvement. Similarly, the present invention can be used with any semiconductor manufacturing process. For the particular embodiment depicted in FIG. 2, transistors 24, are of P-channel type due to the selected signal polarity and the process. However, occasionally due to other considerations, N-channel transistors are selected to perform the common gate amplifier function.

[0055] An example of such is depicted in FIG. 3, to which reference is now made. FIG. 3 illustrates an alternative cluster 112 comprising unit cells 114. In contrast to FIG. 2, the unit cells 114 of FIG. 3 comprise N-channel transistors 104 which perform the same associated function as that performed by transistors 24 of FIG. 2. Elements similar to those in FIG. 2 are similarly referenced and will not be explained further. Reference is now made an alternative embodiment of clustered unit cells, FIG. 4, which illustrates a four-photogate cluster 212. Elements similar to those described above are similarly numbered and will not be described further.

[0056] Cluster 212 comprises four unit cells 214, reset transistor 26, buffer 108 and readout transistor 30. Each such unit cell 214 comprises an associated photogate sensors 102 and N-channel type transistors 104, Similar to the principle described hereinabove in connection with FIGS. 2 and 3, the four photogates 102, share the single, reset, source follower buffer 108, and the readout transistor 30, which reduces the average number of transistors per photogate sensor 102.

[0057] It is noted that although only 3 embodiments of the present invention are presented herein, other combinations of unit cells and shared circuitry, such as, for example, photogates and P-channel transistors, fall within the principles of the present invention.

[0058] Operation of Sensor 10

[0059] Referring again to FIG. 1, sensing of an image on the level of sensor 10 is as follows: A series of associated integration signals Int are applied to clusters 12, driving charge integration therein. Charge is accumulated in an integration capacitor (not shown in FIG. 1), typically proportional to the charge-integration time and to the local light intensity.

[0060] Operation of Clusters 12

[0061] Referring again to FIG. 2, the operations of cluster 12 are as described below. It is noted that the operations for clusters 112 and 212 (FIGS. 3 and 4, respectively) are similar and are included within the principles described below. Except where different, operations of clusters 112 and 212 will not be described further.

[0062] Operation Cycle

[0063] The sequence of the FIG. 2 image sensing and readout cycle on the level of cluster 12 is as follows: The cycle starts by driving the reset signal Rst, thus causing the reset transistor 26 to conduct and capacitor 28 to flush any residue charge originating in the previous cycle.

[0064] Photodetectors 22, being exposed to light, transmit associated photocurrents Iph, generally designated Iph-A to Iph-D. The associated integration signals Int-A to Int-D, respectively, are applied to their associated transistors 24, opening the associated transistors 24, thus allowing flow of photocurrent Iph from the associated photodetectors 22.

[0065] Transistor 24, acting as a common gate amplifier, isolates the associated photodetector 22 from capacitor 28, and provides photocurrent Iph unaffected by the voltage changes in the capacitor 28. Transistors 24 additionally transduce the photocurrent Iph from the photodetector 22 into the capacitor 28.

[0066] The charge integration cycle is terminated when the integration signal Int signal goes high, cutting off the associated transistors 24 and restricting flow of photocurrent IPH Read-row signal RdRw goes high, causing readout transistor 30 to conduct and read out the accumulated charge on integration capacitor 28. Conduction of readout transistor 30 enables the capacitor 28 to transfer the accumulated charge over the column sense line ColSense to a sense amplifier (not shown). The cycle is then repeated, starting with flushing of the capacitor 28.

[0067] It is noted that transistor 26 is optional, since the reset function can be alternatively performed through the readout transistor 30. It is further noted that for some readout circuits, the residue charge left on capacitor 28 may be negligible; however, preferably the residue charge is flushed prior to the next integration sub-cycle.

[0068] Sub-Cycles

[0069] The image sensing cycle comprises equal length sub-cycles. Each sub-cycle comprises reset, charge integration and readout for the associated unit cell 14. Therefore, there is one sub-cycle for unit cell 14A, one sub-cycle for unit cell 14B, and so on, for a total of 4 sub-cycles.

[0070] It is noted that depending on the setting of cluster 12, it is possible to program the duration and the number of the sub-cycles. This programming capability allows varying the duration and content of the sub-cycles by varying the charge integration sampling of the unit cells 14. It is thus also possible to vary the number of sub-cycles per cycle.

[0071] As an example, each of the four unit cells 14 can be individually sampled (individual sub-cycle) for a total of 4 sub-cycles per cycle. Alternatively, the four unit cells 14 can be sampled in pairs (dual sub-cycle) for a total of 2 sub-cycles per cycle, Furthermore, all four unit cells 14 can sampled simultaneously (simultaneous sub-cycle) for a total of 1 sub-cycle per cycle.

[0072] Each sampling rate provides different levels of resolution and sensitivity. The highest resolution but lowest sensitivity is achieved with individual sub-cycles, and the lowest resolution and highest sensitivity is achieved with simultaneous sub-cycles.

[0073] It is noted that if cluster 12 were to comprise more unit cells 14, such as 6 or 8 or 16, the number of sub-cycles and resultant imaging performances would vary accordingly.

[0074] Still referring to FIG. 2, the following is a model of exemplary operation of individual sub-cycles (separate sampling of each unit cell 14). The integration signals Int-B, Int-C, and Int-D signals are driven high, cutting off photocurrent flow from transistors 24B to 24D. Meanwhile, integration signal Int-A is pulled to the Vbias voltage or low level, allowing transistor 24A to conduct. Photocurrent Iph-A flows from photodetector 22A through the associated transistor 24A, and is accumulated in capacitor 28. Integration signal Int-A signal then goes high, cuffing off the transistor 24A. The accumulated charge on capacitor 28 is then read-out.

[0075] The next sub-cycle is then executed, this time with integration signals Int-A, Int-C, and Int-D being driven high, and integration signal Int-B pulled to low, and so on for unit cells 14C and 14D, until all four unit cells 14 have completed their respective sub-cycle and the sampling and readout of the entire image sensor 10 is complete.

[0076] It will be apparent to those skilled in the art that by controlling the timing of the integration signals Int-A to Int-D it is possible to allow one or more transistors 24 to conduct simultaneously, and thus one or more associated unit cells 14 can be read out simultaneously. As an example, for dual-sub-cycles the associated integration signals Int-A and int-B are simultaneously activated, and therefore the photocurrents from unit cells 14A and 14B are simultaneously summed up. This reduces the spatial resolution by a factor of two in one direction and improves the signal-to-noise ratio by {square root}2 and sensitivity by a factor of 2.

[0077] As another example, for simultaneous sub-cycles the associated integration signals Int-A to Int-D are simultaneously activated, and the photocurrents from all four-unit cells 14 are simultaneously summed up. This reduces the spatial resolution by a factor of two in each direction but significantly improves the signal-to-noise ratio and sensitivity.

[0078] Thus, the application of the present photodetector clustering invention provides efficient multiresolution function along with the ability to tradeoff resolution versus sensitivity, and vice versa.

[0079] Reference is now made to FIG. 4 and the operations of cluster 212. In contrast to the above example, each photogate 102 accumulates its charge on its own associated capacitor (not shown). Therefore, since all the photogates 102 may collect charge, the charge-integration time is not compromised as the result of time-multiplexed sampling/readout. Cluster 212 is also capable of multiresolution, as described hereinbelow with reference to FIGS. 5-8; however, for cluster 212 the integration time is fixed. The improvement in the signal-to-noise ratio is proportional to the number of simultaneously sampled photogates. The resolution is reduced by the same factor.

[0080] Timing Diagrams

[0081] Reference is now made to FIG. 5, a timing diagram depicting individual sub-cycles for each of the four-unit cells 14, and useful in understanding the operation of the embodiment depicted in FIG. 2.

[0082] It is noted that the depicted signal polarities are exemplary and, if reversed, would be applicable to the embodiment depicted in FIG. 3. Additionally noted in reference to FIG. 5, elements similar to those previously described are similarly designated and will not be discussed in further detail.

[0083] For purposes of clarity in the explanation of the following figures, reference to an activity performed by a specific element is denoted with a subscript letter, while explanations of general activities are sans subscript. As an example, photocurrent Iph from transistor 22A is denoted as photocurrent Iph-A, while photocurrent for general explanation purposes is denoted as photocurrent Iph.

[0084]FIG. 5 depicts four sub-cycles, labeled TA, TB, TC and TD, respectively. During each sub-cycle T, the associated unit-cell 14 runs through an entire cycle of reset, sampled and read out. For example, during sub-cycle TA, photodetector 22A is reset, sampled and read out, and so on.

[0085]FIG. 5 additionally depicts the timing of the reset signal Rst, the four integration signals Int-A to Int-D, a capacitor photocurrent IC, a capacitor voltage VC, and the four read-row signals RdRWA-D respectively.

[0086] The cycle depicted in FIG. 5 starts at point 42 with sub-cycle TA. At point 42 reset signal Rst is pulled to high, causing discharge of integration capacitor 28. It is noted that when reset signal Rst is high, all the other signals (Integration and ReadRow) are low.

[0087] As depicted by point 44, the reset signal Rst also drives capacitor 28 into a deep depletion state, as noted by drop of capacitor voltage VC. The Reset signal Rst then goes low, switching off transistor 26.

[0088] Shortly after, all the integration signals Int-A to Int-D are pulled high, disconnecting photodetectors 22 from capacitor 28 for a brief period, as designated by period 46.

[0089] Charge integration sub-period Tint-A starts when the integration signal Int-A levels to voltage Vbias, causing transistor 24A to operate as a common gate preamplifier, allowing photocurrent Iph-A from photodetector 22A to flow into the capacitor 28 for a charge integration sub-period Tint-A. It is noted that concurrently, integration signals Int-B to Int-D remain high, restricting flow from photodetector 22B to 22D.

[0090] Thus, since photocurrent Iph flows only from transistor 22A, during charge integration sub-period Tint-A, the capacitor photocurrent IC is equal to photocurrent Iph-A. Additionally, assuming that the integration capacitor 28 is linear and does not vary with voltage, the capacitor's voltage Vc rises linearly in time, as noted by slope 48.

Thus, Ic=Iph-A and VC=VC-A

[0091] The end of integration sub-period Tint-A is designated by peak voltage VC-A. Completion of the integration sub-period TInt-A is followed by a readout period TRd-A. Readout is performed sequentially, line after line in the array and is controlled by the readout signals RdRw1,2, RdRw3,4, . . . , RdRwV-3,V-2, RdRwV-1,V, which activate sampling of the accumulated charge in the capacitor 28.

[0092] Sampling of the integration capacitor 28 flushes the capacitor, as depicted as drop 50, although some small residue charge may still be left on the capacitor 28, as depicted by level 52.

[0093] Sub-cycle TB then starts, commencing again with the reset signal Rst being pulled to high, causing discharge of capacitor photocurrent IC from integration capacitor 28. Steps as performed for sub-cycle TA are repeated for sub-cycle TB through TD, with the appropriate signals for the associated unit cells 14.

[0094] Typically, the integration period Tint and readout period Trd for all the photodetectors 22 in cluster 12 is identical, unless the image sensor enables individual tuning of the charge integration time for each unit cell 14. Thus sub-cycle TA=TB=TC=TD and the entire image sensor sampling/readout cycle T is (4TA).

[0095] Alternative timing for charge-integration samplings is possible. Reference is now made to FIG. 6, which depicts dual sub-cycles of simultaneous sampling of photodetectors 22A and 22B, followed by simultaneous sampling of photodetectors 22C and 22D. Elements similar to those described above are similarly numbered and will not be described further.

[0096] For the instance illustrated in FIG. 6, the capacitor photocurrent Ic=Iph-A+Iph-B, and if the photocurrents IphA to IphD are identical, then Ic=2Iph-A=2Iph-D. Additionally, dual sub-cycle periods TA+B+TC+D=TA+TB+TC+TD.

[0097] As depicted in FIG. 6, the length of dual-readout sub-periods TRdA+B is roughly equivalent to individual readout period TRd-A. Thus the result net time left for the dual-integration sub-period TInt-A+B is longer, resulting in a much larger capacitance voltage VC, where VC=VC−A+B.

[0098] Reference is now made to FIG. 7, an illustration of simultaneously sampling of photodetectors 22A and 22C, followed by photodetectors 22B and 22D. The results of the sampling for FIG. 7 are similar to those achieved from the sampling illustrated in FIG. 6.

[0099] Reference is now made to FIG. 8, an illustration of sampling of all four photodetectors 22 simultaneously. This sampling method results in the highest sensitivity but the lowest resolution. Calculations of signal-to-noise ratios and integration time are located in the Appendix.

[0100] Sensor Applications

[0101] As is apparent to one skilled in the art, the resolution and signal-to-noise ratio as produced by the embodiment illustrated in FIG. 5 is not equivalent to that depicted in FIG. 6. Since the signal-to-noise ratio improves as a square root of the integration time while the integration time more than doubles (due to halved readout time for the same frame rate), and the photocurrent signal more than doubles in FIG. 6 as compared to FIG. 5, the dual signal-to-noise ratio improves by more than {square root}2 times for the dual integration than for the individual signal-to-noise ratio.

[0102] In contrast, since photodetectors 22A and 22B are in the same row while photodetectors 22C and 22D are in the next row below, the sampling sequence illustrated in FIG. 6 results in a reduced horizontal resolution. Thus for dual sub-cycles, while the signal-to-noise ratio improves, it is at the cost of reduced resolution.

[0103] In the time diagram of FIG. 7, photodetectors 22A and 22C are in the same column, while photodetectors 22B and 22D are in the next column to the right, resulting in reduced vertical resolution and improved signal-to-noise ratio.

[0104] Finally, in FIG. 8, simultaneous sub-cycles result in half the resolution in the horizontal direction as well as in the vertical direction. However, the signal-to-noise ratio is greatly improved.

[0105] Thus, by analyzing the operations of FIGS. 5-8, it is possible to appreciate that the present invention provides the ability to select the appropriate resolution and signal-to-noise ratio for the relevant application.

[0106] It will be appreciated by those skilled in the art that many of the prior art technologies can be used in conjunction with the present invention. As an example, backside-illuminated image sensors, when combined with a multi-photodetector unit cell, enables implementation of smaller pixels.

[0107] It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described hereinabove. Rather the scope of the present invention is defined only by the claims that follow:

APPENDIX

[0108] Equations

[0109] The tradeoff between resolution and signal-to-noise ratio is explained in the following series of equations. The photocurrents Iph as summed-up in capacitor is: l c = j = 0 K - 1 l ph - j ( 1 )

[0110] and current noise In sums up as: i n = ( j = 0 K - 1 i n - j 2 ) 1 / 2 ( 2 )

[0111] where,

[0112] Ic is the total current charging the capacitor at once,

[0113] Iph-j is the individual current flowing from the j-th photodetector into capacitor,

[0114] in is the total, current noise originating from photodetector,

[0115] in-j is the j-th photodetector current noise, and

[0116] K is the number of the simultaneously conducting photodetectors.

[0117] It is noted that the above formula assumes that the photodetector originated noise is dominant, while other types of noise sources, such as the reset noise and 1/f noise originating from the switching transistor, are negligible.

[0118] If the signal-to-noise ratio is defined as: S N = I c i n ( 3 )

[0119] and provided that all the photodetectors sink the same photocurrent Iph, and generate the same noise during the charge integration period, and assuming that other noise sources are negligible, then ( S N ) K = S N 1 K ( 4 )

[0120] for thermal noise, where S/N is the signal-to-noise ratio for a single photodetector charging the integration capacitor, and (S/N)K is the signal-to-noise ratio, when K photodetectors are simultaneously charging the integration capacitor.

[0121] Thus, as an example, if K=4 and the charge integration time is kept constant, the signal-to-noise ratio improves by a factor of 2.

[0122] Typically, under normal conditions, photocurrent Iph is very small and the transistor operates in the weak inversion region. Provided that the integration capacitor is linear and does not vary with voltage, then:

Ic=Iph  (5)

[0123] V c = I C C I t ( 6 )

[0124] where Ic is the current from the capacitor and t is the integration sub-period. For instances where t equals integration sub-period Tint, the capacitor voltage Vc level is, V c = I C C I T int ( 7 )

[0125] Furthermore, if TA is the sub-cycle of photodetector A,

[0126] Tint-A is the integration period for photodetector A,

[0127] Trd-A is the readout time for photodetector A.

[0128] Then,

T A =T int-A +T rd-A  (8)

[0129] Since typically the integration period Tint and readout period Trd for all the photodetectors in the cluster is identical, then for sub-cycle time T,

TA=TB=TC=TD  (9)

[0130] and the entire image sensor sampling/readout cycle T is:

T=4T A  (10)

[0131] By substituting equation (10) into equation (8), it is found out that per photodetector, the maximum individual integration sub-cycle Tint-max-individual is T int - max - individual = T 4 - T rd ( 11 )

[0132] and the maximum dual integration sub-cycle Tint-dual per photodetector is more than doubled in comparison to the maximum individual integration sub-period Tint. T int - max - dual = T 2 - T rd ( 12 )

[0133] By evaluating equation (4), it is noted that when going from individual sub-cycles to dual sub-cycles, the signal-to-noise ratio improves as a square root of the integration time, and the photocurrent signal is doubled. If equation (4) and (12) are solved, and the signal-to-noise ratio for dual sub-cycles is solved for then: ( S N ) dual = 2 T 2 - T rd T 4 - T rd ( S N ) individual ( 13 )

[0134] When all the four-photodetector currents Iph are summed up simultaneously on the integration capacitor the result is half the resolution in the horizontal direction, as well as in the vertical direction. However, the signal-to-noise ratio is greatly improved, as following ( S N ) all - combinded = 4 T 2 - T rd T 4 - T rd ( S N ) individual ( 14 )

EXAMPLE 1

[0135] If T=33.33 msec, Trd=4 msec, the dual signal-to-noise ratio is 3.4 times better than the individual signal-to-noise ratio.

EXAMPLE 2

[0136] If T=33.33 msec and Trd=4 msec, the signal-to-noise ratio for all the photodetectors summed up simultaneously if 10.4 times better than for the instance where it is done on an individual basis.

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Classifications
U.S. Classification348/302, 348/308, 348/E03.02, 348/E03.018, 348/E05.091, 348/310, 348/307
International ClassificationH04N5/347, H04N5/363, H04N5/3745
Cooperative ClassificationH04N5/37457, H04N5/347, H04N5/343
European ClassificationH04N5/3745C, H04N5/343, H04N5/347
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