US20040171273A1 - Specimen surface processing apparatus and surface processing method - Google Patents

Specimen surface processing apparatus and surface processing method Download PDF

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Publication number
US20040171273A1
US20040171273A1 US10/375,093 US37509303A US2004171273A1 US 20040171273 A1 US20040171273 A1 US 20040171273A1 US 37509303 A US37509303 A US 37509303A US 2004171273 A1 US2004171273 A1 US 2004171273A1
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sample
plasma
surface processing
gas
vacuum chamber
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US10/375,093
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Masatoshi Oyama
Yoshiyuki Ohta
Tsuyoshi Yoshida
Hironobu Kawahara
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Hitachi High Tech Corp
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Hitachi High Technologies Corp
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Priority to US10/375,093 priority Critical patent/US20040171273A1/en
Assigned to HITACHI HIGH-TECHNOLOGIES CORPORATION reassignment HITACHI HIGH-TECHNOLOGIES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OHTA, YOSHIYUKI, KAWAHARA, HIRONOBU, OYAMA, MASATOSHI, YOSHIDA, TSUYOSHI
Publication of US20040171273A1 publication Critical patent/US20040171273A1/en
Priority to US11/224,967 priority patent/US7354525B2/en
Abandoned legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32917Plasma diagnostics
    • H01J37/32935Monitoring and controlling tubes by information coming from the object and/or discharge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32917Plasma diagnostics
    • H01J37/3299Feedback systems
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • H01L21/31138Etching organic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/905Cleaning of reaction chamber
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/907Continuous processing

Definitions

  • the present invention relates to a surface processing apparatus and a surface processing method of a sample such as a semiconductor element.
  • a surface processing apparatus and a surface processing method suitable for performing etching and ashing of the semiconductor surface using a plasma are particularly advantageous.
  • a plasma processing apparatus is widely used in the fine processing processes such as film deposition, etching, and ashing.
  • the process by plasma processing performs a prescribed process in the following manner.
  • a process gas introduced into a vacuum chamber (reactor) is transformed into a plasma by plasma generation means.
  • the resulting plasma is allowed to react on the semiconductor wafer surface to perform a fine processing, and volatile reaction products are discharged.
  • the present invention covers the apparatus utilizing a plasma in general.
  • an apparatus called an ECR (Electron Cyclotron Resonance) system which is one of those apparatuses.
  • This ECR system generates a plasma by microwave discharge in a vacuum chamber externally applied with a magnetic field.
  • a bias voltage is applied to the sample.
  • the device configuration of a semiconductor element has become increasingly complicated in recent years, so that there are demands for an increase in speed of processing and a reduction in number of steps in the manufacturing process thereof. Namely, for a semiconductor integrated device, with a request for downsizing, for example, for a pitch between wirings of about 0.2 ⁇ m or less, the capacitance between neighboring wirings relatively increases at the wiring portion. If a conventional silicon dioxide film is used as an insulating material between wirings of such a device, it becomes impossible to enjoy benefits due to higher speed of a transistor resulting from downsizing. For this reason, a material with a low dielectric constant (k value) such as SiOC is employed as an interwiring insulating material.
  • k value dielectric constant
  • the material with a low dielectric constant (k value) is mainly used in combination with copper as a wiring material, and formed by a process called dual damascene. This requires a step of etching processing of an insulating film.
  • the dual damascene formation process includes a step of processing and transferring a trench profile into a porous insulating film using a hard mask, and imparting a prescribed profile to a sample having a hole profile processed in the previous step.
  • Such a technology is disclosed, for example, in Japanese Patent Laid-open No. H 9(1997)-115878.
  • a method for monitoring the processing state, and controlling the process is also adopted in the prior art.
  • the method for monitoring the processing state, and controlling the process for example, there is known the method in which a reflected interference light from a processed wafer is monitored to terminate etching processing, disclosed in U.S. Pat. No. 5,658,418.
  • a sample surface processing apparatus comprises: a vacuum chamber; means for generating a plasma in the vacuum chamber; a sample stage for mounting a sample to be surface processed by the plasma thereon; and a power source for applying a high frequency bias to the sample, wherein the surface processing of the sample is performed by the plasma.
  • the apparatus further comprises a function of monitoring the plasma emission intensity of a reaction product in the vacuum chamber, and the changes in interference light, automatically determining the state of the surface processing based on the monitor result, and controlling the high frequency bias.
  • the apparatus further comprises means for introducing a mixed gas of an oxygen gas and a fluorine-containing gas as an ashing gas into the vacuum chamber.
  • a mixed gas of an oxygen gas and a fluorine-containing gas is introduced as an ashing gas, and subsequently, ashing is performed with a plasma using only an oxygen gas.
  • a sample surface processing method comprises: generating a plasma in a vacuum chamber, and applying a high frequency bias to a sample stage for mounting a sample thereon, for performing the surface processing of the sample, and the method is characterized in that a mixed gas of an oxygen gas and a fluorine-containing gas is introduced into the vacuum chamber to perform the surface processing of the sample by the plasma.
  • a mixed gas of an oxygen gas and a fluorine-containing gas is introduced as an ashing gas. This allows the following steps to be carried out at the same time: removal of the silicon component left on the mask material surface and the mask material in the area including the cured mask layer and the like; and the removal of the carbon-based, and silicon-based deposits deposited on the inner wall of the vacuum chamber.
  • the removal of the mask material is performed under low pressure, and in the subsequent step to the step using a mixed gas of a fluorine-containing gas and an oxygen gas, a plasma of only an oxygen gas is used. As a result, it becomes possible to reduce the damages (etching) to the film layer after etching.
  • FIG. 1 is a schematic diagram showing an overall configuration of a plasma processing apparatus to which the present invention is applied;
  • FIGS. 2A to 2 C are diagrams respectively showing the states of the surface of a sample and the vacuum chamber inner wall in a processing method of the present invention
  • FIG. 3 is a diagram showing the desirable ranges of the processing pressure and the frequency of a power source in the method of the present invention.
  • FIG. 4 is a diagram showing the states of the surface of a sample and the vacuum chamber inner wall in a prior art example.
  • FIG. 1 is a schematic diagram of a plasma processing apparatus applying electron cyclotron resonance (ECR), to which the present invention is suitably applicable.
  • the plasma processing apparatus includes a plurality of processing chambers 1 which are vacuum chambers. Around each processing chamber 1 , coils 2 are disposed in order to generate a magnetic field for electron cyclotron resonance (ECR).
  • a gas for etching is supplied to each processing chamber 1 through a gas supply tube 4 connected to each gas source 30 via each mass flow controller 3 .
  • the etching gas is introduced from a gas supply plate 5 made of silicon or glassy carbon and provided with about several hundreds fine holes with a diameter of about 0.4 to 0.5 nm into each processing chamber 1 .
  • a disc-like antenna 6 for radiating a UHF band microwave is disposed above the gas supply plate 5 .
  • the microwave is fed from a power source 7 through a matching circuit 8 and a lead-in axis 9 to the antenna 6 .
  • the microwave is radiated from around the antenna 6 , and the resonance electric field in the space above the antenna 6 is introduced into each processing chamber through a dielectric member 10 .
  • the band capable of making the electron temperature of the plasma as low as 0.25 eV to 1 eV is selected, which falls within the range from 300 MHz to 1 GHz. In the examples, a frequency band in the vicinity of 450 MHz was used.
  • the dielectric member 10 quartz or alumina can be used.
  • a heat-resistant polymer with a low dielectric loss such as polyimide may also be used.
  • a wafer mounting electrode 11 is disposed, on which a wafer 12 is supported by electrostatic adsorption.
  • a power source for electrostatic adsorption is not shown.
  • a high frequency bias is applied from a high frequency power source 13 to the wafer mounting electrode 11 to draw ions in the plasma into the wafer 12 .
  • the plasma emission intensity of a reaction product and the changes in interference light are observed by monitors 15 and 16 , so that the end point is determined through a controller 17 . Further, the plasma processing apparatus also includes an inspection unit for determining the line width or the like of the wafer processed by a critical dimension measurement SEM.
  • the controller 17 controls the overall plasma processing apparatus including the control of the mass flow controller 3 , the power source 7 , the high frequency power source 13 , the inspection unit, and the like.
  • the controller 17 is composed of a computer including, for example, a CPU, a memory, a program, an external memory, and an input/output unit.
  • the wafers after processing are inspected for the conditions of the residue one by one by the inspection unit, so that the quality of each wafer is determined.
  • the wafers rejected because of large residues thereon upon the inspection are eliminated, and are not fed to the subsequent processing step.
  • the inspection information is reflected in the subsequent processing step. For example, for the wafer which has been identified as being acceptable upon inspection, but has a relatively larger residue thereon, a correction processing with attention given to the residue is performed in the subsequent step.
  • a display unit is included as the input/output unit of the controller 17 , wherein the state of the residue of every wafer, the pass/fail results of the inspection, the current operation recipe, and the like are displayed.
  • the antenna 6 and a processing chamber inner wall 14 are temperature controlled. Namely, a refrigerant is introduced form a thermoregulator not shown to the antenna 6 and the processing chamber inner wall 14 to control the temperature, so that the antenna 6 and the inner wall 14 are kept at a constant temperature.
  • the temperature was set so as to be controlled in the range of 30 to 80° C.
  • the vacuum chamber directly connected to the processing chamber 1 is equipped with a turbo-molecular pump with a pumping speed of about 2000 L/s to 3000 L/s. Further, although not shown, the opening of the turbo-molecular pump is equipped with a conductance valve for controlling the pumping speed, so that the pumping speed is controlled to achieve the flow rate and the pressure suitable for etching and ashing. Further, a stop valve is also disposed for isolating the turbo-molecular pump for air release or the like.
  • a wafer is carried in by a carrier arm from a carrying chamber, and delivered onto the wafer mounting electrode 11 .
  • the carrier arm retreats, and the valve between the processing chamber 1 and the carrying chamber is closed.
  • the wafer mounting electrode 11 moves upward, and stops at a position suitable for etching and ashing.
  • the distance between the wafer 12 and the gas supply plate 5 is set at 30 nm to 100 nm.
  • a plasma is generated in the vacuum chamber by means of a plasma source to perform etching on the wafer. Then, ashing is performed in the same vacuum chamber to perform the removal of the mask material or the like.
  • the ashing in the examples of the present invention basically comprises the following two steps: first step and second step.
  • the first step performs the removal of the upper layer of the wafer surface, i.e., the cured layer of the mask material surface and the Si-containing layer.
  • the second step performs the removal of the lower layer of the wafer surface, i.e., the mask material.
  • One example of the processing conditions of each step will be shown as follows.
  • Ashing gas Mixed gas of O 2 and CF 4
  • High frequency power source for wafer Frequency 800 MHz, Output 300 W
  • Ashing gas O 2 Single gas
  • the coils 2 were applied with a current to generate a resonance magnetic field of 0.016 T with a UHF microwave of 450 MHz between the gas supply plate 5 and the wafer mounting electrode 11 (i.e., the wafer 12 ). Then, the microwave power source 7 was operated. This accordingly results in generation of an intense plasma in an ECR area with a magnetic field intensity of 0.016 T due to electron cyclotron resonance.
  • the ECR position can be freely controlled by the magnetic field coils 2 , and hence it is possible to obtain the optimum ion density distribution.
  • the ECR area was formed in convex with respect to the wafer 12 .
  • a high voltage is applied from a DC power source connected in parallel to the high frequency power source 13 to the wafer mounting electrode 11 , so that the wafer 12 is electrostatically adsorbed on the wafer mounting electrode 11 .
  • a helium gas is introduced to the back of the wafer 12 electrostatically adsorbed thereon.
  • the wafer is temperature controlled through the helium gas between the wafer mounting side of the wafer mounting electrode 11 temperature controlled by a refrigerant and the wafer.
  • the high frequency power source 13 is operated, so that a high frequency bias is applied to the wafer mounting electrode 11 .
  • ions are made vertically incident from the plasma upon the wafer 12 .
  • ashing is started. Ashing is terminated in a prescribed ashing time.
  • the plasma emission intensity of the reaction product and the changes in interference light are observed by means of the monitors 15 and 16 , so that the end point is determined through the controller 17 to determine the ashing completion time.
  • appropriate overashing is carried out, and then ashing is completed. Ashing is completed when the application of a bias voltage from the high frequency power source 13 has been stopped through the controller 17 . Simultaneously therewith, the supply of an ashing gas is also stopped.
  • the processing time of the first step is 30 seconds
  • the processing time of the second step is about 240 seconds.
  • Switching between the first step and the second step may be properly accomplished by previously acquiring the data on the same processing conditions, and setting their respective times. Alternatively, the switching may also be accomplished automatically in the following manner. Namely, the changes in plasma emission intensity of the reaction product are monitored. Thus, the processing of the upper layer on the wafer surface is performed in the first step. Upon completion of the processing, the process shifts to the second step, wherein the lower layer on the wafer surface is processed.
  • the surface of the wafer 12 is so configured that a (C-, and H-containing) resist 122 for forming a prescribed pattern such as a trench 123 in the surface is formed on an insulating film 120 made of SiOC formed on the underlying film SiC.
  • the inner wall surface 100 of the processing chamber 1 is in a clean state free from foreign matters such as reaction products attached thereto.
  • a cured layer 124 of the resist resulting from heat input from the plasma is formed in the upper surface of the resist 122 .
  • Si in the insulating film 120 separated by etching is also deposited.
  • a deposition layer 126 of reaction products based on C which is the component of the resist and based on Si which is the component of a material to be etched is formed.
  • a step of desorbing the electrostatically adsorbed wafer 12 from the wafer mounting electrode 11 wherein argon, a gas species actually used for ashing, or the like is used as an electric charge-removing gas.
  • the supply of an electrostatic adsorption voltage is stopped, and an electric supply line is connected to a ground.
  • a charge removal time of about 10 seconds is set, while keeping the discharge of a microwave.
  • the electric charges on the wafer 12 are removed away into the ground through the plasma, which allows the wafer 12 to be desorbed with ease.
  • the supply of the electric charge removing gas is stopped, and the supply of the microwave is also stepped. Further, the supply of a current to the coils 2 is also stopped. Whereas, the wafer mounting electrode 11 is moved downward to the height of the wafer delivery position.
  • the processing chamber 1 is evacuated to a high vacuum for some time.
  • the valve between the carrying chambers is opened, and a carrier arm is inserted thereinto to receive the wafer 12 , and to carry it out.
  • ashing is carried out in accordance with the foregoing procedure again. Up to this, the typical flow of the ashing process has been described.
  • One of the features of the present invention is that, as the conditions for ashing, the processing pressure is low, while the frequency of the UHF microwave power source is high.
  • the removal of the mask material is carried out under low pressure.
  • the second step using a plasma of only an oxygen gas is carried out.
  • the reduction in processing pressure and the increase in frequency of UHF microwave power source facilitate the control of oxygen radicals.
  • FIG. 3 shows the desirable ranges of the processing pressure and the frequency of the power source in the method of the present invention.
  • the processing pressure is desirably not more than 2 Pa from the viewpoint of reducing the damages to the film layer after etching. Namely, it is desirable that ashing is carried out within the scope of a processing pressure of 0.2 to 2 Pa, and a frequency of the UHF microwave of not less than 100 MHz, indicated as the “effective area” of FIG. 3.
  • Table 1 shows the characteristic processing conditions of one example of the present invention, and the comparative examples of effects in the case where the conditions are partly changed therefrom.
  • TABLE 1 Processing chamber Surface System O 2 gas CF 4 gas pressure Bias residue Deterioration 1 Supplied None High None Observed Observed pressure 2 Supplied Supplied High None Si removed Observed pressure Cured layer left 3 Supplied Supplied Low None Si removed Observed pressure Cured layer removed 4 Supplied (1) Supplied Low (1) Applied Same as None (present (2) None pressure (2) None above invention
  • Ashing of a sample in which the thickness of the lower layer on the wafer surface, i.e., the mask material is 100 nm was carried out under the same conditions as those in Example 1, except that processing pressure was 2 Pa, UHF microwave power source had a frequency of 450 MHz, and an output of 400 W.
  • Example 4 Cleaning of the inner wall surface of the processing chamber 1 was carried out under the same processing conditions as those in Example 1, so that the C-based, or Si-based reaction product was removed.
  • This example 4 can be considered as a process for performing cleaning subsequent to the processing of a plurality of wafers under the conditions of Example 1.
  • the fluorine-containing gas to be supplied in the first step is preferably any of CHF 3 , CH 2 F 2 , CF 4 , and SF 6 .
  • a mixed gas of a fluorine-containing gas and an oxygen gas is used as an ashing gas.
  • Use of a mixed gas of a fluorine-containing gas and an oxygen gas as an ashing gas allows the following steps to be carried out at the same time: removal of the silicon component left on the mask material surface and the mask material in the area including the cured mask layer and the like; and the removal of the carbon-based, and silicon-based deposits deposited on the inner wall of the vacuum chamber.
  • the removal of the mask material is carried out under low pressure.
  • a plasma of only an oxygen gas is used.

Abstract

For a surface processing apparatus using a plasma, a mixed gas of a fluorine-containing gas and an oxygen gas is used as an ashing gas. A mixed gas of an oxygen gas and a fluorine-containing gas is introduced as an ashing gas. This allows the following steps to be carried out at the same time: removal of the silicon component left on the mask material surface and the mask material in the area including the cured mask layer and the like; and the removal of the carbon-based, and silicon-based deposits deposited on the inner wall of a vacuum chamber. In addition, the removal of the mask material is performed under low pressure, and in the subsequent step to a step using a mixed gas of a fluorine-containing gas and an oxygen gas, a plasma of only an oxygen gas is used. As a result, it becomes possible to reduce the damages (etching) to the film layer after etching.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a surface processing apparatus and a surface processing method of a sample such as a semiconductor element. In particular, it relates to a surface processing apparatus and a surface processing method suitable for performing etching and ashing of the semiconductor surface using a plasma. [0001]
  • BACKGROUND OF THE INVENTION
  • In the semiconductor manufacture process, a plasma processing apparatus is widely used in the fine processing processes such as film deposition, etching, and ashing. The process by plasma processing performs a prescribed process in the following manner. A process gas introduced into a vacuum chamber (reactor) is transformed into a plasma by plasma generation means. The resulting plasma is allowed to react on the semiconductor wafer surface to perform a fine processing, and volatile reaction products are discharged. [0002]
  • The present invention covers the apparatus utilizing a plasma in general. Now, the prior art will be explained by taking as an example an apparatus called an ECR (Electron Cyclotron Resonance) system which is one of those apparatuses. This ECR system generates a plasma by microwave discharge in a vacuum chamber externally applied with a magnetic field. In order to accelerate ions incident on a sample, a bias voltage is applied to the sample. [0003]
  • The device configuration of a semiconductor element has become increasingly complicated in recent years, so that there are demands for an increase in speed of processing and a reduction in number of steps in the manufacturing process thereof. Namely, for a semiconductor integrated device, with a request for downsizing, for example, for a pitch between wirings of about 0.2 μm or less, the capacitance between neighboring wirings relatively increases at the wiring portion. If a conventional silicon dioxide film is used as an insulating material between wirings of such a device, it becomes impossible to enjoy benefits due to higher speed of a transistor resulting from downsizing. For this reason, a material with a low dielectric constant (k value) such as SiOC is employed as an interwiring insulating material. [0004]
  • The material with a low dielectric constant (k value) is mainly used in combination with copper as a wiring material, and formed by a process called dual damascene. This requires a step of etching processing of an insulating film. The dual damascene formation process includes a step of processing and transferring a trench profile into a porous insulating film using a hard mask, and imparting a prescribed profile to a sample having a hole profile processed in the previous step. Such a technology is disclosed, for example, in Japanese Patent Laid-open No. H 9(1997)-115878. [0005]
  • Further, a method for monitoring the processing state, and controlling the process is also adopted in the prior art. As the method for monitoring the processing state, and controlling the process, for example, there is known the method in which a reflected interference light from a processed wafer is monitored to terminate etching processing, disclosed in U.S. Pat. No. 5,658,418. [0006]
  • Still further, in the prior art, removal of the mask material is carried out by means of another vacuum chamber or device in the same apparatus after the completion of etching. For example, Japanese Patent Laid-open No. 2000-352827 discloses a technology for removing the etching residues and the resist surface cured layer by a wet processing. [0007]
  • In the prior art, removal of the mask material is carried out by means of another vacuum chamber or device in the same apparatus after the completion of etching. This results in an increase in number of steps, and accordingly, a reduction in total throughput, and requires another vacuum chamber (device). [0008]
  • Further, with a method for carrying out the removal of the mask material by only an oxygen plasma, it is difficult to remove a silicon component remaining on the surface, and the mask material including a cured mask layer. Now, a consideration will be given to the case where a prescribed pattern such as a [0009] trench 121 is formed to the position indicated by a dotted line in the resist formed on an insulating film 120 made of SiOC as the surface processing of a wafer as shown in FIG. 4. On the surface of the mask material after etching, there remains an area including a cured layer 124 of a resist resulting from heat input from a plasma. In the cured layer 124, Si in the insulating film 120 separated by etching is also deposited. With the method for carrying out the removal of the mask material only by an oxygen plasma, it is impossible to remove such a cured mask layer in the surface of the mask material. Further, a damaged portion 125 in the film layer also occurs.
  • SUMMARY OF THE INVENTION
  • It is an object of the present invention to solve the foregoing problems, and to provide surface processing apparatus and surface processing method for readily carrying out ashing and removal of a mask material in the same vacuum chamber. [0010]
  • It is another object of the present invention to provide surface processing apparatus and surface processing method for readily carrying out the removal of a silicon component left on the mask material surface after etching and the mask material in the area including the cured mask layer and the like, and causing less damages to the film layer after etching. [0011]
  • It is a still other object of the present invention to provide surface processing apparatus and surface processing method for readily carrying out the removal of the mask material, and also carrying out the removal of carbon-based and silicon-based deposits deposited on the inner wall of a vacuum chamber upon etching. [0012]
  • In accordance with one aspect of the present invention, a sample surface processing apparatus comprises: a vacuum chamber; means for generating a plasma in the vacuum chamber; a sample stage for mounting a sample to be surface processed by the plasma thereon; and a power source for applying a high frequency bias to the sample, wherein the surface processing of the sample is performed by the plasma. The apparatus further comprises a function of monitoring the plasma emission intensity of a reaction product in the vacuum chamber, and the changes in interference light, automatically determining the state of the surface processing based on the monitor result, and controlling the high frequency bias. [0013]
  • In accordance with the present invention, it is possible to accomplish etching and ashing by the use of the same vacuum chamber. [0014]
  • In accordance with another aspect of the present invention, a sample surface processing apparatus for performing surface processing of a sample comprises: a vacuum chamber; means for generating a plasma therein; a sample stage for mounting the sample to be surface processed by the plasma thereon; and a power source for applying a high frequency bias to the sample. The apparatus further comprises means for introducing a mixed gas of an oxygen gas and a fluorine-containing gas as an ashing gas into the vacuum chamber. [0015]
  • In accordance with the present invention, a mixed gas of an oxygen gas and a fluorine-containing gas is introduced as an ashing gas, and subsequently, ashing is performed with a plasma using only an oxygen gas. As a result, it becomes possible to increase the selectivity between the mask material and a material to be etched. By the synergistic effects thereof, it is possible to accomplish ashing of the mask material while preserving the shape of a pattern after etching as much as possible, with the high selectivity being kept. [0016]
  • In accordance with a still other aspect of the present invention, a sample surface processing method comprises: generating a plasma in a vacuum chamber, and applying a high frequency bias to a sample stage for mounting a sample thereon, for performing the surface processing of the sample, and the method is characterized in that a mixed gas of an oxygen gas and a fluorine-containing gas is introduced into the vacuum chamber to perform the surface processing of the sample by the plasma. [0017]
  • In accordance with the present invention, a mixed gas of an oxygen gas and a fluorine-containing gas is introduced as an ashing gas. This allows the following steps to be carried out at the same time: removal of the silicon component left on the mask material surface and the mask material in the area including the cured mask layer and the like; and the removal of the carbon-based, and silicon-based deposits deposited on the inner wall of the vacuum chamber. In addition, the removal of the mask material is performed under low pressure, and in the subsequent step to the step using a mixed gas of a fluorine-containing gas and an oxygen gas, a plasma of only an oxygen gas is used. As a result, it becomes possible to reduce the damages (etching) to the film layer after etching.[0018]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic diagram showing an overall configuration of a plasma processing apparatus to which the present invention is applied; [0019]
  • FIGS. 2A to [0020] 2C are diagrams respectively showing the states of the surface of a sample and the vacuum chamber inner wall in a processing method of the present invention;
  • FIG. 3 is a diagram showing the desirable ranges of the processing pressure and the frequency of a power source in the method of the present invention; and [0021]
  • FIG. 4 is a diagram showing the states of the surface of a sample and the vacuum chamber inner wall in a prior art example.[0022]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Below, the present invention will be described by way of examples. First, a description will be given to the configuration of a plasma etching apparatus to which surface processing of a sample of the present invention is applied. [0023]
  • FIG. 1 is a schematic diagram of a plasma processing apparatus applying electron cyclotron resonance (ECR), to which the present invention is suitably applicable. The plasma processing apparatus includes a plurality of [0024] processing chambers 1 which are vacuum chambers. Around each processing chamber 1, coils 2 are disposed in order to generate a magnetic field for electron cyclotron resonance (ECR). A gas for etching is supplied to each processing chamber 1 through a gas supply tube 4 connected to each gas source 30 via each mass flow controller 3. The etching gas is introduced from a gas supply plate 5 made of silicon or glassy carbon and provided with about several hundreds fine holes with a diameter of about 0.4 to 0.5 nm into each processing chamber 1. A disc-like antenna 6 for radiating a UHF band microwave is disposed above the gas supply plate 5. The microwave is fed from a power source 7 through a matching circuit 8 and a lead-in axis 9 to the antenna 6. The microwave is radiated from around the antenna 6, and the resonance electric field in the space above the antenna 6 is introduced into each processing chamber through a dielectric member 10. For the frequency of the microwave, the band capable of making the electron temperature of the plasma as low as 0.25 eV to 1 eV is selected, which falls within the range from 300 MHz to 1 GHz. In the examples, a frequency band in the vicinity of 450 MHz was used. Further, as the dielectric member 10, quartz or alumina can be used. Alternatively, a heat-resistant polymer with a low dielectric loss such as polyimide may also be used.
  • Under the [0025] gas supply plate 5, a wafer mounting electrode 11 is disposed, on which a wafer 12 is supported by electrostatic adsorption. A power source for electrostatic adsorption is not shown. A high frequency bias is applied from a high frequency power source 13 to the wafer mounting electrode 11 to draw ions in the plasma into the wafer 12.
  • The plasma emission intensity of a reaction product and the changes in interference light are observed by [0026] monitors 15 and 16, so that the end point is determined through a controller 17. Further, the plasma processing apparatus also includes an inspection unit for determining the line width or the like of the wafer processed by a critical dimension measurement SEM.
  • Incidentally, the [0027] controller 17 controls the overall plasma processing apparatus including the control of the mass flow controller 3, the power source 7, the high frequency power source 13, the inspection unit, and the like. The controller 17 is composed of a computer including, for example, a CPU, a memory, a program, an external memory, and an input/output unit. The wafers after processing are inspected for the conditions of the residue one by one by the inspection unit, so that the quality of each wafer is determined. The wafers rejected because of large residues thereon upon the inspection are eliminated, and are not fed to the subsequent processing step. On the other hand, also for the wafers identified as being acceptable as a result of the inspection, the inspection information is reflected in the subsequent processing step. For example, for the wafer which has been identified as being acceptable upon inspection, but has a relatively larger residue thereon, a correction processing with attention given to the residue is performed in the subsequent step.
  • Further, a display unit is included as the input/output unit of the [0028] controller 17, wherein the state of the residue of every wafer, the pass/fail results of the inspection, the current operation recipe, and the like are displayed.
  • Further, the [0029] antenna 6 and a processing chamber inner wall 14 are temperature controlled. Namely, a refrigerant is introduced form a thermoregulator not shown to the antenna 6 and the processing chamber inner wall 14 to control the temperature, so that the antenna 6 and the inner wall 14 are kept at a constant temperature. In the examples, the temperature was set so as to be controlled in the range of 30 to 80° C.
  • The vacuum chamber directly connected to the [0030] processing chamber 1 is equipped with a turbo-molecular pump with a pumping speed of about 2000 L/s to 3000 L/s. Further, although not shown, the opening of the turbo-molecular pump is equipped with a conductance valve for controlling the pumping speed, so that the pumping speed is controlled to achieve the flow rate and the pressure suitable for etching and ashing. Further, a stop valve is also disposed for isolating the turbo-molecular pump for air release or the like.
  • Next, a description will be given to etching and ashing using the plasma etching apparatus in the examples of the present invention. [0031]
  • To the [0032] processing chamber 1 in the evacuated state to a high vacuum, although not shown, a wafer is carried in by a carrier arm from a carrying chamber, and delivered onto the wafer mounting electrode 11. The carrier arm retreats, and the valve between the processing chamber 1 and the carrying chamber is closed. Then, the wafer mounting electrode 11 moves upward, and stops at a position suitable for etching and ashing. For the examples, the distance between the wafer 12 and the gas supply plate 5 (the distance between electrodes) is set at 30 nm to 100 nm.
  • First, a plasma is generated in the vacuum chamber by means of a plasma source to perform etching on the wafer. Then, ashing is performed in the same vacuum chamber to perform the removal of the mask material or the like. [0033]
  • The ashing in the examples of the present invention basically comprises the following two steps: first step and second step. The first step performs the removal of the upper layer of the wafer surface, i.e., the cured layer of the mask material surface and the Si-containing layer. The second step performs the removal of the lower layer of the wafer surface, i.e., the mask material. One example of the processing conditions of each step will be shown as follows. [0034]
  • EXAMPLE 1
  • (1) First Step: [0035]
  • Ashing gas=Mixed gas of O[0036] 2 and CF4
  • Gas flow rate (O[0037] 2/CF4)=100 sccm/5 sccm
  • Processing pressure=0.5 Pa [0038]
  • UHF microwave power source=Frequency 450 MHz, Output 400 W [0039]
  • High frequency power source for wafer=Frequency 800 MHz, Output 300 W [0040]
  • (2) Second step [0041]
  • Ashing gas=O[0042] 2 Single gas
  • Gas flow rate (O[0043] 2)=100 sccm
  • Processing pressure=0.5 Pa [0044]
  • UHF microwave power source=Frequency 450 MHz, Output 400 W [0045]
  • Output of high frequency power source for wafer=0 W [0046]
  • In ashing, in either of the steps, the [0047] coils 2 were applied with a current to generate a resonance magnetic field of 0.016 T with a UHF microwave of 450 MHz between the gas supply plate 5 and the wafer mounting electrode 11 (i.e., the wafer 12). Then, the microwave power source 7 was operated. This accordingly results in generation of an intense plasma in an ECR area with a magnetic field intensity of 0.016 T due to electron cyclotron resonance.
  • For making uniform the ashing characteristics, it is necessary to achieve a uniform ion density incident on the surface of the [0048] wafer 12. However, the ECR position can be freely controlled by the magnetic field coils 2, and hence it is possible to obtain the optimum ion density distribution. In this example, the ECR area was formed in convex with respect to the wafer 12.
  • After ignition of the plasma, although not shown, a high voltage is applied from a DC power source connected in parallel to the high [0049] frequency power source 13 to the wafer mounting electrode 11, so that the wafer 12 is electrostatically adsorbed on the wafer mounting electrode 11. A helium gas is introduced to the back of the wafer 12 electrostatically adsorbed thereon. Thus, the wafer is temperature controlled through the helium gas between the wafer mounting side of the wafer mounting electrode 11 temperature controlled by a refrigerant and the wafer.
  • Then, the high [0050] frequency power source 13 is operated, so that a high frequency bias is applied to the wafer mounting electrode 11. As a result, ions are made vertically incident from the plasma upon the wafer 12. Simultaneously upon application of a bias voltage to the wafer 12, ashing is started. Ashing is terminated in a prescribed ashing time. Alternatively, the plasma emission intensity of the reaction product and the changes in interference light are observed by means of the monitors 15 and 16, so that the end point is determined through the controller 17 to determine the ashing completion time. Thus, appropriate overashing is carried out, and then ashing is completed. Ashing is completed when the application of a bias voltage from the high frequency power source 13 has been stopped through the controller 17. Simultaneously therewith, the supply of an ashing gas is also stopped.
  • When the thickness of the mask material is 300 nm to 400 nm, the processing time of the first step is 30 seconds, and the processing time of the second step is about 240 seconds. Switching between the first step and the second step may be properly accomplished by previously acquiring the data on the same processing conditions, and setting their respective times. Alternatively, the switching may also be accomplished automatically in the following manner. Namely, the changes in plasma emission intensity of the reaction product are monitored. Thus, the processing of the upper layer on the wafer surface is performed in the first step. Upon completion of the processing, the process shifts to the second step, wherein the lower layer on the wafer surface is processed. [0051]
  • By reference to FIGS. 2A to [0052] 2C, a description will be given to the state of surface processing of the wafer by etching and ashing in the examples of the present invention.
  • In the initial state of the wafer shown in FIG. 2A, the surface of the [0053] wafer 12 is so configured that a (C-, and H-containing) resist 122 for forming a prescribed pattern such as a trench 123 in the surface is formed on an insulating film 120 made of SiOC formed on the underlying film SiC. At this step, the inner wall surface 100 of the processing chamber 1 is in a clean state free from foreign matters such as reaction products attached thereto. After etching, as shown in FIG. 2B, a cured layer 124 of the resist resulting from heat input from the plasma is formed in the upper surface of the resist 122. Further, in the cured layer 124, Si in the insulating film 120 separated by etching is also deposited. Whereas, on the inner wall of the processing chamber 1, a deposition layer 126 of reaction products based on C which is the component of the resist and based on Si which is the component of a material to be etched is formed.
  • If ashing is carried out under the foregoing conditions, the selectivity between the mask material and the film layer after etching increases. For this reason, it is easy to remove the cured [0054] layer 124 in the surface of the unnecessary mask material. Namely, as shown in FIG. 2C, the cured layer 124 in the surface of the mask material is completely removed, and the deposition layer 126 on the inner wall of the processing chamber 1 is also completely removed.
  • Then, a step of desorbing the electrostatically adsorbed [0055] wafer 12 from the wafer mounting electrode 11 is required, wherein argon, a gas species actually used for ashing, or the like is used as an electric charge-removing gas. The supply of an electrostatic adsorption voltage is stopped, and an electric supply line is connected to a ground. Then, a charge removal time of about 10 seconds is set, while keeping the discharge of a microwave. As a result, the electric charges on the wafer 12 are removed away into the ground through the plasma, which allows the wafer 12 to be desorbed with ease. Upon completion of the electric charge removing step, the supply of the electric charge removing gas is stopped, and the supply of the microwave is also stepped. Further, the supply of a current to the coils 2 is also stopped. Whereas, the wafer mounting electrode 11 is moved downward to the height of the wafer delivery position.
  • Thereafter, the [0056] processing chamber 1 is evacuated to a high vacuum for some time. Upon completion of high vacuum evacuation, the valve between the carrying chambers is opened, and a carrier arm is inserted thereinto to receive the wafer 12, and to carry it out. For the subsequent etching, another wafer is carried in, and ashing is carried out in accordance with the foregoing procedure again. Up to this, the typical flow of the ashing process has been described.
  • One of the features of the present invention is that, as the conditions for ashing, the processing pressure is low, while the frequency of the UHF microwave power source is high. The removal of the mask material is carried out under low pressure. In addition, following the first step using a mixed gas of a fluorine-containing gas and an oxygen gas, the second step using a plasma of only an oxygen gas is carried out. As a result, it becomes possible to reduce the damages to the film layer after etching (side etching and etching of the trench bottom). Namely, the reduction in processing pressure and the increase in frequency of UHF microwave power source facilitate the control of oxygen radicals. As a result, it is possible to perform the removal of the hard mask material while reducing the damages to the film layer after etching. [0057]
  • FIG. 3 shows the desirable ranges of the processing pressure and the frequency of the power source in the method of the present invention. [0058]
  • In order to stabilize the discharge in the vacuum processing chamber, it is desirable that the relationship between the frequency of the power source and the processing pressure falls within the diagonally shaded area of FIG. 3. On the other hand, the processing pressure is desirably not more than 2 Pa from the viewpoint of reducing the damages to the film layer after etching. Namely, it is desirable that ashing is carried out within the scope of a processing pressure of 0.2 to 2 Pa, and a frequency of the UHF microwave of not less than 100 MHz, indicated as the “effective area” of FIG. 3. [0059]
  • Table 1 shows the characteristic processing conditions of one example of the present invention, and the comparative examples of effects in the case where the conditions are partly changed therefrom. [0060]
    TABLE 1
    Processing
    chamber Surface
    System O2 gas CF4 gas pressure Bias residue Deterioration
    1 Supplied None High None Observed Observed
    pressure
    2 Supplied Supplied High None Si removed Observed
    pressure Cured
    layer left
    3 Supplied Supplied Low None Si removed Observed
    pressure Cured
    layer
    removed
    4 Supplied (1) Supplied Low (1) Applied Same as None
    (present (2) None pressure (2) None above
    invention
  • EXAMPLE 2
  • Ashing of a sample in which the thickness of the lower layer on the wafer surface, i.e., the mask material is 100 nm was carried out under the same conditions as those in Example 1, except that processing pressure was 2 Pa, UHF microwave power source had a frequency of 450 MHz, and an output of 400 W. [0061]
  • EXAMPLE 3
  • Ashing of the wafer surface and cleaning of the inner wall surface of the [0062] processing chamber 1 were simultaneously carried out under the same conditions as those in Example 1.
  • EXAMPLE 4
  • Cleaning of the inner wall surface of the [0063] processing chamber 1 was carried out under the same processing conditions as those in Example 1, so that the C-based, or Si-based reaction product was removed. This example 4 can be considered as a process for performing cleaning subsequent to the processing of a plurality of wafers under the conditions of Example 1.
  • Incidentally, the fluorine-containing gas to be supplied in the first step is preferably any of CHF[0064] 3, CH2F2, CF4, and SF6.
  • In accordance with the example of the present invention, with the surface processing apparatus using a plasma, a mixed gas of a fluorine-containing gas and an oxygen gas is used as an ashing gas. Use of a mixed gas of a fluorine-containing gas and an oxygen gas as an ashing gas allows the following steps to be carried out at the same time: removal of the silicon component left on the mask material surface and the mask material in the area including the cured mask layer and the like; and the removal of the carbon-based, and silicon-based deposits deposited on the inner wall of the vacuum chamber. [0065]
  • Further, the removal of the mask material is carried out under low pressure. In addition, in the subsequent step to the step using a mixed gas of a fluorine-containing gas and an oxygen gas, a plasma of only an oxygen gas is used. As a result, it becomes possible to reduce the damages to the film layer after etching (side etching and etching of trench bottom). [0066]
  • Incidentally, in these examples, a description has been given assuming that the UHF type ECR plasma etching apparatus is used. However, use of other plasma sources does not create any problem, and the plasma source to be used is not limited to the UHF type ECR plasma etching apparatus. Therefore, the present invention is applicable to even other induction type plasma apparatuses than the microwave type apparatus. [0067]
  • Further, a description was given to the case where etching and ashing are carried out in the same surface processing apparatus in accordance with the examples of the present invention. However, it is also acceptable that etching and ashing are separately carried out in different surface processing apparatuses. [0068]
  • As described above, in accordance with the present invention, it is possible to accomplish etching and ashing by the use of the same vacuum chamber. Further, the step using a fluorine-containing as an ashing additive gas, and the ashing step with an oxygen plasma are employed. This allows an increase in selectivity between the mask material and the material to be etched. By the synergistic effects thereof, it is possible to accomplish ashing of the mask material while preserving the shape of a pattern after etching as much as possible, with the high selectivity being kept. [0069]

Claims (12)

What is claimed is:
1. A sample surface processing apparatus, comprising:
a vacuum chamber; means for generating a plasma in the vacuum chamber; a sample stage for mounting a sample to be surface processed by the plasma thereon; and a power source for applying a high frequency bias to the sample, wherein the surface processing of the sample is performed by the plasma, and
said apparatus further comprising a function of monitoring the plasma emission intensity of a reaction product in the vacuum chamber, and the changes in interference light, automatically determining the state of the surface processing based on the monitor result, and controlling the high frequency bias.
2. The sample surface processing apparatus according to claim 1, further comprising means for introducing a mixed gas of an oxygen gas and a fluorine-containing gas as an ashing gas into the vacuum chamber.
3. A sample surface processing apparatus, comprising:
a vacuum chamber; a plasma source for generating a plasma in the vacuum chamber; a sample stage for mounting a sample thereon; and a power source for applying a high frequency bias to the sample, wherein the surface processing of the sample is performed by the plasma, and
said apparatus further comprising: means for introducing an oxygen gas or a mixed gas of an oxygen gas and a fluorine-containing gas into the vacuum chamber; and means for selectively supplying the oxygen gas or the mixed gas according to the surface state of the sample, and performing the surface processing of the sample within the scope of a processing pressure of not more than 2 Pa and a frequency of the plasma source of not less than 100 MHz.
4. The sample surface processing apparatus according to claim 3, further comprising a function of monitoring the changes in plasma emission intensity of a reaction product in the vacuum chamber, automatically determining the state of the surface processing based on the monitor result, and performing switching between supplying the oxygen gas and the mixed gas, and switching of the high frequency bias.
5. The sample surface processing apparatus according to claim 4, further comprising a display unit for displaying the change of the method for processing the sample based on the monitor result.
6. A sample surface processing method comprising: generating a plasma in a vacuum chamber, and applying a high frequency bias to a sample stage for mounting a sample thereon, for performing the surface processing of the sample, wherein a mixed gas of an oxygen gas and a fluorine-containing gas is introduced into the vacuum chamber to perform the surface processing of the sample by the plasma.
7. A sample surface processing method by a sample processing apparatus comprising: a vacuum chamber; means for generating a plasma in the vacuum chamber; a sample stage for mounting a sample to be processed thereon; and a power source for applying a high frequency bias to the sample, wherein the surface processing of the sample is performed by the plasma,
said method comprising:
introducing a mixed gas of an oxygen gas and a fluorine-containing gas into the vacuum chamber;
performing surface processing of the sample by the plasma;
monitoring the plasma emission intensity of a reaction product in the vacuum chamber, and the changes in interference light; and
automatically determining the state of the surface processing based on the monitor result, and performing switching between supplying the oxygen gas and the mixed gas, and switching of the high frequency bias.
8. The sample surface processing method according to claim 6 or 7, further comprising:
a first step of applying a high frequency bias to the sample, and removing only the surface layer of the mask material of the sample by a plasma of the mixed gas of the oxygen gas and the fluorine-containing gas; and
a second step of stopping the high frequency bias, and removing the mask material left after the removal of the surface layer by an oxygen plasma.
9. The sample surface processing method according to claim 6 or 7, wherein the pressure of the gas during surface processing is set at 0.2 to 2 Pa.
10. The sample surface processing method according to claim 6 or 7, wherein the fluorine-containing gas is preferably any of CHF3, CH2F2, CF4, and SF6.
11. The sample surface processing method according to claim 6 or 7, wherein the removal of the mask material of the sample and the removal of a deposit attached to the sidewall of the vacuum chamber are performed at the same time.
12. The sample surface processing method according to claim 6 or 7, wherein the removal of a deposit attached to the inner wall of the vacuum chamber is performed.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050106875A1 (en) * 2003-09-25 2005-05-19 Tokyo Electron Limited Plasma ashing method
US20050112879A1 (en) * 2002-08-28 2005-05-26 Kiwamu Fujimoto Insulation film etching method
US20060060626A1 (en) * 2004-09-20 2006-03-23 Guo-Hong Chang Golf ball pocket
US20060154486A1 (en) * 2005-01-11 2006-07-13 Tokyo Electron Limited Low-pressure removal of photoresist and etch residue
US7700494B2 (en) 2004-12-30 2010-04-20 Tokyo Electron Limited, Inc. Low-pressure removal of photoresist and etch residue
US20100154707A1 (en) * 2004-01-28 2010-06-24 Tokyo Electron Limited Process chamber cleaning method in substrate processing apparatus, substrate processing apparatus, and substrate processing method

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7815815B2 (en) 2006-08-01 2010-10-19 Sony Corporation Method and apparatus for processing the peripheral and edge portions of a wafer after performance of a surface treatment thereon
US7910477B2 (en) * 2007-12-28 2011-03-22 Texas Instruments Incorporated Etch residue reduction by ash methodology

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010015175A1 (en) * 2000-02-21 2001-08-23 Toshio Masuda Plasma processing system and apparatus and a sample processing method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3529849B2 (en) * 1994-05-23 2004-05-24 富士通株式会社 Method for manufacturing semiconductor device
JPH09129594A (en) 1995-03-23 1997-05-16 Sharp Corp Method and apparatus for dry etching
JPH10335309A (en) 1997-05-29 1998-12-18 Sony Corp Plasma treating system
JP3252789B2 (en) 1998-04-03 2002-02-04 日本電気株式会社 Etching method
US6492277B1 (en) * 1999-09-10 2002-12-10 Hitachi, Ltd. Specimen surface processing method and apparatus
JP2003068705A (en) * 2001-08-23 2003-03-07 Hitachi Ltd Manufacturing method of semiconductor element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010015175A1 (en) * 2000-02-21 2001-08-23 Toshio Masuda Plasma processing system and apparatus and a sample processing method

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US20050112879A1 (en) * 2002-08-28 2005-05-26 Kiwamu Fujimoto Insulation film etching method
US6967171B2 (en) * 2002-08-28 2005-11-22 Tokyo Electron Limited Insulation film etching method
US20050106875A1 (en) * 2003-09-25 2005-05-19 Tokyo Electron Limited Plasma ashing method
US20100154707A1 (en) * 2004-01-28 2010-06-24 Tokyo Electron Limited Process chamber cleaning method in substrate processing apparatus, substrate processing apparatus, and substrate processing method
US8608901B2 (en) * 2004-01-28 2013-12-17 Tokyo Electron Limited Process chamber cleaning method in substrate processing apparatus, substrate processing apparatus, and substrate processing method
US20060060626A1 (en) * 2004-09-20 2006-03-23 Guo-Hong Chang Golf ball pocket
US7700494B2 (en) 2004-12-30 2010-04-20 Tokyo Electron Limited, Inc. Low-pressure removal of photoresist and etch residue
DE112005003338B4 (en) * 2004-12-30 2011-11-03 Tokyo Electron Ltd. Low pressure removal of photoresist and etch residues
DE112005003338B8 (en) * 2004-12-30 2011-12-15 Tokyo Electron Ltd. Low pressure removal of photoresist and etch residues
US20060154486A1 (en) * 2005-01-11 2006-07-13 Tokyo Electron Limited Low-pressure removal of photoresist and etch residue
US7344993B2 (en) * 2005-01-11 2008-03-18 Tokyo Electron Limited, Inc. Low-pressure removal of photoresist and etch residue

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