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Publication numberUS20040178492 A1
Publication typeApplication
Application numberUS 10/808,502
Publication dateSep 16, 2004
Filing dateMar 25, 2004
Priority dateSep 28, 2001
Also published asCA2462130A1, CA2462130C, CN1559162A, EP1437928A1, EP1437928A4, US7584535, US20070175025, WO2003030602A1
Publication number10808502, 808502, US 2004/0178492 A1, US 2004/178492 A1, US 20040178492 A1, US 20040178492A1, US 2004178492 A1, US 2004178492A1, US-A1-20040178492, US-A1-2004178492, US2004/0178492A1, US2004/178492A1, US20040178492 A1, US20040178492A1, US2004178492 A1, US2004178492A1
InventorsTakehito Tsukamoto, Hiroshi Matsuzawa, Satoshi Akimoto, Masataka Maehara, Takumi Suemoto, Masayuki Ode, Yuichi Sakaki
Original AssigneeToppan Printing Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Multi-layer wiring board, IC package, and method of manufacturing multi-layer wiring board
US 20040178492 A1
Abstract
A multi-layer circuit wiring board comprising a laminate of films, each film having a wiring pattern formed on at least one surface thereof, wherein the wiring pattern formed on each film is electrically connected with the wiring pattern formed on another film which is disposed neighboring thereto through a via-contact layer provided on any one of the neighboring films.
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Claims(51)
What is claimed is:
1. A multi-layer circuit wiring board comprising a laminate of films, each film having a wiring pattern formed on at least one surface thereof, wherein the wiring pattern formed on each film is electrically connected with the wiring pattern formed on another film which is disposed neighboring thereto through a via-contact layer formed in any one of the neighboring films.
2. The multi-layer circuit wiring board according to claim 1, wherein all of said films have almost the same thickness.
3. A method of manufacturing a multi-layer circuit wiring board, which comprises: simultaneously laminating a second flexible resin film on one surface of a first flexible resin film having a first wiring pattern on at least one surface thereof, and a third wiring pattern on another surface of the first flexible resin film, said second flexible resin film having a second wiring pattern formed on at least one surface thereof, and said third flexible resin film having a third wiring pattern formed on at least one surface thereof.
4. A multi-layer circuit wiring board comprising:
a first film having a first wiring pattern formed on one surface thereof, a second wiring pattern formed on another surface thereof, and a first via-contact layer electrically connecting said first wiring pattern with said second wiring pattern;
a second film provided with a third wiring pattern for mounting an IC on one surface thereof, another surface thereof being superimposed on said one surface of said first film;
a third film provided on one surface thereof with a fourth wiring pattern to be electrically connected with a printed wiring board, another surface thereof being superimposed on the other surface of said first film;
a second via-contact layer for electrically connecting said first wiring pattern with said third wiring pattern; and
a third via-contact layer for electrically connecting said second wiring pattern with said fourth wiring pattern.
5. The multi-layer circuit wiring board according to claim 4, wherein said first film comprises a polyimide resin layer, and a first and a second wiring patterns each formed of copper and formed on said polyimide resin layer; said second film comprises a polyimide resin layer and a third wiring pattern formed of copper and formed on said polyimide resin layer; and said third film comprises a polyimide resin layer and a fourth wiring pattern formed of copper and formed on said polyimide resin layer.
6. The multi-layer circuit wiring board according to claim 5, wherein a surface roughness of that surface of the polyimide resin layer on which said wiring pattern is formed, is within a range of 0.01 μm to 5.0 μm based on an average roughness as measured at optional ten points, said polyimide resin layer being at least one film selected from the group consisting of said first film, second film and third film.
7. The multi-layer circuit wiring board according to claim 5, wherein a line width of said wiring pattern formed on said polyimide resin layer is 50 m or less, said polyimide resin layer being at least one film selected from the group consisting of said first film, second film and third film, and a surface roughness of said polyimide resin layer is within a range of 0.01 μm to 5.0 μm based on an average roughness as measured at optional ten points.
8. The multi-layer circuit wiring board according to claim 5, which further comprises a first adhesive layer for bonding said second film to said first film, and a second adhesive layer for bonding said third film to said first film.
9. The multi-layer circuit wiring board according to claim 8, wherein said adhesive layers are formed of a thermosetting adhesive layer containing an epoxy curing component.
10. The multi-layer circuit wiring board according to claim 8, wherein a thickness of each of said adhesive layers is 301 μm or less.
11. The multi-layer circuit wiring board according to claim 4, wherein said first via-contact layer, second via-contact layer and third via-contact layer are formed of a blind via-contact layer, and a ratio of diameter of a bottom of each of these via-contact layers to diameter of a top opening of each of these via-contact layers is within a range of 0.2 to 1.0.
12. The multi-layer circuit wiring board according to claim 4, wherein said first via-contact layer, second via-contact layer and third via-contact layer are formed of a blind via-contact layer, and a ratio of diameter of a bottom of each of these via-contact layers to diameter of a top opening of each of these via-contact layers is within a range of 0.4 to 0.8.
13. The multi-layer circuit wiring board according to claim 4, wherein value of (value of a top opening of each of these via-contact layers)/(total value of a thickness of the conductor layer+a thickness of the second film or the third film+a thickness of the first adhesive layer or of the second adhesive layer) or value of (value of a top opening of each of these via-contact layers)/(total value of a thickness of the conductor layer+a thickness of the first film) is 1.5 or less.
14. A multi-layer circuit wiring board comprising:
a first film having a first wiring pattern formed on one surface thereof; and
a second film provided with a third wiring pattern for mounting an IC on one surface thereof, another surface thereof being superimposed on said one surface of said first film;
wherein said second film is provided with a first via-contact layer for electrically connecting said first wiring pattern with said third wiring pattern.
15. The multi-layer circuit wiring board according to claim 14, wherein said first film comprises a polyimide resin layer and a first wiring pattern formed of copper and formed on said polyimide resin layer; and
said second film comprises a polyimide resin layer and a third wiring pattern formed of copper and formed on one surface of said polyimide resin layer.
16. The multi-layer circuit wiring board according to claim 14, which further comprises a fixing frame which is attached by means of an adhesive to that portion of an IC mounting surface on which said IC is not to be located.
17. The multi-layer circuit wiring board according to claim 16, which said fixing frame is made of a metal or resin.
18. A multi-layer circuit wiring board comprising:
a first film having a first wiring pattern formed on one surface thereof, a second wiring pattern formed on another surface thereof, and a first via-contact layer electrically connecting said first wiring pattern with said second wiring pattern;
a second film provided with a third wiring pattern on one surface thereof, another surface thereof being superimposed on said one surface of said first film;
a third film provided with a fourth wiring pattern on one surface thereof, another surface thereof being superimposed on the other surface of said first film;
a second via-contact layer for electrically connecting said first wiring pattern with said third wiring pattern;
a third via-contact layer for electrically connecting said second wiring pattern with said fourth wiring pattern;
a fourth film provided with a fifth wiring pattern for mounting an IC on one surface thereof, another surface thereof being superimposed on said second film;
a fifth film provided on one surface thereof with a sixth wiring pattern to be electrically connected with a printed wiring board, another surface thereof being superimposed on said third film;
a fourth via-contact layer for electrically connecting said third wiring pattern with said fifth wiring pattern; and
a fifth via-contact layer for electrically connecting said fourth wiring pattern with said sixth wiring pattern.
19. The multi-layer circuit wiring board according to claim 18, wherein said first film comprises a polyimide resin layer and a first and a second wiring patterns each formed of copper and formed on said polyimide resin layer; said second film comprises a polyimide resin layer and a third wiring pattern formed of copper and formed on said polyimide resin layer; said third film comprises a polyimide resin layer and a fourth wiring pattern formed of copper and formed on said polyimide resin layer; said fourth film comprises a polyimide resin layer and a fifth wiring pattern formed of copper and formed on said polyimide resin layer; and said fifth film comprises a polyimide resin layer and a sixth wiring pattern formed of copper and formed on said polyimide resin layer.
20. The multi-layer circuit wiring board according to claim 18, which further comprises:
a first adhesive layer for bonding said second film to said first film;
a second adhesive layer for bonding said third film to said first film;
a third adhesive layer for bonding said fourth film to said second film; and
a fourth adhesive layer for bonding said fifth film to said third film.
21. A multi-layer circuit wiring board comprising a laminate of resin films, each resin film having a wiring pattern formed on at least one surface thereof, wherein the wiring pattern formed on one resin film is electrically connected with a wiring pattern formed on another resin film which is disposed next to said one resin film, through a via-contact layer provided on said one resin film or on said another resin film, a wiring pattern formed on an outermost resin film on one side of said laminate is a wiring pattern for mounting an IC, and a wiring pattern formed on another outermost resin film on another side of said laminate is a wiring pattern to be electrically connected with a printed wiring board.
22. An IC package comprising an IC, and a multi-layer circuit wiring board mounting said IC, wherein said multi-layer circuit wiring board comprising:
a first film having a first wiring pattern formed on one surface thereof, a second wiring pattern formed on another surface thereof, and a first via-contact layer electrically connecting said first wiring pattern with said second wiring pattern;
a second film provided with a third wiring pattern for mounting an IC on one surface thereof, another surface thereof being superimposed on said one surface of said first film;
a third film provided on one surface thereof with a fourth wiring pattern to be electrically connected with a printed wiring board, another surface thereof being superimposed on said other surface of said first film;
a second via-contact layer for electrically connecting said first wiring pattern with said third wiring pattern; and
a third via-contact layer for electrically connecting said second wiring pattern with said fourth wiring pattern.
23. The IC package according to claim 22, wherein said first film comprises a polyimide resin layer and a first and a second wiring patterns each formed of copper and formed on said polyimide resin layer; said second film comprises a polyimide resin layer and a third wiring pattern formed of copper and formed on said polyimide resin layer; and said third film comprises a polyimide resin layer and a fourth wiring pattern formed of copper and formed on said polyimide resin layer.
24. An IC package comprising an IC, a multi-layer circuit wiring board mounting said IC, and a printed wiring board mounting said multi-layer circuit wiring board, wherein said multi-layer circuit wiring board comprising:
a first film having a first wiring pattern formed on one surface thereof, a second wiring pattern formed on another surface thereof, and a first via-contact layer electrically connecting said first wiring pattern with said second wiring pattern;
a second film provided with a third wiring pattern for mounting an IC on one surface thereof, another surface thereof being superimposed on said one surface of said first film;
a third film provided on one surface thereof with a fourth wiring pattern to be electrically connected with a printed wiring board, another surface thereof being superimposed on the other surface of said first film;
a second via-contact layer for electrically connecting said first wiring pattern with said third wiring pattern; and
a third via-contact layer for electrically connecting said second wiring pattern with said fourth wiring pattern.
25. The IC package according to claim 22, wherein said first film comprises a polyimide resin layer and a first and a second wiring patterns each formed of copper and formed on said polyimide resin layer; said second film comprises a polyimide resin layer and a third wiring pattern formed of copper and formed on said polyimide resin layer; and said third film comprises a polyimide resin layer and a fourth wiring pattern formed of copper and formed on said polyimide resin layer.
26. The IC package according to claim 22, which further comprises a first adhesive layer for bonding said second film to said first film, and a second adhesive layer for bonding said third film to said first film.
27. The IC package according to claim 26, wherein each of said adhesive layers is formed of a thermosetting adhesive layer containing an epoxy curing component.
28. The IC package according to claim 26, wherein the thickness of each of said adhesive layers is 30 μm or less.
29. The IC package according to claim 22, wherein said first via-contact layer, said second via-contact layer and said third via-contact layer are all formed of a blind via-contact layer, and the ratio of the diameter of the bottom of each of these via-contact layer to the diameter of the top opening of each of these via-contact layer is within the range of 0.2 to 1.0.
30. The IC package according to claim 22, wherein said first via-contact layer, said second via-contact layer and said third via-contact layer are all formed of a blind via-contact layer, and the ratio of the diameter of the bottom of each of these via-contact layers to the diameter of the top opening of each of these via-contact layers is within the range of 0.4 to 0.8.
31. The IC package according to claim 22, wherein said IC is electrically connected with said multi-layer circuit wiring board by way of face-down bonding.
32. The IC package according to claim 22, wherein said IC is electrically connected with said multi-layer circuit wiring board by way of wire bonding using a gold or aluminum wire.
33. The IC package according to claim 22, wherein said IC is sealed with a resin.
34. The IC package according to claim 31, wherein said IC is laminated with a metal plate and then sealed.
35. A method of manufacturing a multi-layer circuit wiring board, said method comprising:
forming a first via-contact layer in a first film having a first conductor layer formed on one surface thereof, and a second conductor layer formed on another surface thereof, thereby electrically connecting said first conductor layer with said second conductor layer;
forming a first wiring pattern in said first conductor layer, and forming a second wiring pattern in said second conductor layer;
laminating a second film having a first insulating layer and a third conductor layer formed on said first insulating layer on said one surface of said first film in such a manner that said first insulating layer is in contact with said one surface of said first film;
laminating a third film having a second insulating layer and a fourth conductor layer formed on said second insulating layer on the other surface of said first film in such a manner that said second insulating layer is in contact with said other surface of said first film;
forming a second via-contact layer electrically connecting said third conductor layer with said first wiring pattern, and forming a third via-contact layer electrically connecting said fourth conductor layer with said second wiring pattern;
forming a wiring pattern for mounting an IC on said first conductor layer; and
forming a wiring pattern to be electrically connected with a printed wiring board on said second conductor layer.
36. The method according to claim 35, wherein a roll-to-roll technique is employed for a formation of said first and second wiring patterns, for a formation of said first via-contact layer, for a lamination of said second film onto said first film, for a lamination of said third film onto said first film, for a formation of a wiring pattern for mounting said IC, for a formation of a wiring pattern to be electrically connected with said printed wiring board, for a formation of said second via-contact layer, and for a formation of said third via-contact layer.
37. The method according to claim 35, wherein said first, second and third via-contact layers are respectively formed by a procedure where an ultraviolet laser having a wavelength of third harmonics or more is employed to form a via-hole, and scattered metal particles deposited at an edge of opening of said via-hole are removed by making use of at least one method selected from a physical polishing using said ultraviolet laser, a physical polishing using abrasive grains, and a chemical polishing by way of acid treatment, thereby obtaining said via-hole having an aspect ratio of 1.5 or less.
38. The method according to claim 35, wherein said first, second and third via-contact layers are respectively formed by a procedure where an ultraviolet laser having a wavelength of third harmonics or more is employed to form a via-hole, and scattered metal particles deposited at an edge of opening of said via-hole are removed by making use of a physical polishing using said ultraviolet laser, wherein at least one method selected from a physical polishing using abrasive grains, and a chemical polishing using acid treatment is employed before or after the first-mentioned physical polishing to polish said first, second, third and fourth conductor layers until the aspect ratio of said via-hole becomes 1.5 or less.
39. The method according to claim 35, wherein said first, second and third via-contact layers are respectively formed by a procedure wherein an ultraviolet laser having a wavelength of third harmonics or more is employed to form a via-hole, residues generated in the formation of said via-hole are removed by making use of a desmear treatment, the holes to be used for forming said via-contact layer is treated to provide the holes with conductivity, and said holes are subjected to an electrolytic plating to form said via-contact layer.
40. The method according to claim 35, wherein said first, second and third via-contact layers are respectively formed by a procedure wherein an ultraviolet laser having a wavelength of third harmonics or more is employed to form a blind via-hole, and residues generated in the formation of said via-hole are removed by making use of a desmear treatment using permanganate.
41. The method according to claim 40, wherein said desmear treatment is followed by a treatment to provide said via-hole with conductivity by means of a direct plating system using at least one material selected from the group consisting of a tin-palladium colloid-based catalyst, a conductive polymer and carbon graphite.
42. The method according to claim 40, wherein said desmear treatment is followed by an electroless copper plating to provide said via-hole with conductivity.
43. The method according to claim 35, wherein said first, second and third via-contact layers are respectively formed by a procedure wherein an ultraviolet laser having a wavelength of third harmonics or more is employed to form a blind via-contact layer-forming hole, residues generated in the formation of said blind via-contact layer-forming hole are removed by making use of a desmear treatment using permanganate, said via-hole is treated using a tin-palladium-based catalyst to provide said via-hole with conductivity or said via-hole is subjected to electroless plating to provide said via-hole with conductivity, and said via-hole is subjected to electrolytic plating using two or more stages of electric density to thereby fill the interior of said blind via-contact layer-forming hole with a metal.
44. The method according to claim 35, wherein the formation of a wiring pattern in said first conductor layer, the formation of a wiring pattern in said second conductor layer, the formation of a wiring pattern in said third conductor layer and the formation of a wiring pattern in said fourth conductor layer are formed by a procedure wherein said first, second, third and fourth conductor layers are respectively chemically polished to confine the thickness thereof to fall within the range of 3 to 12 μm and to confine non-uniformity in thickness of each of these conductor layers to fall within 20% or less of the thicknesses of said first, second, third and fourth conductor layers, and redundant portions of said first, second, third and fourth conductor layers are selectively removed by means of etching treatment using a resist to thereby form predetermined wiring patterns in said first, second, third and fourth conductor layers.
45. The method according to claim 35, wherein the formation of a wiring pattern in said first conductor layer, the formation of a wiring pattern in said second conductor layer, the formation of a wiring pattern in said third conductor layer and the formation of a wiring pattern in said fourth conductor layer are formed by a procedure wherein said first, second, third and fourth conductor layers are respectively chemically polished to confine the thickness thereof to fall within the range of 0.5 to 3 μm and to confine non-uniformity in thickness of each of these conductor layers to fall within 20% or less of the thicknesses of said first, second, third and fourth conductor layers, and said first, second, third and fourth conductor layers are respectively selectively subjected to plating using a resist to form a predetermined pattern, which is followed by chemical polishing of said first, second, third and fourth conductor layers to thereby remove portions thereof other than the plated portions thereof, thereby forming predetermined wiring patterns in said first, second, third and fourth conductor layers.
46. The method according to claim 45, wherein said plating is performed by a process wherein said conductor layers are subjected to acid washing treatment after the formation of said resist, and then subjected to Cu-plating at a current density of 1 to 4 A/dm2.
47. A method of manufacturing a multi-layer circuit wiring board, said method comprising:
forming a first via-contact layer in a first film having a first conductor layer formed on one surface thereof, and a second conductor layer formed on another surface thereof, thereby electrically connecting said first conductor layer with said second conductor layer; forming a first wiring pattern in said first conductor layer, and forming a second wiring pattern in said second conductor layer;
laminating a second film having a first insulating layer and a third conductor layer formed on said first insulating layer on said one surface of said first film in such a manner that said first insulating layer is brought into contact with said one surface of said first film;
laminating a third film having a second insulating layer and a fourth conductor layer formed on said second insulating layer on the other surface of said first film in such a manner that said second insulating layer is brought into contact with the other surface of said first film;
forming a second via-contact layer electrically connecting said third conductor layer with said first wiring pattern, and forming a third via-contact layer electrically connecting said fourth conductor layer with said second wiring pattern;
forming a predetermined wiring pattern respectively in said third conductor layer and in said fourth conductor layer;
laminating a fourth film over said wiring pattern of said third conductor layer, said fourth film having a third insulating layer and a fifth conductor layer formed on said third insulating layer;
laminating a fifth film over said wiring pattern of said fourth conductor layer, said fifth film having a fourth insulating layer and a sixth conductor layer formed on said fourth insulating layer;
forming a fourth via-contact layer electrically connecting the wiring pattern of said third conductor layer with said fifth conductor layer, and forming a fifth via-contact layer electrically connecting the wiring pattern of said fourth conductor layer with said sixth conductor layer;
forming a wiring pattern for mounting an IC on said fifth conductor layer; and
forming a wiring pattern to be electrically connected with a printed wiring board on said sixth conductor layer.
48. The method according to claim 47, wherein the formation of a wiring pattern in said first conductor layer, in said second conductor layer, in said third conductor layer, in said fourth conductor layer, in said fifth conductor layer and in said sixth conductor layer is performed by a procedure wherein with respect to a fine pattern-forming region of layer where a wire-working pitch of fine wiring pattern is finer than 30 μm, these conductor layers are respectively chemically polished to confine the thickness thereof to fall within the range of 0.5 to 3 μm and to confine non-uniformity in thickness of said fine pattern-forming region of layer to fall within 20% or less, and said fine pattern-forming region of layer is selectively subjected to plating using a resist to form a predetermined pattern, which is followed by chemical polishing thereof to thereby remove portions other than the plated portions thereof, thereby forming predetermined wiring patterns in said fine pattern-forming region of layer; and with respect to a residual region of layer other than said fine pattern-forming region of layer, these conductor layers are respectively chemically polished to confine the thickness thereof to fall within the range of 3 to 12 μm and to confine non-uniformity in thickness of said residual region of layer to fall within 20% or less, and said residual region of layer is selectively subjected to etching using a resist to remove redundant portions thereof, thereby forming predetermined wiring patterns in said residual region of layer.
49. A method of manufacturing a multi-layer circuit wiring board, said method comprising:
(a) forming a first via-contact layer in a first film having a first conductor layer formed on one surface thereof, and a second conductor layer formed on another surface thereof, thereby electrically connecting said first conductor layer with said second conductor layer;
(b) forming a first wiring pattern in said first conductor layer, and forming a second wiring pattern in said second conductor layer;
(c) laminating a second film having a first insulating layer and a third conductor layer formed on said first insulating layer on said one surface of said first film in such a manner that said first insulating layer is brought into contact with said one surface of said first film;
(d) laminating a third film having a second insulating layer and a fourth conductor layer formed on said second insulating layer on the other surface of said first film in such a manner that said second insulating layer is brought into contact with the other surface of said first film;
(e) forming a second via-contact layer electrically connecting said third conductor layer with said first wiring pattern, and forming a third via-contact layer electrically connecting said fourth conductor layer with said second wiring pattern;
(f) forming a predetermined wiring pattern respectively in said third conductor layer and in said fourth conductor layer;
(g) laminating a fourth film over said wiring pattern of said third conductor layer, said fourth film having a third insulating layer and a fifth conductor layer formed on said third insulating layer;
(h) laminating a fifth film over said wiring pattern of said second conductor layer, said fifth film having a fourth insulating layer and a sixth conductor layer formed on said fourth insulating layer;
(i) forming a fourth via-contact layer electrically connecting the wiring pattern of said third conductor layer with said fifth conductor layer, and forming a fifth via-contact layer electrically connecting the wiring pattern of said fourth conductor layer with said sixth conductor layer;
repeating said steps (g) through (i) to thereby form a required number of layers to form a laminate;
forming a wiring pattern for mounting an IC on an outermost conductor layer which is disposed on one surface of said laminate; and
forming a wiring pattern to be electrically connected with a printed wiring board on another outermost conductor layer which is disposed on the other surface of said laminate.
50. The method according to claim 49, wherein the formation of a wiring pattern in each of these conductor layers is performed by a procedure wherein with respect to a fine pattern-forming region of layer where a wire-working pitch of fine wiring pattern is finer than 30 μm, these conductor layers are respectively chemically polished to confine the thickness thereof to fall within the range of 0.5 to 3 μm and to confine non-uniformity in thickness of said fine pattern-forming region of layer to fall within 20% or less, and said fine pattern-forming region of layer is selectively subjected to plating using a resist to form a predetermined pattern, which is followed by chemical polishing thereof to thereby remove portions other than the plated portions thereof, thereby forming predetermined wiring patterns in said fine pattern-forming region of layer; and with respect to a residual region of layer other than said fine pattern-forming region of layer, these conductor layers are respectively chemically polished to confine the thickness thereof to fall within the range of 3 to 12 μm and to confine non-uniformity in thickness of said residual region of layer to fall within 20% or less, and said residual region of layer is selectively subjected to etching using a resist to remove redundant portions thereof, thereby forming predetermined wiring patterns in said residual region of layer.
51. A method of manufacturing a multi-layer circuit wiring board, said method comprising:
forming a first via-contact layer in a first film having a first conductor layer formed on one surface thereof, and a second conductor layer formed on another surface thereof, thereby electrically connecting said first conductor layer with said second conductor layer;
performing a patterning of said first conductor layer to form a first wiring pattern in said first conductor layer;
laminating a second film having a first insulating layer and a third insulating layer on said first wiring pattern in such a manner that said first insulating layer is brought into contact with said first wiring pattern;
forming a second via-contact layer in said second film, thereby electrically connecting said third conductor layer with said first wiring pattern;
performing a patterning of said third conductor layer to form a second wiring pattern in said third conductor layer;
laminating a third film having a second insulating layer and a fourth insulating layer on said second wiring pattern in such a manner that said second insulating layer is brought into contact with said second wiring pattern;
forming a third via-contact layer in said third film, thereby electrically connecting said fourth conductor layer with said second wiring pattern;
performing a patterning of said fourth conductor layer to form a third wiring pattern in said fourth conductor layer; and
performing a patterning of said second conductor layer to form a fourth wiring pattern in said second conductor layer.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This is a Continuation Application of PCT Application No. PCT/JPO2/10172, filed Sep. 30, 2002, which was not published under PCT Article 21(2) in English.

[0002] This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2001-304651, filed Sep. 28, 2001, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0003] 1. Field of the Invention

[0004] The present invention relates to a multi-layer wiring board, to a semiconductor package, and to a method of manufacturing the multi-layer wiring board.

[0005] 2. Description of the Related Art

[0006] In recent years, there has been developed, as a semiconductor device such a semiconductor large scale integrated circuit (LSI), one whose operating speed is increased up to 1 GHz in terms of clock frequency. In such a high-speed semiconductor device, the integration degree of transistors is fairly high, so that the number of input/output terminals may in sometimes exceed over 1,000.

[0007] In order to mount such a multi-terminal semiconductor device on a printed wiring board, there have been developed various kinds of techniques. The techniques which are currently widely put into practical use include an interposer such as BGA (Ball Grid Array) and CSP (Chip Size Package).

[0008]FIG. 1 illustrates one example of an IC package wherein a semiconductor device is mounted on an interposer of BGA structure and packaged in a printed wiring board.

[0009] Referring to FIG. 1, a multi-layer circuit wiring board 53 comprises a copper-clad substrate (glass epoxy substrate) 530 made from glass cloth into which epoxy resin is impregnated, a first layer 531 formed of a laminate comprising insulating layers and conductive wiring layers, which are alternately superimposed, and a second layer 532 formed of a laminate also comprising insulating layers and conductive wiring layers, which are alternately superimposed. The first layer 531 is placed on one of the main surfaces of the glass epoxy substrate 530, and the second layer 532 is placed on the other main surface of the glass epoxy substrate 530.

[0010] The first layer 531 is provided on the top surface thereof with surface-treated gold pads 536, and with gold bumps 537 for bringing into contact with the electrodes (not shown) of a semiconductor device 54. Further, the second layer 532 is provided on the bottom surface thereof with surface-treated gold pads 538 for bringing into contact, through a solder ball 52, with a conductive wiring layer 511 of a printed wiring board 51. A pad 536 is electrically connected with a pad 538 by way of via-contact conductor layers 533 and 535.

[0011] A method of forming a multi-layer circuit wiring board by successively piling up insulating resin layers and conductive wiring layers one upon another on a glass epoxy substrate as described above is called a build-up technique. Details of this technique are described for example in Japanese Laid-open Patent Publication (Kokai) No. 4-148590 (1992).

[0012] In this technique, it is no longer required to employ a core material such as glass cloth which has been conventionally employed as an insulating layer of a multi-layer circuit wiring board and laminated together with a wiring layer. Namely, the insulating layer of the multi-layer circuit wiring board is formed in this technique by a method wherein a photosensitive resin composition is coated on a surface of glass epoxy substrate and then cured to form the insulating layer. On the other hand, the wiring pattern of the multi-layer circuit wiring board according to the aforementioned build-up technique is formed by making use of a plating method in contrast to that of the conventional multi-layer circuit wiring board. Therefore, it is possible, according to the aforementioned build-up technique, to form a finer wiring pattern in the multi-layer circuit wiring board as compared with the wiring pattern of the conventional multi-layer circuit wiring board. For example, it is possible to form a wiring pattern 50 μm in line width and about 50 μm in width of space between lines.

[0013] The via-contact layer 535 for bringing into contact with both of upper and lower conductive wiring layers can be formed by a method wherein a fine hole is formed in the layer by means of photolithography by taking advantage of the photosensitivity of a resin composition, and then the hole is filled with a conductive material by means of plating. In the case of the conventional multi-layer circuit wiring board where all of the layers are collectively laminated, the diameter of the through-hole cannot be made smaller than 300 μm. Whereas, according to the aforementioned build-up technique, the diameter of the through-hole can be made as small as 100 μm or so, thereby making it possible to enhance the density of the through-holes.

[0014] However, the structure of the conventional multi-layer circuit wiring board is accompanied with the following problems in enhancing the density of wirings, in increasing the transmitting speed of signals, and in promoting the mass production thereof.

[0015] First, the conductive wiring layer according to the build-up technique is formed at first by way of electroless plating on an insulating resin layer, which is followed by electrolytic plating. Generally, the adhesive strength of the electroless-plated layer to the insulating resin layer is relatively low. Therefore, the surface of the insulating resin layer is roughened prior to the electroless plating to have a surface roughness 5 μm to 10 μm in maximum height, thereby promoting the anchoring effect and hence enhancing the adhesive strength of the electroless-plated layer. Due to this surface roughness however, non-uniformity in lateral direction is caused to generate on the occasion of forming a wiring pattern by an etching method, etc., thereby making it impossible to obtain a wiring pattern excellent in linearity. In a wiring pattern where the line width thereof is 50 μm or less, this non-uniformity cannot be disregarded. Namely, noise due to reflection may become enlarged on the occasion of passing signals at a high speed, thus raising a problem. Therefore, according to the conventional build-up technique, it is difficult to manufacture a multi-layer circuit wiring board which is high in density of wiring pattern and capable of transmitting signals at a high speed, or more specifically, a multi-layer circuit wiring board having a fine wiring pattern 50 μm or less in line-and-space, and hence to manufacture an IC package having such features.

[0016] Secondly, since the glass epoxy substrate is poor in flexibility, it is impossible to adopt a roll-to-roll technique which is designed to continuously manufacture a multi-layer circuit wiring board by making use of a long strip of base material, and hence it is difficult to apply a mass-production method to the manufacture of the conventional multi-layer circuit wiring board.

[0017] Thirdly, as described above, as a semiconductor device is designed so as to further increase the processing speed thereof, the number of input/output terminals of the semiconductor device is also required to be proportionally increased. Under such circumstances, the conventional wire bonding method is no-longer capable of performing the electrical connection between such an increased number of terminals and the interposers. On the other hand, the wirings extending from the connecting terminals which are provided within the interposer can be hardly dealt with by a single layer and hence may be required to be separated so as to arrange them in at least two layers. Further, in order to cope with the speedup of signals, it may be required to adopt a microstrip structure of wirings, a strip structure of wirings, or the multiplication of wirings such as a coplanar structure.

[0018] However, as far as the manufacturer of the interposer is concerned, any increase in number of wiring layers leads to a substantial reduction of yield. Therefore, it is very important to consider how to effectively arrange the wirings, and how to design the wirings in order to minimize the number of wiring layers. There are increasing demands for the development of a multi-layer circuit wiring board and an IC package where the wirings thereof are constituted by a wiring pattern of finer line-and-space in order to realize an effective arrangement of wirings.

[0019] Fourthly, as described above, in the multi-layer circuit wiring board to be according to the build-up technique, a substrate (glass epoxy substrate) manufactured by means of the conventional method is employed as a core layer of the wiring board. In order to electrically connect the upper side of the substrate with the underside side thereof, a through-hole is formed by making use of a drill, and plating is applied to the inner wall of the through-hole to thereby obtain a plated through-hole. In this case, since the through-hole is mechanically formed by making use of a drill, the miniaturization in size of the through-hole would be considerably restricted. Likewise, for the same reason, the minimization in pitch of the through-holes would be considerably restricted. For example, at present, a typical value of the diameter of the through-hole is 300 μm, and a typical value of the pitch of the through-holes is 800 μm.

[0020] As described above, since the miniaturization in size of the through-hole as well as the minimization in pitch of the through-holes are restricted, there is a problem in the prior art that the density of BGA ball pin cannot be enhanced. As a result, any increase in the number of input/output terminals in a semiconductor device would inevitably lead to an increase in size of the body of the interposer, resulting in the elongation in length of the wirings and hence in the delay of signals.

[0021] Additionally, since the pitch of the through-holes in the core layer is relatively large, a high density fine wiring is formed only on one of the build-up layers which is designed to mount semiconductor devices. Whereas, the other build-up layer which is disposed on the opposite surface of the core layer and designed to mount balls is frequently employed solely for preventing the warpage of the wiring board. As a result, the number of layers is caused to increase more than needed, which leads to an increase in manufacturing cost of the wiring board.

[0022] Further, since the glass epoxy substrate to be employed as the core layer is generally made of a glass cloth, the thickness of the core layer becomes relatively large, thus substantially increasing the total thickness of the interposer. If the total thickness of the interposer is increased in this manner, it becomes difficult to align the characteristic impedance of the wirings formed in board-thickness direction, i.e. the through-hole and via-contact layer, thus making it disadvantageous in enhancing the operating speed of semiconductor device.

[0023] The present invention has been accomplished in view of overcoming the aforementioned problems, and therefore, the objects of the present invention are to provide a method of manufacturing a multi-layer circuit wiring board, which is capable of forming a wiring pattern having a fine line-and-space, and of adopting a roll-to-roll technique where a long strip of base material is employed to continuously manufacture a multi-layer circuit wiring board.

BRIEF SUMMARY OF THE INVENTION

[0024] According to a first aspect of the present invention, there is provided a multi-layer circuit wiring board comprising a laminate of films, each film having a wiring pattern formed on at least one surface thereof, wherein the wiring pattern formed on each film is electrically connected with the wiring pattern formed on another film which is disposed neighboring thereto through a via-contact layer formed in any one of the neighboring films.

[0025] According to a second aspect of the present invention, there is provided a multi-layer circuit wiring board comprising: a first film having a first wiring pattern formed on one surface thereof, a second wiring pattern formed on another surface thereof, and a first via-contact layer electrically connecting the first wiring pattern with the second wiring pattern; a second film provided with a third wiring pattern for mounting an IC on one surface thereof, another surface thereof being superimposed on the one surface of the first film; a third film provided on one surface thereof with a fourth wiring pattern to be electrically connected with a printed wiring board, another surface thereof being superimposed on the other surface of the first film; a second via-contact layer for electrically connecting the first wiring pattern with the third wiring pattern; and a third via-contact layer for electrically connecting the second wiring pattern with the fourth wiring pattern.

[0026] According to a third aspect of the present invention, there is provided a multi-layer circuit wiring board comprising: a first film having a first wiring pattern formed on one surface thereof; and

[0027] a second film provided with a third wiring pattern for mounting an IC on one surface thereof, another surface thereof being superimposed on the one surface of the first film; wherein the second film is provided with a first via-contact layer for electrically connecting the first wiring pattern with the third wiring pattern.

[0028] According to a fourth aspect of the present invention, there is provided a multi-layer circuit wiring board comprising: a first film having a first wiring pattern formed on one surface thereof, a second wiring pattern formed on another surface thereof, and a first via-contact layer electrically connecting the first wiring pattern with the second wiring pattern; a second film provided with a third wiring pattern on one surface thereof, another surface thereof being superimposed on the one surface of the first film;

[0029] a third film provided with a fourth wiring pattern on one surface thereof, another surface thereof being superimposed on the other surface of the first film; a second via-contact layer for electrically connecting the first wiring pattern with the third wiring pattern; a third via-contact layer for electrically connecting the second wiring pattern with the fourth wiring pattern; a fourth film provided with a fifth wiring pattern for mounting an IC on one surface thereof, another surface thereof being superimposed on the second film; a fifth film provided on one surface thereof with a sixth wiring pattern to be electrically connected with a printed wiring board, another surface thereof being superimposed on the third film; a fourth via-contact layer for electrically connecting the third wiring pattern with the fifth wiring pattern; and a fifth via-contact layer for electrically connecting the fourth wiring pattern with the sixth wiring pattern.

[0030] According to a fifth aspect of the present invention, there is provided a multi-layer circuit wiring board comprising a laminate of resin films, each resin film having a wiring pattern formed on at least one surface thereof, wherein the wiring pattern formed on one resin film is electrically connected with a wiring pattern formed on another resin film which is disposed next to the one resin film, through a via-contact layer provided on the one resin film or on the another resin film, a wiring pattern formed on an outermost resin film on one side of the laminate is a wiring pattern for mounting an IC, and a wiring pattern formed on another outermost resin film on another side of the laminate is a wiring pattern to be electrically-connected with a printed wiring board.

[0031] According to a sixth aspect of the present invention, there is provided an IC package comprising an IC, and a multi-layer circuit wiring board mounting the IC, wherein the multi-layer circuit wiring board comprising: a first film having a first wiring pattern formed on one surface thereof, a second wiring pattern formed on another surface thereof, and a first via-contact layer electrically connecting the first wiring pattern with the second wiring pattern; a second film provided with a third wiring pattern for mounting an IC on one surface thereof, another surface thereof being superimposed on the one surface of the first film; a third film provided on one surface thereof with a fourth wiring pattern to be electrically connected with a printed wiring board, another surface thereof being superimposed on the other surface of the first film; a second via-contact layer for electrically connecting the first wiring pattern with the third wiring pattern; and a third via-contact layer for electrically connecting the second wiring pattern with the fourth wiring pattern.

[0032] According to a seventh aspect of the present invention, there is provided an IC package comprising an IC, a multi-layer circuit wiring board mounting the IC, and a printed wiring board mounting the multi-layer circuit wiring board, wherein the multi-layer circuit wiring board comprising: a first film having a first wiring pattern formed on one surface thereof, a second wiring pattern formed on another surface thereof, and a first via-contact layer electrically connecting the first wiring pattern with the second wiring pattern; a second film provided with a third wiring pattern for mounting an IC on one surface thereof, another surface thereof being superimposed on the one surface of the first film; a third film provided on one surface thereof with a fourth wiring pattern to be electrically connected with a printed wiring board, another surface thereof being superimposed on the other surface of the first film; a second via-contact layer for electrically connecting the first wiring pattern with the third wiring pattern; and

[0033] a third via-contact layer for electrically connecting the second wiring pattern with the fourth wiring pattern.

[0034] According to an eighth aspect of the present invention, there is provided a method of manufacturing a multi-layer circuit wiring board, the method comprising: forming a first via-contact layer in a first film having a first conductor layer formed on one surface thereof, and a second conductor layer formed on another surface thereof, thereby electrically connecting the first conductor layer with the second conductor layer; forming a first wiring pattern in the first conductor layer, and forming a second wiring pattern in the second conductor layer; laminating a second film having a first insulating layer and a third conductor layer formed on the first insulating layer on the one surface of the first film in such a manner that the first insulating layer is in contact with the one surface of the first film; laminating a third film having a second insulating layer and a fourth conductor layer formed on the second insulating layer on the other surface of the first film in such a manner that the second insulating layer is in contact with the other surface of the first film; forming a second via-contact layer electrically connecting the third conductor layer with the first wiring pattern, and forming a third via-contact layer electrically connecting the fourth conductor layer with the second wiring pattern; forming a wiring pattern for mounting an IC on the first conductor layer; and forming a wiring pattern to be electrically connected with a printed wiring board on the second conductor layer.

[0035] According to a ninth aspect of the present invention, there is provided a method of manufacturing a multi-layer circuit wiring board, the method comprising: forming a first via-contact layer in a first film having a first conductor layer formed on one surface thereof, and a second conductor layer formed on the other surface thereof, thereby electrically connecting the first conductor layer with the second conductor layer; forming a first wiring pattern in the first conductor layer; forming a second wiring pattern in the second conductor layer; laminating a second film having a first insulating layer and a third conductor layer formed on the first insulating layer on the one surface of the first film in such a manner that the first insulating layer is brought into contact with the one surface of the first film; laminating a third film having a second insulating layer and a fourth conductor layer formed on the second insulating layer on the other surface of the first film in such a manner that the second insulating layer is brought into contact with the other surface of the first film; forming a second via-contact layer electrically connecting the third conductor layer with the first wiring pattern; forming a third via-contact layer electrically connecting the fourth conductor layer with the second wiring pattern; forming a predetermined wiring pattern respectively in the third conductor layer and in the fourth conductor layer; laminating a fourth film over the wiring pattern of the third conductor layer, the fourth film having a third insulating layer and a fifth conductor layer formed on the third insulating layer; laminating a fifth film over the wiring pattern of the second conductor layer, the fifth film having a fourth insulating layer and a sixth conductor layer formed on the fourth insulating layer; forming a fourth via-contact layer electrically connecting the wiring pattern of the third conductor layer with the fifth conductor layer; forming a fifth via-contact layer electrically connecting the wiring pattern of the fourth conductor layer with the sixth conductor layer; forming a wiring pattern for mounting an IC on the third conductor layer; and forming a wiring pattern to be electrically connected with a printed wiring board on the fourth conductor layer.

[0036] According to a tenth aspect of the present invention, there is provided a method of manufacturing a multi-layer circuit wiring board, the method comprising: (a) forming a first via-contact layer in a first film having a first conductor layer formed on one surface thereof, and a second conductor layer formed on the other surface thereof, thereby electrically connecting the first conductor layer with the second conductor layer; (b) forming a first wiring pattern in the first conductor layer, and forming a second wiring pattern in the second conductor layer; (c) laminating a second film having a first insulating layer and a third conductor layer formed on the first insulating layer on the one surface of the first film in such a manner that the first insulating layer is brought into contact with the one surface of the first film;

[0037] (d) laminating a third film having a second insulating layer and a fourth conductor layer formed on the second insulating layer on the other surface of the first film in such a manner that the second insulating layer is brought into contact with the other surface of the first film; (e) forming a second via-contact layer electrically connecting the third conductor layer with the first wiring pattern, and forming a third via-contact layer electrically connecting the fourth conductor layer with the second wiring pattern; (f) forming a predetermined wiring pattern respectively in the third conductor layer and in the fourth conductor layer; (g) laminating a fourth film over the wiring pattern of the third conductor layer, the fourth film having a third insulating layer and a fifth conductor layer formed on the third insulating layer; (h) laminating a fifth film over the wiring pattern of the second conductor layer, the fifth film having a fourth insulating layer and a sixth conductor layer formed on the fourth insulating layer; (i) forming a fourth via-contact layer electrically connecting the wiring pattern of the third conductor layer with the fifth conductor layer, and forming a fifth via-contact layer electrically connecting the wiring pattern of the fourth conductor layer with the sixth conductor layer; repeating the steps (g) through (i) to thereby form a required number of layers to form a laminate; forming a wiring pattern for mounting an IC on an outermost conductor layer which is disposed on one surface of the laminate; and forming a wiring pattern to be electrically connected with a printed wiring board on another outermost conductor layer which is disposed on the other surface of the laminate.

[0038] According to an eleventh aspect of the present invention, there is provided a method of manufacturing a multi-layer circuit wiring board, the method comprising: forming a first via-contact layer in a first film having a first conductor layer formed on one surface thereof, and a second conductor layer formed on the other surface thereof, thereby electrically connecting the first conductor layer with the second conductor layer; performing a patterning of the first conductor layer to form a first wiring pattern in the first conductor layer; laminating a second film having a first insulating layer and a third insulating layer on the first wiring pattern in such a manner that the first insulating layer is brought into contact with the first wiring pattern; forming a second via-contact layer in the second film, thereby electrically connecting the third conductor layer with the first wiring pattern; performing a patterning of the third conductor layer to form a second wiring pattern in the third conductor layer; laminating a third film having a second insulating layer and a fourth insulating layer on the second wiring pattern in such a manner that the second insulating layer is brought into contact with the second wiring pattern; forming a third via-contact layer in the third film, thereby electrically connecting the fourth conductor layer with the second wiring pattern; performing a patterning of the fourth conductor layer to form a third wiring pattern in the fourth conductor layer; and performing a patterning of the second conductor layer to form a fourth wiring pattern in the second conductor layer.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0039]FIG. 1 is a cross-sectional view illustrating one example of an IC package wherein a semiconductor element is mounted on an interposer of BGA structure and mounted on a printed wiring board;

[0040]FIG. 2 is a cross-sectional view illustrating an IC package 10 of so-called first level of packaging wherein a multi-layer circuit wiring board 11 and an IC 12 are mounted thereon;

[0041]FIG. 3 is a cross-sectional view illustrating another example of the structure wherein an IC 12 is mounted on a multi-layer circuit wiring board;

[0042]FIG. 4 is a cross-sectional view illustrating a further example of the structure wherein an IC 12 is mounted on a multi-layer circuit wiring board;

[0043]FIG. 5 is a cross-sectional view illustrating a further example of the structure wherein an IC 12 is mounted on a multi-layer circuit wiring board;

[0044]FIG. 6 is a cross-sectional view illustrating a further example of the structure wherein an IC 12 is mounted on a multi-layer circuit wiring board;

[0045]FIG. 7 is a diagram schematically illustrating the roll-to-roll technique;

[0046]FIGS. 8A through 8I represent respectively a cross-sectional view illustrating a method of manufacturing a multi-layer circuit wiring board according to Example 1;

[0047]FIGS. 9A through 9E represent respectively a cross-sectional view illustrating a method of manufacturing a multi-layer circuit wiring board according to Example 1;

[0048]FIG. 10 is a cross-sectional view illustrating a 6-ply multi-layer circuit wiring board;

[0049]FIG. 11 is a cross-sectional view illustrating a 4-ply multi-layer circuit wiring board having a fixing frame;

[0050]FIG. 12 is a cross-sectional view illustrating a 6-ply multi-layer circuit wiring board having a fixing frame;

[0051]FIGS. 13A through 13G represent respectively a cross-sectional view illustrating a method of manufacturing a multi-layer circuit wiring board according to Example 3; and

[0052]FIGS. 14A through 14L represent respectively a cross-sectional view illustrating a method of manufacturing a multi-layer circuit wiring board according to Example 4.

DETAILED DESCRIPTION OF THE INVENTION

[0053] Next, the present invention will be explained with reference to drawings. Incidentally, in the following explanation, the constituent elements having almost the same function and the same construction will be identified by the same symbols, and the duplicate explanation thereof will be made only when it is required to do so.

[0054]FIG. 2 shows an IC package 10 of a so-called first level of packaging, which is provided with solder balls 9, a multi-layer circuit wiring board 11 and an IC 12. In FIG. 2, the multi-layer circuit wiring board 11 comprises insulating layers 131 a, 131 b, 131 c, adhesive layers 15 b, 15 c, wiring patterns 17 a, 17 b, 21, 23, and via-contact layers 19 a, 19 b. In this multi-layer circuit wiring board 11, the IC 12 is mounted on the wiring pattern 21 and will be packaged through the wiring pattern 23 within a printed wiring board (not shown). The IC package 10 and the printed wiring board (not shown) are designed to constitute an IC package of so-called second level of packaging.

[0055] The insulating layers 131 a, 131 b, 131 c are respectively formed of a film made of polyimide resin, polyolefin resin, liquid crystal polymer, etc. Among them, polyimide resin is especially preferable in view of its excellent heat-resistance. Polyimide resin is a heat-resistant polymer and can be manufactured through a condensation reaction between a diamine compound and a tetra-carboxylic acid compound. Especially when an aromatic compound is employed as any one of these compounds, it is possible to manufacture a highly heat-resistant polymer having a glass transition temperature of 350° C. or more. This highly heat-resistant polymer can be extensively employed as an insulating material for an electronic material and in various forms, e.g. as a film, or as a coating material. However, it is also possible to employ a film of other kinds of materials as long as the film is excellent in heat-resistance, in flexibility and in smoothness, and low in water absorption.

[0056] The thickness of these insulating layers may preferably be confined within the range of 12.5 to 80 μm. Because, if the thickness of these insulating layers is less than 12.5 μm, it may become difficult to ensure electric insulation. On the other hand, if the thickness of these insulating layers exceeds over 80 μm, it will invite not only a substantial increase in total thickness of the board but also necessity to increase the wiring line width due to the increased thickness of the insulating layers as the characteristic impedance thereof is taken into account, thereby making it difficult to realize a wiring of high density.

[0057] Incidentally, for the purpose of simplifying the explanation of the present invention, these insulating layers 131 a, 131 b, 131 c are all formed of a polyimide layer. The surface roughness of these polyimide layers 131 a, 131 b, 131 c, as measured based on ten point height of irregularities (Rz) as defined by JIS B 0601, may preferably be confined within Rz=0.01 to 5.0. Because, if the ten point height of irregularities (Rz) of these insulating layers is less than 0.01, it would become impossible to secure a sufficient adhesion strength between these insulating layers, thereby deteriorating the layer-to-layer reliability. On the other hand, if the Rz of these insulating layers is larger than 5.0, it may become difficult to form a sufficiently fine pattern.

[0058] In particular, in the case where the width of wiring formed on the top surface of a polyimide layer is 50 μm or less, if the Rz becomes 5.0 or more, the non-uniformity of wiring width can no longer be disregarded, so that the noise due to reflection can not be disregarded when signals are passed through the wiring at a high speed. Therefore, the Rz may preferably be 5.0 or less.

[0059] The wiring patterns 17 a, 17 b, the wiring pattern 21 and the wiring pattern 23 are formed from conductor layers laminated respectively on the polyimide layer 131 a, the polyimide layer 131 b and the polyimide layer 131 c by a process to be described hereinafter. As for the raw material to be employed for constituting these conductor layers, i.e. the raw material of the wiring patterns 17 a, 17 b, 21, 23, it is possible to employ the material constituting the ordinary wiring substrate as it is, and there is no particular limitation with regard to this raw material. Generally, copper foil, for example, can be employed for this purpose. If copper foil is to be employed for forming the conductor layer of wiring, any kind of copper foil can be employed, as long as the copper foil is flat and smooth. For example, electrolytic copper foil, rolled copper foil, etc. can be utilized for this purpose.

[0060] The thickness of the conductor layer may preferably be confined within the range of 3 to 18 μm.

[0061] On the wiring pattern 21 side of the multi-layer circuit wiring board 11 shown in FIG. 2, there is mounted, via bumps 25, the IC 12. On the other hand, on the opposite side of the multi-layer circuit wiring board 11, the wiring pattern 23 disposed thereon is connected, via solder balls 9, with a printed wiring board (the solder balls as well as the printed wiring board are not shown).

[0062] The adhesive layers 15 b, 15 c are disposed to attach the film 131 b to one surface of the film 131 a and to attach the film 131 c to the other surface of the film 131 a. As for the characteristics of these adhesive layers 15 b, 15 c, there is no particular limitation as long as they are excellent in heat-resistance, in flexibility and in smoothness, and low in water absorption. For example, it is possible to employ an epoxy-based adhesive, a rubber-based adhesive, a polyimide-based adhesive, a polyolefin-based adhesive, an acrylic adhesive, etc. Among them, a thermosetting adhesive containing therein at least an epoxy-curing component is more preferable.

[0063] While a thermoplastic adhesive is caused to repeatedly exhibit thermoplasticity at a working temperature of not lower than the melting point thereof, the thermosetting adhesive containing therein at least an epoxy-curing component is capable of enhancing the heat-resistance thereof as it is thermally cured after the lamination thereof, thereby giving a cured product which is excellent in reliability. As for the specific examples of the adhesive containing therein at least an epoxy-curing component, they include, other than an epoxy-based adhesive, an adhesive comprising an acrylic material to which an epoxy-curing component is added, an adhesive comprising a polyimide-based material to which an epoxy-curing component is added, and an adhesive comprising a rubber-based material to which an epoxy-curing component is added. Incidentally, it should not be construed that the adhesive to be employed in the present invention is limited to these adhesives mentioned above. As a matter of course, it may be any other kind of adhesive.

[0064] In this specification, the term “epoxy-curing component” means any curing system contains an epoxy compound and a component which is capable of reacting with and curing the epoxy compound. For example, such curing systems include those capable of generating a curing reaction between an epoxy compound and amines; a curing reaction between an epoxy compound and carboxylic acids; a curing reaction between an epoxy compound and phenols; a curing reaction between an epoxy compound and acid anhydrides; a curing reaction between an epoxy compound and polyamide resin; a curing reaction of an epoxy compound by making use of imidazoles; a curing reaction of an epoxy compound by making use of a latent curing agent; or a system which is capable of generating the curing reaction of an epoxy resin through any combination of these curing reactions. Of course, the examples of the epoxy-curing component are not confined to the compounds exemplified above.

[0065] Incidentally, the thickness of adhesive layers 15 b, 15 c may preferably be 30 μm or less. Because, if the thickness of these adhesive layers exceeds over 30 μm, the aspect ratio of via-hole for effecting a layer-to-layer contact may become undesirably enlarged due to the addition of the polyimide layer employed as an insulating layer, thereby making it difficult to form a via-contact layer excellent in reliability.

[0066] The via-contact layers 19 are provided for realizing an electric connection between wiring patterns which are formed on the films 131 a, 131 b, 131 c. Therefore, the via-contact layers 19 are respectively constituted by a conductor layer which can be formed by way of a plating treatment, etc.

[0067] The bumps 25 are respectively formed of solder, for mounting the IC 12 on the multi-layer circuit wiring board 11.

[0068]FIG. 3 shows another example of a structure where the IC 12 is mounted on the multi-layer circuit wiring board 11. In this structure shown in FIG. 3, the IC 12 is mounted on the multi-layer circuit wiring board 11 in such a manner that the electrodes of the IC 12 are directed upward, and that these electrodes are connected with the wiring pattern 21 through a wire bonding using a wire 200 (for example, a gold wire, an aluminum wire, etc.).

[0069]FIGS. 4 and 5 illustrate an IC package wherein a metal plate is disposed over the IC 12 that has been mounted as shown in FIG. 2. More specifically, in the embodiment shown in FIG. 4, a fixing frame 210 is adhered in advance by means of an adhesive 230 to a portion of the IC-mounting surface where the IC 12 is not located, and then, the opening encircled by the fixing frame 210 is closed by a flat metal plate 220, thereby sealing the IC 12. On the other hand, in the embodiment shown in FIG. 5, a fixing frame is not employed, and instead, a molded metal plate 221 is placed over the IC 12 to thereby sealing the IC 12. As for the material for the fixing frame 210, it is possible to employ a metal, a resin or a hybrid material consisting of an inorganic material and an organic material. These metal plates 220 and 221 are both capable of functioning not only as a member for sealing the IC 12 but also as a radiating plate.

[0070]FIG. 6 illustrates a structure wherein the IC 12 that has been mounted as shown in FIG. 3 is sealed by making use of a sealing resin 240. This resin sealing can be performed by a potting method wherein a resin solution is dropped from the top of the IC 12 to thereby seal the IC 12, or by a transfer molding method wherein a fused resin is poured over the IC 12 by making use of a mold.

[0071] Since the multi-layer circuit wiring board 11 described above is formed of polyimide resin and the like, the multi-layer circuit wiring board 11 is flexible. Accordingly, the multi-layer circuit wiring board 11 can be mass-produced by way of a roll-to-roll system.

[0072] Next, the details of this roll-to-roll system will be explained. As shown in FIG. 7, according to this roll-to-roll system, a tape substrate is unwound from an unwinding section and transferred to a processing section to treat the tape substrate, thereby manufacturing a multi-layer circuit wiring board, which is then taken up at a take-up section. This method is advantageous in that the productivity of the multi-layer circuit wiring board is excellent. Since the unwinding and rewinding of a tape substrate are performed in this method, the tape substrate to be employed herein is required to be flexible to a prescribed degree. Therefore, the conventional tape substrate made of glass epoxy resin cannot be employed in this roll-to-roll system.

[0073] The multi-layer circuit wiring board 11 is constituted by multiple layers of circuit wiring (in FIG. 2, a four-ply circuit wiring consisting of wiring patterns 17 a, 17 b, 21 and 23). Therefore, a semiconductor device having a large number of terminals can be mounted thereon, and the transmission of signals can be performed effectively and at a high speed. Furthermore, the high integration of semiconductor devices can be further advanced. Still further, all of the wiring patterns 17 a, 17 b, 21, 23 can be bonded smoothly and strongly to the polyimide layers 131 a, 131 b, 131 c. Therefore, as compared with the wiring board provided with an irregular surface for realizing a strong bonding, this multi-layer circuit wiring board 11 is capable of exhibiting a higher signal transmitting efficiency.

[0074] Further, according to a manufacturing method to be set forth hereinafter, it is possible to further increase the layers of the multi-layer circuit wiring board 11 (namely, to provide it with four or more layers of circuit wiring). As a result, it is now possible to realize the mounting of a semiconductor device having a large number of terminals, the enhancement of the speed and efficiency in transmitting signals, and a further enhancement in integration of semiconductor devices.

[0075] Manufacturing method of multi-layer circuit wiring board:

[0076] Next, a typical lamination process of the multi-layer circuit wiring board 11 will be explained. Incidentally, specific examples of manufacturing process will be explained in detail with reference to the examples to be discussed hereinafter.

[0077] The lamination process of the multi-layer circuit wiring board 11 can be generally divided into the step of laminating films, the step of forming via-holes, and the step of forming wiring patterns. The details of each of these steps will be explained as follows.

[0078] 1. Step of Lamination:

[0079] In this step of lamination, a film having a conductor layer on one surface thereof is laminated on another film having a wiring pattern on at least one of the surfaces thereof in such a manner that said conductor layer is placed on one outer side of the resultant laminate. Although it is not intended to limit the step of lamination, a lamination apparatus such as an ordinary press or laminator can be utilized in this lamination step. More preferably, in order to prevent the generation of bubbles or voids, the employment of a vacuum press or a vacuum laminator is preferable. Further, because of the reason that productivity can be improved, the laminate may preferably be produced by way of the aforementioned roll-to-roll system.

[0080] The lamination of films can be performed by a method wherein an adhesive layer formed of an adhesive is newly provided, or by a method wherein a film having anadhesive property is employed, thus unnecessitating the provision of an adhesive layer. The film having adhesive property can be represented by a thermoplastic film exhibiting thermoplasticity, such as a thermoplastic polyimide or liquid crystal polymer. When these films are employed, the lamination can be performed by making use of a single body of film without necessitating the provision of an adhesive layer.

[0081] When the provision of an adhesive layer formed of an adhesive is required, the adhesive to be employed in this example may be conceivably formulated as a varnish type or as a film type. Although it is not intended to limit the type of the adhesive, the employment of this film type is more preferable in view of its excellent productivity. When an adhesive of this film type is to be employed, the following lamination method can be employed. Namely, a film provided with a wiring on at least one surface thereof, a film-like adhesive and a film provided with a conductor layer on one surface thereof are concurrently laminated with each other to fabricate a laminated film. Alternatively, it is also possible to employ a method wherein a film-like adhesive is laminated on a film provided with a wiring on at least one surface thereof, and then, a film provided with a conductor layer on one surface thereof is further laminated thereon. Additionally, it is also possible to employ a method wherein an adhesive layer is applied to a film provided with a conductor layer on one surface thereof, and then, a film provided with a wiring on at least one surface thereof is further laminated thereon.

[0082] When an adhesive of the varnish type is to be employed, the following lamination method can be employed. Namely, an adhesive is coated on the surface of a film provided with a wiring on at least one surface thereof to form an adhesive layer, and then, a film provided with a conductor layer on one surface thereof is further laminated to fabricate a laminated film. Alternatively, an adhesive is coated on the surface of a film provided with a conductor layer on one surface thereof to form an adhesive-attached film, which is then laminated with a film provided with a wiring on at least one surface thereof by making use of the adhesive to thereby fabricate a laminated film. Of course, the method of forming such a laminated film is not limited to these methods mentioned above.

[0083] The adhesive layer mentioned above may preferably be constituted by an adhesive containing, as a main component, a resinous adhesive such as an epoxy-based adhesive, a rubber-based adhesive, a polyimide-based adhesive, a polyolefin-based adhesive, an acrylic adhesive, etc. The reason to employ these adhesives is mainly to secure the insulating property of a thin film, though it may depend on a specific composition of the adhesive. When these resin-based adhesives are employed as a main component, it is possible to form a via-hole by means of a low energy density laser to be employed in working these resins.

[0084] When this laminating process is to be performed without any intervention of an adhesive, it can be performed by making use of a thermoplastic film for example. This thermoplastic film is provided with adhesive property. Accordingly, it is possible to obtain a laminated film by laminating a film provided with a conductor layer on one surface onto a film provided with a wiring on at least one surface thereof in such a manner that the conductor layer is placed to constitute an outer surface of the resultant laminate.

[0085] Further, when a thermoplastic film requiring a very high working temperature is to be employed, the lamination may be performed by making use of an adhesive layer having adhesive property for the convenience of working process thereof. Further, in view of enhancing the adhesive strength, an adhesive layer may be attached to the thermoplastic film in obtaining the lamination.

[0086] When the lamination is to be performed using a film having wirings on opposite surfaces thereof, the lamination of another film to each of the surfaces can be performed successively or concurrently. It is possible, in any of such methods, to manufacture the multi-layer circuit wiring board 11. However, the lamination of other films onto both surfaces of the film may preferably be performed concurrently in view of enhancing the productivity.

[0087] In all of the aforementioned methods of laminating a film provided with a conductor layer on one surface thereof onto a film provided with a wiring, it is preferable to roughen the surface of the wiring pattern. As the surface of the wiring pattern is roughened, the area of the adhesion surface can be increased, and due to the anchoring effect derived from the resultant irregular surface, the adhesion strength between adhered layers can be enhanced.

[0088] Followings illustrate one example of this roughening treatment.

[0089] By making use of an apparatus which is capable of transferring a trip of film by way of the roll-to-roll system, a roughening agent (CZ-8101: Mech Co., Ltd.) was sprayed against the surface of patterned conductor to form fine irregularities thereon, which was washed with an acid and then, with water. After being dried, the patterned conductor was subjected to a surface-roughening treatment.

[0090] The conditions for this surface-roughening treatment were: 30° C. in temperature of the roughening agent; and 0.1 MPa in spray pressure. The degree of surface roughness obtained from the surface-roughening treatment under the aforementioned was 1.5 μm at a film-transferring speed of 1.0 m/min. The degree of surface roughness can be adjusted by controlling the transferring speed of the film.

[0091] The surface roughness of the surface of the wiring pattern may preferably be confined within the range of 0.1 to 10.0 as measured based on the ten point height of irregularities (Rz) as defined by JIS B 0601. Because, if the surface roughness based on the ten point height of irregularities (Rz) is smaller than 0.1, the adhesive strength of the film can be hardly improved, while if the surface roughness based on this Rz is larger than 10.0, it may become difficult to maintain the configuration of the wiring pattern.

[0092] 2. Step of Forming Via-Contact Layer:

[0093] 2-1. Formation of Via-Hole:

[0094] The working for forming a via-hole can be performed by making use of a mechanical drill, carbon dioxide gas laser beam, ultraviolet ray laser beam, excimer laser beam, etc. The mechanical drill is capable of forming only a through-hole, whereas the drilling work using a laser beam makes it possible to form not only a through-hole but also non-through-hole (which corresponds to a blind via).

[0095] If the provision of through-holes is permitted in designing a circuit wiring board, the holes can be formed using a mold or a mechanical drill such as an NC drill. When a mold is employed, a plurality of holes can be formed en bloc at predetermined locations of the wiring board. Further, even in a drilling work using the NC drill, a plurality of holes can be formed en bloc by multiplying the shaft of the NC drill. Moreover, even in the employment of the NC drill, it is possible, by suitably manipulating the drilling work (the control of depth-wise working direction), to form not only through-holes but also a non-through-hole. Even in the formation of a blind via, the laser seed may be suitably selected by taking into consideration the productivity, the stability of apparatus (easiness of maintenance) and characteristics of laser beam. Namely, the formation of holes may preferably be performed by taking into consideration the design of the circuit wiring board to be manufactured and the manufacturing cost, etc.

[0096] As for the kinds of laser beam generally utilized as a laser beam in the working machine, there are known carbon dioxide gas laser (wavelength: 9.3-10.6 μm), YAG laser (fundamental wavelength: 1.06 μm), YAG, YLF, YAP and YVO4 lasers of ultraviolet region (wavelength of third harmonic: 355 nm; wavelength of fourth harmonic: 266 nm), and excimer laser (wavelength of XeCl: 308 nm; wavelength of KrF: 248 nm; and wavelength of ArF: 193 nm). Among these laser beams, the carbon dioxide gas laser is the highest in energy density per pulse. According to this carbon dioxide gas laser, the hole-forming treatment can be performed at a high speed. However, this carbon dioxide gas laser is limited in forming a hole of minute diameter, i.e. the minimum diameter which can be realized by the employment of this carbon dioxide gas laser is considered as being at most 50 μm or so.

[0097] Further, when it is desired to directly work a metal layer which has been formed on a polyimide layer, a special pretreatment such as a blacking treatment for enhancing the absorption of optical energy is required to be performed. Because, the zone of absorption wavelength of polyimide differs from that of the metal. Further, the excimer laser is advantageous in that, although the excimer laser is a kind of gas laser, it is capable of working a hole of very small diameter such as 20 μm. However, this excimer laser may not be applicable, on some occasions, to mass production due to the high cost for securing consumable goods such as a high reflection metal oxide mask and maintaining the atmosphere for the laser.

[0098] Since the ultraviolet laser beams that can be derived through a conversion of wavelength of a solid crystal such as YAG, YLF, YAP and YVO4 overlaps with the absorption wavelength of the metal, they are capable of directly working a conductor layer. Further, since these ultraviolet laser beams are capable of contracting the focus of working point down to a very small diameter as compared with that of carbon dioxide gas laser, it is possible to form a hole of very small diameter such as 30 μm or less. Incidentally, the hole-forming speed of these ultraviolet laser beams is questioned at present. However, this problem is now going to be solved through the enhancement of oscillating frequency of laser beam and the multiplication of the working heads.

[0099] Incidentally, since the wavelength of ultraviolet region is higher than the dissociation energy of insulating resin, it is called pholysis working. Since the working to be effected by the carbon dioxide gas laser is thermal working, it may not be possible, on some occasions, to obtain reliable electrical connection between layers through the provision of a via-contact unless the removal of residues (smear), i.e. the residues resulting from the working of resin, is carefully performed. However, when ultraviolet laser is employed, the molecular chains of resin can be dissociated, thereby making it possible to considerably reduce the generation of such residues.

[0100] Although the details of treatment will be made clear in the examples to be discussed hereinafter, ultraviolet laser having a high energy density, for example, is irradiated onto and passed through the conductor layer of a substrate comprising, on its opposite surfaces, two adhesive layers, with a circuit wiring substrate being interposed therebetween (see FIG. 8A). On the other hand, against the polyimide film, preferably, an ultraviolet laser having a low energy density is irradiated to thereby form a blind via which is a non-through-hole (see FIG. 8C). Since the ultraviolet laser of low energy density to be employed for working the polyimide film is incapable of working the conductor layer, a non-through-hole can be formed by taking advantage of a difference in density of energy.

[0101] On this occasion, when the film thickness of the conductor layer is reduced to the range of 3 to 8 μm by way of soft etching, the working of the conductor layer can be facilitated and hence to shorten the working time.

[0102] 2-2. Removal of Dross:

[0103] Generally, the effects of ultraviolet laser beam on a metal in the working of the metal are derived, as a main factor, from the thermal fusion of the metal, so that the metal fused by the ultraviolet laser beam is permitted to disperse as is well known in the art. In this manufacturing method also, the metal constituting the conductor layer is permitted to disperse as a result of the working thereof on the occasion of directly forming holes in the conductor layer. The dispersed particles of the metal are called dross, which is required to be removed by all means in a step after the working of the metal by making use of a laser beam. Because, if the dross builds up along the edge of an opening of a hole to a height of 1 to 3 μm, it may be an obstacle in the chemical treatment in the next step.

[0104] The dross of this kind can be removed by various means, such-as physical polishing, using abrasive grains, chemical polishing by way of acid treatment, or a method of re-irradiating ultraviolet laser beam against the dross to thereby flatten the dross. The features of each of these dross-removing methods are as follows.

[0105] The physical polishing is designed such that by making use of a buff roll or a flat polishing paper, a substrate is entirely polished. Accordingly, when the substrate is formed of a film-like substrate, the generation of the extension of the substrate is feared. Further, it is also feared that useless matter may be left remained inside the via-hole after the polishing of the substrate. Since the dross can be dissolved by an acid in the case of chemical polishing, the problem of residual useless matter will be overcome. Further, according to the chemical polishing, it is possible to remove only the dross by making use of a chemical solution of a suitable concentration. Because, the dross is characterized by its fine rugged surface.

[0106] The employment of a laser beam is featured in that it is not intended to remove the dross but to flatten the dross to thereby prevent the dross from becoming an obstacle in the next step. In the case of physical or chemical polishing, a production line which is designed exclusively for the polishing is required. However, when the treatment of dross is performed immediately after the formation of the hole by making-use of the same laser apparatus, the production line can be shortened. However, since this treatment of dross at the hole is required to be performed one by one, the speed of this treatment may become a problem.

[0107] Although several examples for the removal of dross have been discussed above, the treatments which can be used for the removal of dross are not limited to these examples.

[0108] 2-3. Adjustment of Aspect Ratio:

[0109] In order to make the chemical treatment of via-hole smooth, the via-hole to be formed may preferably be tapered in configuration. More specifically, the ratio of the diameter of the bottom of the via-hole to the diameter of the top opening thereof may preferably be confined within the range of 0.2 to 1.0. Incidentally, when the ratio of the diameter of the bottom to the diameter of the top opening is more than 1.0, the configuration of the via-hole would become a reversed taper-like configuration. On the other hand, when this ratio becomes smaller, the degree of normal taper-like configuration would become increasingly sharp.

[0110] Generally, according to a wet treatment including a treatment using a chemical solution, the circulation of the liquid thereof inside the via-hole would be facilitated as the configuration of the via-hole is normally tapered rather than reversely tapered. However, a smaller ratio of the diameter of the bottom to the diameter of the top opening is indicative of a smaller contact area of the bottom portion to the underlying conductor, thereby leading to the deterioration of reliability of the electrical connection of the via-contact layer. Therefore, the aspect ratio may preferably be confined within the range of 0.4 to 0.8 or so.

[0111] The aspect ratio (the thickness of insulating layer/the diameter of the opening of via-hole) of the conventional via-hole is around 0.5 (for example, 50 μm in thickness of the insulating layer against 100 μm in diameter of the opening of the via-hole). Therefore, problem has been scarcely raised with regard to the circulation of liquid into the via-hole on the occasion of the treatment thereof using a chemical solution. However, when the via-hole is required to be designed and worked so as to make it smaller in diameter, the aspect ratio would become 1 or more, so that the circulation of liquid into the via-hole would be required to be taken into account. Because, if this liquid circulation is deteriorated, voids would be more easily generated inside the via-hole, thereby deteriorating the reliability of the electrical connection of the via-contact layer.

[0112] According to this embodiment, for the purpose of making the circulation of a chemical solution smoother, the film thickness of the conductor layer is minimized before or after the step of forming the via-hole to thereby reduce the aspect ratio. This can be specifically performed by the same treatments as employed on the occasion of removing the dross, i.e. a physical polishing, a chemical polishing and a treatment using laser beam. Since the physical polishing and chemical polishing are respectively a treatment which is applied to the entire surface of film substrate, the film thickness of the top conductor can be uniformly reduced. On the other hand, according to a treatment using laser beam, only the edge portion of the opening of via-hole can be selectively treated, thereby making it possible to individually reduce the aspect ratio of each of the via-holes. By making use of these treatments, the aspect ratio can be reduced to 1.5 or less, more preferably 1.0 or less, thereby assisting the treatment using a chemical solution in the following step.

[0113] In view of minimizing the production line, the reduction of the aspect ratio of the via-hole may preferably be performed concurrent with the removal of the dross.

[0114] 2-4. Removal of Residue (Smear): Desmear

[0115] Residue (smear) which is a resinous residue left unremoved even after the irradiation of laser beam executed following the formation of via-hole by making use of ultraviolet laser beam may be sometimes permitted to exist in the vicinity of the edge of the bottom portion of the via-hole. In such a case, if the residue can be completely removed, the reliability of electrical connection between layers by way of the via-contact layer can be enhanced. The removal of such a residue is called desmear in the art. The quantity of this residue is very little. However, unless this residue is completely removed, the electrical connection between layers by way of the via-contact layer would be obstructed and the reliability of the via-contact layer would be deteriorated. The removal of this residue can be performed by a dry method or by a wet method. In the case of the dry method, the residue is chemically reacted with oxygen radical existing in a plasma atmosphere of a mixed gas comprising fluorine gas and oxygen gas, thereby removing the residue. On the other hand, in the case of the wet method, the residue is dissolved by making use of permanganate of an alkaline solution to thereby remove the residue.

[0116] Since the treating liquid to be employed for the removal of residue is high in processing speed, permanganate to be employed in a wet method is generally employed. In this wet method, the surface of film is roughened by the effect of oxidative decomposition, and due to the resultant anchoring effect of this roughened surface, the adhesiveness thereof to a plated metal can be provided. Furthermore, due to the introduction of oxygen atom and additional introduction of a polar group into the surface of resin, the hydrophilicity of the surface of resin can be further enhanced, thereby making it possible to enhance the wettability of a plating liquid and hence to enhance the adhesive strength of the surface of resin.

[0117] Further, when polyimide is employed as an insulating material, it is possible, through an alkaline treatment, to open the imide ring of polyimide which is exposed to the sidewall of the hole, thereby enabling carboxylic group and amino group to be formed on the surface of the sidewall. As a result, the adhesiveness of the sidewall of the hole to palladium metal for forming a metal film in the following step will be enhanced.

[0118] After the step of desmear, a metal film for example is formed inside the via-hole, the resultant metal film being subsequently employed as an electrode so as to enable a metal plating having a predetermined thickness to be formed on the sidewall and bottom of the hole, thereby accomplishing the via-contact. In order to enable the via-contact layer to be formed by means of electrolytic plating, the aforementioned treatment for providing electric conductivity to the hole is required. If this treatment is insufficient, it may become a large factor for generating voids in the via-contact layer, and therefore, this treatment may be carefully performed.

[0119] 2-5. Treatment for Providing Conductivity:

[0120] The treatment for providing conductivity to the interior of a via-hole can be roughly classified into DPS (Direct Plating System) and electroless copper plating. The DPS is a method wherein, for example, a tin/palladium-based catalyst, a conductive polymer, carbon graphite, etc. are applied to the entire surface inside the via-hole, thereby allowing molecules which are negatively electrified to be adsorbed onto the surface, the molecules being subsequently reduced, by making use of a reducing agent, to metal palladium. On the other hand, the electroless copper plating is a method wherein the hole is treated with an aqueous solution of palladium, thereby enabling palladium to become a catalytic nucleus in an electroless copper plating bath to allow copper to be precipitated.

[0121] When both methods are compared with each other, any of these methods can be considered as a catalyst-substitution type plating technique. As far as the steps and treating time are concerned however, the DPS is smaller in number of steps and shorter in treating time as compared with the electroless copper plating.

[0122] Further, with respect to the easiness of conductivity examination, the examination in the case of the electroless copper plating is performed after finishing the copper plating conducted following the formation of the metal film, thereby making it possible to confirm the conductivity-providing treatment. In the case of the DPS, since the catalyst is employed as a nucleus and a metal film is formed during the electrolytic copper plating, the examination is performed by measuring the surface resistance after the DPS treatment.

[0123] 2-6. Electrolytic Plating:

[0124] The electrolytic plating is performed using a film substrate as a cathode after the conductivity-providing treatment of the interior of the via-hole. Usually, in view of cost and productivity, electrolytic copper plating is selected. This electrolytic copper plating is required to be performed by all means. Unless this electrolytic copper plating is performed, the via-contact cannot be created in the case of the DPS, while in the case of electroless copper plating, since the precipitation speed of plating is 1-3 μm/hour, it would be impossible to secure satisfactory mass production by the employment, as it is, of the electroless copper plating. In the case of the electrolytic plating, a film substrate is employed as a cathode and the current density in the electrolytic bath containing copper sulfate as a main component is controlled to 1-4 A/dm2 or so and voltage is continued to apply thereto for several tens minutes, thus allowing electrolytic copper plating to grow.

[0125] Incidentally, depending on the magnitude of current density in the electrolytic copper plating, the following difference would be created. Namely, although it may depend on the configuration of the via-hole (i.e. the diameter of the opening and aspect ratio), when the electrolytic plating is performed at a high current density (for example, 4 A/dm2), it may be possible to realize a high speed growth of plating, but voids may be generated at a high probability if the circulation of plating liquid inside the via-hole is insufficient. On the other hand, when the electrolytic plating is performed at a low current density (for example, 1 A/dm2), the speed of growing the plating would be slow, but due to this slow growth of plating, the probability of generating voids inside the via-contact layer can be minimized and the productivity would be deteriorated. In view of enhancing the quality of the via-contact layer and of improving the productivity, the current density may preferably be confined within the range of 1-4 A/dm2 or so.

[0126] Incidentally, it may be possible, through the employment of two stages of current density or more on the occasion of forming the via-contact layer, to increase the speed of forming the via-contact layer and to improve the productivity while making it possible to suppress the generation of voids. For example, the current density may be controlled to 1 A/dm2 until the aspect ratio of via-hole is changed from 1.0 to 0.6 by the application of electrolytic plating, and to 2 A/dm2 until the aspect ratio of via-hole is changed from 0.6 to 0.3 by the application of electrolytic plating, and to 4 A/dm2 until the aspect ratio of via-hole is changed from 0.3 to 0 by the application of electrolytic plating. Herein, when the aspect ratio becomes zero, it means the accomplishment of the via-contact layer.

[0127] When the current density is adjusted in this manner, it would be possible to realize an electrolytic copper plating method which is capable of suppressing the generation of voids and enhancing the productivity.

[0128] This electrolytic copper plating method can be realized by constructing a production line having a plurality of plating baths, so that the existing plating apparatus would be sufficiently capable of coping with this plating method. Furthermore, without being restricted by the specific configuration of the via-hole, the aforementioned manufacturing method can be applied not only to a configuration of via-contact where a film of predetermined thickness is formed on the sidewall of the hole (conformal via) but also to a configuration of via-contact where the interior of the hole is completely filled with a metal (field via).

[0129] When the plating in the via-hole shown in FIG. 8C is controlled in such a manner that either the value of (a value of the opening of the via-hole)/(a total value of the thickness of the conductor layer+the thickness of the second film or the third film+the thickness of the first adhesive layer or of the second adhesive layer) or the value of (a value of the opening of the via-hole)/(a total value of the thickness of the conductor layer+the thickness of the first film) is confined to 1.5 or less, the chemical solution can be easily introduced into the hole, thereby making it possible to perform a stable plating. A more preferable range of the aforementioned values is 1.0 or less.

[0130] 3. Step of Forming a Wiring Pattern:

[0131] As for the method of working wirings, there are known a subtractive method where an etching treatment is utilized and a semi-additive method where an electrolytic plating is utilized. Incidentally, the present invention will be further explained with reference to drawings illustrating specific steps described in the following examples. However, the present invention will not be restricted by these specific steps.

[0132] <Subtractive Method>

[0133] According to the subtractive method, since it is designed-such that a deposit layer is formed on the surface of a conductor layer on the occasion of creating electrical connection between the conductor layer formed on the polyimide layer and the via-contact layer, the film thickness would be increased as a whole (for example, the deposit layer 28 in FIG. 8F). When it is tried to work the conductor layer having such a large film thickness for the purpose of forming a wiring by means of etching, it would be badly affected by the side etching, thereby making it difficult to perform the wiring work. If it is desired to overcome such a problem, a soft etching is required to be applied to the deposit layer and also to the conductor layer to thereby optimize the thickness thereof. Namely, the film thickness in this case may preferably be confined within the range of 3 to 10 μm and the non-uniformity in film thickness of these layers may preferably be suppressed to 20% or less.

[0134] The treating liquid for this soft etching can be suitably selected depending on the material of the conductor layer. For example, when copper which is commonly employed is used as a conductor layer and as a deposit layer, it is possible to employ a system comprising an aqueous hydrogen peroxide solution+sulfuric acid; or peroxodisulfates such as sodium peroxodisulfate and ammonium peroxodisulfate.

[0135] After finishing the soft etching treatment, a resist layer is formed on the surface of the conductor—layer, the resist layer being subsequently formed into a mask having a desired pattern. FIG. 8G shows the resist layer 30 that has been formed in a step of working a wiring in Example 1 described below.

[0136] In this case, depending on the conditions for forming the deposit layer, the polishing speed of the deposit layer in the soft etching may be caused to differ from the polishing speed of the conductor layer, so that the portion of interface between the conductor layer and the deposit layer may be exposed non-uniformly in a midway of the process for reducing the film thickness thereof by means of soft etching. If such a situation happens to occur, it may become a cause for generating the non-uniformity of the surface condition or of the film thickness after the soft etching treatment. Therefore, it is preferable to form the conductor layer and the deposit layer in such a way that the film thickness of the conductor layer is controlled in advance so as to make the film thickness of the conductor layer become smaller than a predetermined desired film thickness by a thickness of at least 0.5 μm by means of the soft etching, after which the deposit layer is formed. This soft etching step for adjust the film thickness of the conductor layer in advance may be also utilized in and executed concurrent with the step of removing the dross subsequent to the step of laser working.

[0137] As for the material for this resist layer, it may preferably be selected from materials which are fundamentally resistive to the etching liquid to be employed in the working of the conductor layer and can be easily removed in the final step of removing the resist layer. Further, the material for this resist layer can be suitably selected depending on the method of forming the openings. Specifically, when the openings are to be formed by making use of photolithography, it is preferably to employ a photosensitive resin which is excellent in resistance to the etching solution. More specifically, a dry film resist or a liquid photosensitive resin resist would be suitable for use. Because when these resist materials are employed, an etching solution will be enabled to easily enter the openings and it becomes possible to form the resist layer having such a film thickness that can be prevented from being damaged during the etching treatment, i.e. a film thickness ranging from 3 μm to 7 μm. Further, when the openings are to be formed by means of laser working, the material for this resist layer can be selected from various kinds of resins. However, when the easiness in executing the subsequent step or the resist layer-removing step is taken into account, the employment of a photosensitive resin is more preferable.

[0138] Incidentally, if required, for the purpose of protecting the surface of the substrate which is opposite to the wiring-forming surface, the resist layer may be formed on the surface of the substrate which is opposite to the wiring circuit-forming surface (namely, when wiring working is to be performed to the conductor layer 130 b, the resist layer 30 may be formed on the surface of the conductor layer 130 c). As for the materials for the resist layer to be formed on this opposite surface, they may be selected from any kinds of materials as long as they are excellent in resistance to the plating solution and can be easily removed therefrom. Namely, the material for this resist layer may not necessarily be required to be the same as that of the resist layer to be applied to the wiring-working surface.

[0139] By making use of the aforementioned resist layer formed in this manner as an etching mask, the etching treatment of the conductor layer is performed to thereby work the wiring pattern (see FIG. 8H). The etching liquid to be employed in this etching treatment can be selected depending on the kind of material constituting the conductor layer. For example, when copper is employed for the conductor layer, a solution of iron(III)chloride or a solution of copper(II) chloride can be employed in general as the etching liquid. Among them, the employment of a solution of iron(III)chloride is more preferable in viewpoints of the processing speed of etching and of the excellent finishing of the etched surface. On the other hand, the employment of a solution of copper(II) chloride is more preferable, from the viewpoints of the easiness in controlling the etching liquid and of the stability of the etching liquid.

[0140] Finally, the resist layer is removed to obtain a wiring circuit board (see FIG. 8I).

[0141] <Semi-Additive Method>

[0142] In this semi-additive method, the conductor layers 28 and 29 shown in FIG. 9A are soft-etched so as to reduce the film thickness thereof to a desired thickness. The film thickness reduced in this manner may preferably be confined within the range of 0.5 to 3 μm for the purpose of removing useless matters by means of soft etching in the final step of removing the thin conductor layer. Further, the non-uniformity in film thickness of these layers may preferably be suppressed to 20% or less. Incidentally, the treating liquid to be employed in the soft etching may be the same as that to be employed in the subtractive method.

[0143] In this case, it is also possible to employ a method wherein a thin conductor layer having a film thickness of 0.5 to 3 μm is formed by means of electroless plating after the conductor layers 28 and 29 have been completely removed by means of soft etching or etching.

[0144] Next, resist layers 30 and 31 are deposited on these thin-filmed conductor layers 28 and 29 (see FIG. 9B), and openings 32 b and 32 c formed into a desired pattern are formed in the resist layers 30 and 31 (see FIG. 9C). In this case, these resist layers 30 and 31 may be selected from materials which are fundamentally excellent in resistance to the plating liquid to be employed in the formation of the conductor layer and which can be easily removed in a subsequent resist layer-removal step.

[0145] The material for these resist layers 30 and 31 can be suitably selected depending on the method of forming the openings 32 b and 32 c. Specifically, when the openings 32 are to be formed by making use of photolithography, it is preferably to employ a photosensitive resin which is excellent in resistance to the plating. Generally speaking, the employment of a dry film would be preferable because of the facts that a resist layer of uniform thickness can be obtained and the process involved can be facilitated. Further, when the openings are to be formed by means of laser working, the material for this resist layer can be selected from various kinds of resins. However, when the easiness in executing the subsequent step or the resist layer-removing step is taken into account, the employment of a photosensitive resin is more preferable.

[0146] Incidentally, with reference to FIG. 9B and FIG. 9C, a wiring pattern may be formed only in the conductor layer 130 b, for instance (namely, a wiring pattern is not formed in the conductor layer 130 c). Alternatively, if required, it may be constructed in such a manner that a resist layer 31 is formed on the conductor layer 130 c. If it is constructed in this manner, both of the working surface and the opposite surface can be protected. In this case, the materials for the resist layer 31 to be formed on the conductor layer 130 c side may be selected from any kind of material as long as they are excellent in resistance to the plating solution and can be easily removed therefrom. Namely, the material for this resist layer 31 may not necessarily be required to be the same as that of the resist layer 30 formed on the conductor layer 130 b side.

[0147] Next, as shown in FIG. 9D, an electrolytic plating is applied to the thin conductor layers 130 b and 130 c formed inside the openings of the resist layers 30 and 31 to thereby form deposit layers 33 and 34 having a desired film thickness. In this case, the electrolytic plating bath may preferably be formed of a filled plating bath. This filled plating bath is a kind of electrolytic plating bath wherein a polymeric surfactant, a quaternary ammonium salt and a compound having a sulfide moiety are added therein as an additive for the purpose of filling the holes of the wiring circuit board with a conductive material.

[0148] The height of plating may desirably be formed so as to make it higher than a predetermined desirable height by a height of 0.5 to 3 μm, since this deposit layer is also polished concurrently when a chemical polishing is employed in the final step of removing the thin conductor layer.

[0149] Incidentally, in order to improve the adhesive strength between the conductor layers 130 b and 130 c and the deposit layer, a surface treatment may preferably be performed prior to the formation of the deposit layers 33 and 34. Because if the adhesion strength between the conductor layers 130 b and 130 c and the deposit layer is poor, peeling may be caused to generate between the conductor layers 130 b and 130 c and the deposit layer as the film is rewound in the roll-to-roll process in a subsequent plating step.

[0150] The surface treatment prior to the electrolytic plating can be performed as follows for instance. Namely, the oxidized film formed on the surface of the conductor layer is removed by making use of acidic washing treatment using dilute sulfuric acid. On this occasion, when an acid cleaner comprising sulfuric acid mixed with an activating agent is employed for the removal of the residue of resist which is permitted to remain inside the openings of the resist layers 30 and 31 concurrent with the removal of the oxidized film of the conductor layers 130 b and 130 c, the adhesive strength of the conductor layers 130 b and 130 c to the deposit layer can be further enhanced. Furthermore, when the soft etching treatment is performed after the aforementioned acid washing to thereby completely remove the oxidized film of the conductor layers 130 b and 130 c, the adhesive strength of the conductor layers 130 b and 130 c to the deposit layer can be further enhanced.

[0151] According to the experiments conducted by the present inventors, it has been confirmed that when this surface treatment is performed, the generation of peeling between the deposit layer and the conductor layers 130 b and 130 c can be effectively prevented even if the deposit layer is formed at a current density of 1-4 A/dm2 in the following deposit layer-forming step.

[0152] Then, the resist layers 30 and 31 are removed, and by means of the soft etching, useless portions of the thin conductor layers 130 b and 130 c can be removed, thereby obtaining the multi-layer circuit wiring board 40 as shown in FIG. 9E.

[0153] As the subtractive method is compared with the semi-additive method, the subtractive method is more advantageous in the respects that the number of steps can be minimized and it is easier to practice. On the other hand, the semi-additive method is more advantageous in the respect that a wiring pattern which is finer in line width can be formed as compared with the subtractive method which is highly influenced by the side etching.

[0154] By following the aforementioned manufacturing steps and by suitably changing the means of forming a wiring pattern for each layer, a multi-layer circuit wiring board having a wiring pattern of finer line-and-space can be easily obtained. Namely, the layer which necessitates the formation of a finer wiring pattern may preferably be worked by making use of the semi-additive method, and other layers which do not necessitate the formation of a finer wiring pattern may preferably be worked by making use of the subtractive method. The criterion for judging the switching of this couple of methods would be such that although it depends on the film thickness required in forming the wiring circuit, where the wiring pitch is required to be 30 μm or less for example, the employment of the semi-additive method is more preferable. Because, when the wiring pitch is required to be 30 μm or less, the working of such a fine wiring cannot be achieved by the subtractive method.

[0155] Incidentally, it is desirable, for the purpose of protecting the wiring pattern formed on the outermost surface or for the purpose of providing the wiring pattern with an excellent insulating property, to provide the outermost surface excluding the regions of outer connecting terminals with a solder mask formed of an insulating resin.

[0156] The foregoing explanations regarding the manufacturing process are directed to the manufacture of a 4-ply multi-layer circuit wiring board. If it is required to manufacture a multi-layer circuit wiring board having a larger number of layers such as a 6-ply multi-layer circuit wiring board, additional two layers can be added to the aforementioned 4-ply multi-layer circuit wiring board by making use of the aforementioned manufacturing method.

[0157]FIG. 10 shows a cross-sectional view of a 6-ply multi-layer circuit wiring board. Referring to FIG. 10, a first film 61, a second film 62, a third film 63, a fourth film 65 and a sixth film 66 are bonded together with a first adhesive layer 71, a second adhesive layer 72, a third adhesive layer 73 and a fourth adhesive layer 75 being interposed between any couple of aforementioned films. In this case, a first wiring pattern 81 is formed on the one surface of the first film 61, and a second wiring pattern 82 is formed on the other surface thereof. Further, a third wiring pattern 83 is formed on the one surface of the second film 62, a fourth wiring pattern 84 is formed on the one surface of the third film 63, a fifth wiring pattern 85 is formed on the one surface of the fourth film 65, and a sixth wiring pattern 86 is formed on the one surface of the fifth film 65.

[0158] In this manner, the 6-ply multi-layer circuit wiring board having six layers of wiring patterns 81, 82, 83, 84, 85 and 86 is constructed.

[0159]FIGS. 11 and 12 illustrate respectively a multi-layer circuit wiring board provided with a fixing frame. This fixing frame can be attached via an adhesive 230 to the multi-layer circuit wiring board after accomplishing the manufacture of the multi-layer circuit wiring board. Specifically, FIG. 11 illustrates a state wherein the fixing frame is attached to a 4-ply multi-layer circuit wiring board, while FIG. 12 illustrates a state wherein the fixing frame is attached to a 6-ply multi-layer circuit wiring board.

[0160] Specific examples of the manufacturing method of the multi-layer circuit wiring board will be explained with reference to the following three examples.

EXAMPLE 1

[0161] Example 1 will be explained with reference to FIGS. 8A through 8I. This example illustrates a manufacturing example of multi-layer circuit wiring board where the subtractive method is employed.

[0162] First of all, as shown in FIG. 8A, a film 13 a or a double conductor-layered polyimide tape substrate comprising a polyimide layer 131 a (25 μm for example) and provided, on the opposite surfaces of the polyimide layer 131 a, with conductor layers (copper foil) 130 a and 132 a (12 μm for example) is prepared. Then, a via-hole 190 is formed in this film 13 a as shown in FIG. 8B by means of ultraviolet laser.

[0163] This via-hole 190 is then subjected to a treatment to remove dross and to a desmear treatment, which is followed by DPS and electrolytic copper plating to thereby form a via-contact layer 19 a functioning to electrically connect one surface of the film 13 a with the other surface thereof as shown in FIG. 8C. Incidentally, the reasons to employ the film 13 a comprising a polyimide layer accompanying conductor layers (copper foil) 130 a and 132 a as shown herein are based on the facts that since the adhesion between a conductor layer (copper foil) and a polyimide layer is strong, the provision of rugged surface for the adhesion thereof can be omitted, that it is possible to realize excellent transmission of signals, and that it is possible to form a structure of fine wiring pattern.

[0164] Then, by means of photoetching method, the conductor layers 130 a and 132 a disposed on the opposite surfaces of the film 13 a are patterned to form wiring patterns (wiring circuit) 17 a and 17 b, thereby manufacturing a substrate having a wiring pattern as shown in FIG. 8C. Incidentally, in the course of the aforementioned photoetching, alignment marks (not shown) are formed in the substrate provided with the wiring pattern. These alignment marks become a working reference in the steps of laser working and exposure to be executed in the subsequent multilayer-forming process.

[0165] Then, two films 13 b and 13 c consisting respectively of polyimide layers 131 b and 131 c (for example, 13 μm in thickness) and conductor layers 130 b and 130 c (for example, 12 μm in thickness) which are laminated on the outer surfaces of aforementioned polyimide layers, respectively, are respectively laminated on each of the opposite surfaces of the film 13 a with adhesive layers 15 b and 15 c being respectively interposed therebetween as shown in FIG. 8D. The lamination of these films 13 b and 13 c was performed as follows.

[0166] Namely, a rubber/epoxy-based adhesive layer both surfaces of which are covered respectively with a polyethylene telephthalate release film is employed and one of the release films is removed to expose a layer of adhesive agent of the adhesive layer on the occasion of adhering the adhesive layer to one of the films 13 b and 13 c with the layer of adhesive agent being directed to face said one of the films 13 b and 13 c. The resultant laminate is then subjected to a provisional press-adhesion process by making use of a laminator under the conditions of 180° C. in temperature and 3 kg/cm in pressure.

[0167] Subsequently, after the other release film has been peeled away, single conductor(copper foil)-layered polyimide tape substrates 13 b and 13 c are placed on the adhesive layer with the conductor layers (copper foil) 130 b and 130 c being respectively directed outward and subjected to a press-adhesion under heating by making use of a laminator under the conditions of 180° C. in temperature and 3 kg/cm in pressure. The aforementioned laminating steps are repeated in the lamination to the other surface of the films 13 b and 13 c, and the resultant laminated substrate is subjected to a thermal curing for one hour at a temperature of 150° C. The thickness of each of the adhesive layers disposed on the wiring circuits 17 a and 17 b is 5 μm.

[0168] Then, by making use of an ultraviolet laser beam having a wavelength of 355 nm, the multi-layered substrate shown in FIG. 8D is treated in such a manner that the conductor layers 130 b and 130 c; the polyimide layers 131 b and 131 c; and the adhesive layers 15 b and 15 c are subjected to the irradiation of a laser beam having an energy density of 20 J/cm2, 2 J/cm2 or 8 J/cm2, respectively, to thereby form via-holes 192 as shown in FIG. 8E. The number of pulses irradiated are five pulses for the conductor layers 130 b and 130 c; ten pulses for the polyimide layers 131 b and 131 c; and five pulses for the adhesive layers 15 b and 15 c. Incidentally, the diameter of the opening of these via-holes 192 is 30 μm, the diameter of the bottom portion of these via-holes 192 is 18 μm, and hence the aspect ratio of these via-holes 192 is 0.6.

[0169] After finishing the working using the laser beam, the multi-layered substrate is subjected to chemical polishing using a 20% aqueous solution of sodium peroxodisulfate at a temperature of 30° C. to thereby remove the dross. Further, the multi-layered substrate is subjected to a desmear treatment using a 10% aqueous solution of potassium permanganate at a temperature of 70° C.

[0170] After being treated by means of DPS using a tin-palladium colloid-based catalyst, the multi-layered substrate is subjected to an electrolytic plating in an electrolytic bath comprising 225 g/L of copper sulfate, 55 g/L of sulfuric acid, 60 mg/L of chlorine ion and 20 mL of an additive, with the temperature of the bath being maintained at a temperature of 25° C. Incidentally, the liquid in the bath is stirred using a spray nozzle with a performance of 5 L/min, for instance. Subsequently, an electric current having a current density of 1 A/dm2 is applied to this plating bath system to thereby perform electrolytic plating which is continued for 20 minutes or until the aspect ratio of via-holes becomes 0.3. Further, the electrolytic plating is continued at a current density of 2.5 A/dm2 for 10 minutes or until the aspect ratio of via-holes becomes 0, thereby forming via-contacts 19 b (field via) as shown in FIG. 8F.

[0171] Thereafter, a 20% aqueous solution of ammonium peroxodisulfate 30° C. in temperature is sprayed against plated copper layers 28 and 29 which have been redundantly precipitated over the conductor as a result of the plating step as shown in FIG. BF, thereby performing a soft etching treatment for about 60 seconds for instance to reduce the thickness of the conductor layers 130 b and 130 c to about 9 μm for instance.

[0172] After the surface of the conductor layer is coated with a positive liquid resist by means of a roll coater, the conductor layer is subjected to a post baking treatment for 5 minutes at a temperature of 90° C. by making use of hot air and an IR drying furnace to thereby form the resist layers 30 b and 30 c having a thickness of 4 μm as shown in FIG. 8G.

[0173] Then, by making use of a photomask having a stripe-like circuit pattern consisting of a plurality of straight lines each having a line width of 20 μm and arrayed at a pitch of 30 μm, the resist layers 30 b and 30 c are subjected to a mask-contacted exposure treatment by making use of a parallel beam with a mercury lamp being employed as a light source. Subsequently, the resist layers 30 b and 30 c are further subjected to a spray development using an organic alkali-based developing solution for about 30 seconds to thereby remove the exposed portions of the resist layers 30 b and 30 c to form the openings 30 b and 30 c as shown in FIG. 8H.

[0174] Then, a solution of iron(III) chloride 1.36 in specific gravity and 5° C. in liquid temperature is sprayed against the resist layers 30 b and 30 c for about 30 seconds to perform the etching treatment of these layers, thereby forming a wiring pattern 21 over the polyimide layer 131 b and a wiring pattern 23 over the polyimide layer 131 c.

[0175] Finally, the substrate 111 provided with the resist layer 30 is sprayed for about 15 seconds with a 4% aqueous solution of sodium hydroxide to thereby peel off the resist layer 30, thus obtaining the multi-layer circuit wiring board 11 as shown in FIG. 8I.

[0176] The multi-layer circuit wiring board 11 obtained from the process mentioned above is provided with a stripe-like circuit pattern having a film thickness of 9 μm and consisting of a plurality of straight lines each having a line width of 15 μm and arrayed at a pitch of 30 μm. This circuit pattern can be fabricated into a desired pattern through the employment of a layout in the photolithography thereof. Further, this multi-layer circuit wiring board 11 is formed of a 4-ply circuit wiring (i.e. the pattern 21, the pattern 23, wiring patterns 17 a and 17 b).

[0177] The number of layers of this circuit wiring can be increased as required by repeating the aforementioned laminating process, so that it is possible to manufacture a substrate having a not less than 6-ply circuit wiring.

[0178] Incidentally, all of the steps to be executed in this embodiment (i.e. all of the steps shown in FIG. 8A through FIG. 8I) can be executed by making use of the roll-to-roll system. The reason for this is that polyimide film which is excellent in flexibility is employed herein. In the foregoing explanation, the steps of working and exposure by making use of ultraviolet laser to the opposite surfaces of substrate are sequentially performed surface by surface. However, by concurrently subjecting these opposite surfaces to all of the steps excluding the steps of working and exposure, the speed of manufacturing process can be further enhanced.

EXAMPLE 2

[0179] Example 2 will be explained with reference to FIGS. 8A through 8F, and FIGS. 9A through 9E. This example illustrates a manufacturing example of multi-layer circuit wiring board where the semi-additive method is employed.

[0180] First of all, as explained with reference to FIGS. 8A through 8F, a conductor layer (copper foil) (130 b)-attached polyimide film 13 b is laminated via the adhesive layer 15 b on one surface of the polyimide layer 131 a having the wiring patterns 17 a and 17 b on the opposite surfaces thereof, respectively, and at the same time, a conductor layer (copper foil) (130 c)—attached polyimide film 13 c is laminated via the adhesive layer 15 c on the other surface of the polyimide layer 131 a. Thereafter, via-contact layers 19 a and 19 b are formed so as to electrically connect the conductor layer 130 b with the conductor layer 130 c. Details of treatment in each of the steps are the same as explained with reference to Example 1.

[0181] Then, as shown in FIG. 9A, an aqueous solution of sodium peroxodisulfate is sprayed against the copper layers 28 and 29 for about 120 seconds, thereby performing a soft etching treatment to reduce the thickness of the copper layers 28 and 29 to about 10 μm for instance. Incidentally, during this film-thinning treatment by means of soft etching treatment, the copper layers 28 and 29 that have been formed by means of plating can be dissolved away, and furthermore, the copper layers 130 b and 130 c formed of copper foil are also partially dissolved to make them thinner in film thickness.

[0182] Then, the surfaces of the copper layers 130 b and 130 c thus reduced in thickness are respectively laminated under heating and pressure with a 15 μm-thick negative dry film resist by means of a roll laminator, thereby forming the resist layers 30 and 31 as shown in FIG. 9B.

[0183] Then, by making use of a photomask having a stripe-like circuit pattern consisting of a plurality of straight lines each having a line width of 10 μm and arrayed at a pitch of 20 μm, the resist layers 30 and 31 are subjected to a mask-contacted exposure treatment by making use of a parallel beam with a mercury lamp being employed as a light source. Subsequently, the resist layers 30 and 31 are further subjected to a developing treatment using a 1% sodium carbonate solution to thereby remove the unexposed portions of the resist layers to form the openings 32 b and 32 c as shown in FIG. 9C.

[0184] Then, by making use of an acidic cleaner, the resultant surface is acid-washed under the conditions of: 40° C. in temperature and 4 minutes in washing time, which is followed by a soft etching treatment wherein an aqueous solution of sodium peroxodisulfate is sprayed against the surface for about 15 seconds, thereby performing a chemical polishing of the exposed surfaces of the conductor layers (copper foil) 130 b and 130 c.

[0185] Then, an electrolytic copper plating for forming a wiring on the surface of the thin film conductor-layer provided inside the openings 32 b and 32 c of the resist layers 30 and 31 is performed for 10 minutes at a current density of 2 A/dm2 to thereby form copper plate layers 33 and 34 each having a thickness of 10 μm as shown in FIG. 9D.

[0186] Then, the substrate is sprayed for about 30 seconds with a 5% aqueous solution of sodium hydroxide to thereby peel off the resist layers 30 and 31.

[0187] Finally, an aqueous solution of sodium peroxodisulfate is sprayed against the resultant surface for 90 seconds to perform the soft etching treatment thereof to thereby remove the redundant portions of the conductor layers 130 b and 130 c where the copper plating layers 33 and 34 are not formed.

[0188] As a result of aforementioned steps, it is found possible to obtain a multi-layer circuit wiring board 40 provided with a stripe-like circuit pattern consisting of a plurality of straight lines each having a line width of 10 μm and arrayed at a pitch of 20 μm as shown in FIG. 9E.

[0189] This multi-layer circuit wiring board is provided with almost the same features as that of the multi-layer circuit wiring board 11 described in Example 1 in the respects that the pattern of each of wiring circuits can be optionally selected, that it is possible to further increase the number of layers, that it can be manufactured by way of the roll-to-roll system, that the opposite surfaces of substrate can be concurrently treated in all of the steps excluding the steps of working and exposure wherein the opposite surfaces of substrate is required to be individually or separately treated.

EXAMPLE 3

[0190] Example 3 will be explained with reference to FIGS. 13A through 13C. This example illustrates a manufacturing example of a multi-layer circuit wiring board 50 having a 6-ply circuit wiring wherein the subtractive method and the semi-additive method are combined.

[0191] First of all, by the same method as explained in Example 1, there is fabricated, as shown in FIG. 13A, a multi-layer circuit wiring board 11 formed of a 4-ply circuit substrate which is provided with a stripe-like wiring pattern consisting of a plurality of straight lines each having a line width of 15 μm and arrayed at a pitch of 30 μm.

[0192] Then, as shown in FIG. 13B, a film 13 d comprising a conductor layer (copper foil) 130 d and a polyimide film 131 d is laminated via the adhesive layer 15 d on one surface of the multi-layer circuit wiring board 11, and at the same time, a film 13 e comprising a conductor layer (copper foil) 130 e and a polyimide film 131 e is laminated via the adhesive layer 15 e on the other surface of the multi-layer circuit wiring board 11.

[0193] Subsequently, as shown in FIG. 13C, in the same manner as explained in Example 1, a via-hole 19 d is formed in the film 13 d, and a via-hole 19 e is formed in the film 13 e. Thereafter, as shown in FIGS. 13D through 13F, in the same manner as explained in Example 2, plated layers 44 and 45 are formed. Namely, as shown in FIG. 13D, copper layers 34 and 35 are formed by means of electrolytic plating, and by way of a soft etching treatment, the film thickness of these copper layers 34 and 35 is reduced. Then, as shown in FIG. 13E, resist patterns 36 and 37 are formed on the surfaces of copper layers 34 and 35. Then, as shown in FIG. 13F, deposit layers 44 and 45 are formed by way of an electrolytic plating.

[0194] By finishing each of the aforementioned steps, it is now possible to manufacture the multi-layer circuit wiring board 50 formed of a 6-ply circuit substrate which is provided with stripe-like wiring patterns 50 a and 50 b consisting of a plurality of straight lines each having a line width of 10 μm and arrayed at a pitch of 20 μm as shown in FIG. 13G.

[0195] In the manufacture of this multi-layer circuit wiring board 50 also, it is possible to provide almost the same features as that of the multi-layer circuit wiring board 11 described in Example 1 in the respects that the pattern of each of wiring circuits can be optionally selected, that it is possible to further increase the number of layers, that it can be manufactured by way of the roll-to-roll system, that the opposite surfaces of substrate can be concurrently treated in all of the steps excluding the steps of working and exposure wherein the opposite surfaces of substrate is required to be individually or separately treated.

[0196] As shown in FIG. 12, a fixing frame 210 which has been produced through the etching of a copper plate having a thickness of 0.5 mm and made into a predetermined configuration can be adhered onto the wiring board, thereby making it possible to manufacture a fixing frame-attached multi-layer circuit wiring board.

EXAMPLE 4

[0197] Example 4 will be explained with reference to FIGS. 14A through 14L. This example illustrates a manufacturing example of a multi-layer circuit wiring board wherein a composite film comprising a couple of insulating layers with a conductor layer being interposed therebetween is employed and the composite film is successively laminated one upon another, thereby forming the multi-layer circuit wiring board. The materials and dimensions of each layer, as well as the conditions for each of the treatments and each of the steps are the same as those of Examples 1 to 3.

[0198] A shown in FIG. 14A, a film substrate—comprising an insulating layer 1 a which is sandwiched between a couple of conductor layers 2 a and 2 b is prepared. Then, as shown in FIG. 14B, via-holes 3 a are formed in this film substrate by means of laser working. Thereafter, as shown in FIG. 14C, one surface of the conductor layer 2 b is laminated and protected with a resist layer 5 and then the film substrate is subjected to a desmear treatment so as to remove any residue that might have been generated on the occasion of forming the via-holes. Thereafter, the film substrate is subjected to a conductivity-providing treatment and then to an electrolytic plating to thereby fill the via-holes 3 a with a metal to form a deposit layer 4 a.

[0199] Then, this deposit layer 4 a is subjected to a chemical polishing to reduce the thickness thereof to the range of 3 to 12 μm and at the same time, the non-uniformity in film thickness of the conductor body comprising a conductor layer 2 a and the deposit layer 4 a is minimized to 20% or less. Thereafter, by making use of a resist pattern (not shown) as a mask, the conductor body is subjected to an etching treatment to thereby selectively remove useless portions of the conductor layer, thus forming a wiring layer 6 a having a predetermined pattern as shown in FIG. 14D.

[0200] Subsequently, as shown in FIG. 14E, an adhesive layer 7 a is laminated on one of the opposite surfaces of the insulating layer 1 a having a wiring pattern 6 a formed thereon, and an adhesive film comprising an insulating layer 1 b laminated with a conductor layer 2 c is laminated on the other surface of the opposite surfaces of the insulating layer 1 a with the conductor layer 2 c being directed outside of the laminate. Next, as shown in FIG. 14F, via-holes 3 b are formed in this adhesive film by means of laser working.

[0201] Thereafter, the resultant laminate is subjected to a desmear treatment so as to remove any residue that might have been generated on the occasion of forming the via-holes. Thereafter, the laminate is subjected to a conductivity-providing treatment and then to an electrolytic plating to thereby fill the via-holes 3 b with a metal to form a deposit layer 4 b as shown in FIG. 14G. Then, this deposit layer 4 b is subjected to a chemical polishing to reduce the thickness thereof to the range of 3 to 12 μm and at the same time, the non-uniformity in film thickness of the conductor body comprising a conductor layer 2 c and the deposit layer 4 b is minimized to 20% or less. Thereafter, by making use of a resist pattern (not shown) as a mask, the conductor body is subjected to an etching treatment to thereby selectively remove useless portions of the conductor layer, thus forming a wiring layer 6 b having a predetermined pattern as shown in FIG. 14H.

[0202] Subsequently, as shown in FIG. 14I, an adhesive layer 7 b is laminated on one of the opposite surfaces of the insulating layer 1 b having a wiring pattern 6 b formed thereon, and an adhesive film comprising an insulating layer 1 c laminated with a conductor layer 2 d is laminated on the other surface of the opposite surfaces of the insulating layer 1 b with the conductor layer 2 d being directed outside of the laminate. Next, as shown in FIG. 14J, via-holes 3 c are formed in this adhesive film by means of laser working.

[0203] Thereafter, the resultant laminate is subjected to a desmear treatment so as to remove any residue that might have been generated on the occasion of forming the via-holes. Thereafter, the laminate is subjected to a conductivity-providing treatment and then to an electrolytic plating to thereby fill the via-holes 3 c with a metal to form a deposit layer 4 c as shown in FIG. 14K. Then, after the resist film 5 functioning as a protective layer is removed, the conductor layer 2 b and the deposit layer 4 c are subjected to a chemical polishing to respectively reduce the thickness thereof to the range of 3 to 12 μm and at the same time, the non-uniformity in film thickness of the conductor body is minimized to 20% or less. Thereafter, by making use of a resist pattern (not shown) as a mask, the conductor body is subjected to an etching treatment to thereby selectively remove useless portions of the conductor layer, thus forming, as shown in FIG. 14L, wiring layers 6 c and 6 d each having a predetermined pattern.

[0204] When the steps described above are performed based on the roll-to-roll system, the multi-layer circuit wiring board can be efficiently mass-produced.

[0205] According to the construction of the present invention, it is now possible to obtain the following advantages.

[0206] The multi-layer circuit wiring board to be obtained according to this embodiment is constituted by a lamination of films comprising, for example, a polyimide layer functioning as an insulating layer, and copper foil functioning as a conductor layer. Therefore, the adhesion between the insulating layer and the conductor layer is very strong, and the irregularities for generating an anchoring effect are extremely minimal. As a result, it is possible to sustain the linearity of the wiring pattern, and to prevent non-uniformity from developing in lateral direction, thereby making it possible to realize an enhanced speed in transmitting signals at a high density.

[0207] The multi-layer circuit wiring board to be obtained according to this embodiment is formed of a laminate of films each excellent in flexibility. Accordingly, it is possible to adopt a roll-to-roll technique which is designed to continuously manufacture a multi layer circuit wiring board by making-use of a long strip of base material, and hence the multi-layer circuit wiring board according to this embodiment is suited in realizing the mass-production thereof.

[0208] For example, when a film consisting of a polyimide layer and copper foil is employed, a wiring pattern having a fine line-and-space can be easily formed. Accordingly, it is now possible to reduce the number of layers to be laminated as compared with the conventional multi-layer circuit wiring board. As a result, an IC package which is highly miniaturized can be easily mass-produced.

[0209] Although the present invention has been explained on the basis of specific examples in the foregoing description, it would be obvious to a person skilled in the art to variously modify and change the present invention within the scope of the idea of the present invention. Therefore, it may be understood that these modifications and changes will fall within the scope of the present invention. Further, each of embodiments disclosed herein may be executed by suitably combining them in any possible manner to thereby obtain the effects of such combinations. Further, the aforementioned embodiments include inventions of various stages and hence it may be possible to derive various inventions through the combinations of such inventions. For example, even if some constituent elements is eliminated from the entire constituent elements disclosed in these embodiments, if any of the objects set forth in the column of object can be solved by such a construction, and if it is possible, by such a construction, to derive at least one of the effects set forth in the column of the effects of the invention, the construction may be considered to fall within the scope of the present invention.

[0210] According to the manufacturing method of the multi-layer circuit wiring board as set forth by the present invention, it is possible to provide a multi-layer circuit wiring board and an IC package, each provided with a wiring pattern having a fine line-and-width and suited for the mass-production thereof, and to provide a manufacturing method of such a multi-layer circuit wiring board.

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Legal Events
DateCodeEventDescription
Mar 25, 2004ASAssignment
Owner name: TOPPAN PRINTING CO., LTD., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TSUKAMOTO, TAKEHITO;MATSUZAWA, HIROSHI;AKIMOTO, SATOSHI;AND OTHERS;REEL/FRAME:015143/0609
Effective date: 20040315