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Publication numberUS20040183213 A1
Publication typeApplication
Application numberUS 10/767,623
Publication dateSep 23, 2004
Filing dateJan 28, 2004
Priority dateDec 28, 2001
Also published asUS6946738, US7253526, US20030122213, US20050230814
Publication number10767623, 767623, US 2004/0183213 A1, US 2004/183213 A1, US 20040183213 A1, US 20040183213A1, US 2004183213 A1, US 2004183213A1, US-A1-20040183213, US-A1-2004183213, US2004/0183213A1, US2004/183213A1, US20040183213 A1, US20040183213A1, US2004183213 A1, US2004183213A1
InventorsChi-Hsing Hsu, Wen-Yuan Chang
Original AssigneeChi-Hsing Hsu, Wen-Yuan Chang
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor packaging substrate and method of producing the same
US 20040183213 A1
Abstract
A semiconductor packaging substrate and a process for producing the same is disclosed. An internal circuit is formed by lamination. Then, external circuit is formed on the internal circuit by build-up technology. The substrate can be used as a flip-chip ball grid array packaging substrate with high density and small pitch. Furthermore, the substrate of the invention has a plurality of bonding pads thereon. The bump pads are divided into power/ground bump pads, first signal bump pads, and second signal bump pads. The first signal bump pads surround the power/ground bump pads and are surrounded by the second signal bump pads.
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Claims(17)
What is claimed is:
1. A semiconductor packaging substrate, comprising:
a laminated circuit structure having a first surface and a second surface, the laminated circuit structure comprising:
a plurality of patterned internal metal layers stacked up;
a plurality of internal insulation layers, wherein each of the internal insulation layers is interposed between two adjacent internal metal layers; and
at least one contact via formed through the internal metal layers and the internal insulation layers, such that the internal metal layers are electrically connected to one another;
a build-up circuit structure on the first surface and the second surface of the laminated circuit, the build-up circuit structure comprising:
a first external insulation layer having at least one first via and a second external insulation layer having at least one second via respectively arranged on the first surface and the second surface of the laminated circuit;
 ; and
a patterned first external metal layer located on the first external insulation layer and a patterned second external metal layer located on the second external insulation layer, wherein the first external metal layer and the second external metal layer are electrically connected to the internal metal layers of the laminated circuit by the first and the second vias, respectively, and wherein the first external metal layer has a plurality of firstexternally exposed areas and the second external metal layer has a plurality of second externally exposed areas.
2. The substrate of claim 1, further comprising a first solder mask that covers the first external insulation layer and the first external metal layer, and exposes the the first externally exposed areas.
3. The substrate of claim 1, further comprising a second solder mask that covers the second external insulation layer and the second external metal layer, and exposes the second externally exposed areas.
4. The substrate of claim 1, wherein the substrate is used as a flip-chip ball grid array packaging substrate.
5. The substrate of claim 1, wherein the first externally exposed areas are used as bump pads and the second externally exposed areas are used as ball pads.
6. A process for forming a semiconductor packaging substrate, comprising:
forming a laminated circuit having a first surface and a second surface opposite to the first surface, wherein the laminated circuit has a plurality of patterned internal metal layers stacked up, and has a plurality of internal insulation layers each of which is interposed between two adjacent internal metal layers;
forming at least one contact via through the internal metal layers and the internal insulation layers, such that the internal metal layers electrically connect to one another;
forming a first external insulation layer and a second external insulation layer respectively on the first surface and the second surface of the laminated circuit, wherein the first external insulation layer has at least one first opening and the external second insulation layer has at least one second opening;
forming a first via in each of the first opening and a second via in each of the second opening;
forming a first external metal layer on the first external insulation layer and a second external metal layer on the second external insulation layer, wherein the first and second external metal layer are electrically connected to the internal metal layers of the laminated circuit respectively through the first and second vias, and wherein the first external metal layer has a plurality of first externally exposed areas and the second external metal layer has a plurality of second externally exposed areas.
7. The process of claim 6, wherein the forming the contact via includes mechanically drilling and plating on the laminated circuit.
8. The process of claim 6, wherein the forming the first and the second vias includes non-mechanically drilling and plating on the first and second external insulation layers, respectively.
9. The process of claim 7, wherein the non-mechanically drill is selected from a group consisting of photo-via forming, laser ablating and plasma etching.
10. The process of claim 6, further comprising a step of forming a first solder mask on the first external metal layer to cover the first external insulation layer and expose the first externally exposed areas, after forming the first external metal layer.
11. The process of claim 6, further comprising a step of forming a second solder mask on the second external metal layer to cover the second external insulation layer and expose the second externally exposed areas, after forming the second external metal layer.
12. The process of claim 6, wherein the semiconductor packaging substrate is a flip-chip ball grid array packaging substrate.
13. The process of claim 6, wherein forming the internal metal layers of the laminated circuit includes forming and patterning copper foils.
14. A semiconductor packaging substrate, comprising:
a first, second, third, fourth, fifth, and sixth patterned metal layers sequentially stacked up, wherein the first metal layer has a plurality of power/ground bump pads, a plurality of first signal bump pads and a plurality of second signal bump pads, and wherein the first signal bump pads surround the power/ground bump pads and are surrounded by the second signal bump pads, and wherein the sixth metal layer has a plurality of ball pads;
a plurality of inner insulation layers, located between the second and third metal layers, between the third and fourth metal layers, and between the fourth and fifth metal layers; and
at least one contact via formed through the insulation layers and the second, the third, the fourth, and the fifth metal layers, such that the second, the third, the fourth, and the fifth metal layers are electrically connected to one another;
a first external insulation layer and a second external insulation layer arranged between the first and second metal layers and between the fifth and the sixth metal layers, respectively; and
at least one first via formed through the first external insulation layer i and at least one second via formed through the second external insulation layer, thereby the first metal layer being electrically connected to the second metal layer through the first via, and the sixth metal layer being electrically connected to the fifth metal layer through the second via;
wherein the first signal bump pads are routed to the sixth metal layer and then fanned out to the corresponding ball pads, the second signal bump pads are fanned out on the first metal layer and then routed to the corresponding ball pads , and the power/ground bump pads are routed to the third and fourth metal layers and then fanned out to the corresponding ball pads.
15. The substrate of claim 14, further comprising a first solder mask arranged on the first external metal layer to cover the first external insulation layer and expose the power/ground bump pads, the first signal bump pads and the second signal bump pads.
16. The substrate of claim 14, further comprising a second solder mask arranged the sixth metal layer to cover the second external insulation layer and expose the ball pads.
17. The substrate of claim 14, wherein the substrate is used as a flip-chip ball grid array packaging substrate.
Description
CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority benefit of Taiwan application serial no. 90132738, filed Dec. 28, 2001.

BACKGROUND OF THE INVENTION

[0002] 1. Field of Invention

[0003] The present invention relates to a semiconductor packaging substrate and a process for producing the same. More specifically, the present invention relates to a semiconductor substrate that can be used in flip-chip ball grid array packaging.

[0004] 2. Description of Related Art

[0005] Flip chip packaging has been a popular packaging technology. In flip chip packaging, bump pads are arranged in area array on an active surface of a chip. Bumps are formed on the corresponding bump pads to electrically connect the chip to the carrier. Flip chip packaging has many advantages such as reduced package area, increased package density, and reduced signal path. A rigid substrate is usually used as a packaging carrier, because it can provide high-density and high-pin-count layout. Generally, the rigid substrate is formed by lamination or build-up.

[0006]

[0007] In the rigid substrate lamination process, more than one single-sided or double-sided sheets having copper foil thereon are provided. Each of the copper foils is patterned to form a patterned metal layer. A bonding sheet is interposed between the sheets and bonded with them by thermal compression. Then, mechanically drilling and plating processes are sequentially performed to form plating through holes (PTH) though the sheets for electrically connecting the metal layers.

[0008] In the rigid substrate build-up process, insulation layers and patterned metal layers are sequentially formed on an insulated core base. The metal layers are electrically connected to one another by at least one contact via. The contact via is formed by forming a through hole in the insulation layers and the patterned metal layers and then plating to fill the through hole. Forming the through hole is achieved by non-mechanically drilling process such as photo-via forming, laser ablating and plasma etching.

[0009]FIG. 1 is a schematic, cross-sectional view of a conventional flip-chip ball grid array packaging substrate obtained by build-up technology. The packaging substrate 100 has a core 110 having copper foils on both sides thereof as a base. The copper foils are patterned to form metal layers 112 on both sides of the base. Mechanically drilling and plating processes are sequentially performed to form vias 114 for electrically connecting with the metal layers 112. Insulation layers 120 a are respectively formed on the metal layers 112. Then, each of the insulation layers 120 a is subject to non-mechanically drilling such as photo-via forming, laser ablating and plasma etching to form a first opening therein, respectively. A plating process is performed to form a via 140 a in each of the first openings and form metal layers 130 a respectively on the insulation layers 120 a. The metal layers 130 a are electrically connected to the metal layers 112 through the vias 140 a. Similarly, the insulation layers 120 b, the metal layers 130 b and the vias 140 b are formed in the same way recited above. Finally, solder masks 150 are formed over the whole structure, while partially exposing the outmost metal layers 130 b for external connection. The exposed portions of the outmost metal layer 130 b on a top of the structure are used as bump pads 132, and those on a bottom of the structure are used as ball pads 134.

[0010] In accordance with flip-chip ball grid array (FCBGA) packaging, when the bump pitch is less than 240 micron, the layout thereof is limited to 40 micron/40 micron (line width/line pitch) design rule. Since a high-density and small-pitch packaging substrate can be obtained by build-up technology, such a packaging substrate can meet the requirement of a high-pin-count device. Currently, the FCBGA substrate has six layers and is formed by build-up fabrication. The number of build-up layers increases with the circuit density increases. However, the FCBGA substrate has disadvantages of low yield and high production cost.

SUMMARY OF INVENTION

[0011] It is an object of the present invention to provide a semiconductor packaging substrate and a process for producing the same. A laminated circuit is an inner circuit instead of a build-up circuit that is commonly used in the art. Thereby, the yield of a flip-chip ball grid array substrate is increased with reduced production cost.

[0012] In one aspect of the invention, a semiconductor packaging substrate including a laminated circuit, the laminated circuit includes a plurality of patterned internal metal layers stacked up, a plurality of insulation layers, and at least one contact via is provided. Each of the insulation layers is interposed between two adjacent internal metal layers. The contact via is formed through the metal layers and the insulation layers, so that the stacked metal layers are electrically connected to one another. In another aspect of the invention, the packaging substrate also includes a build-up structure, in which the first external insulation layer and a second external insulation layer are respectively arranged on a first surface and a second surface of the laminated circuit. The first external insulation layer has a first opening for forming a first via. The second external insulation layer has a second opening for forming a second via. A first via is formed in the first opening, and a second via is formed in the second opening. A first external metal layer is located on the first external insulation layer. A second external metal layer is located on the second external insulation layer. The first external metal layer is electrically connected to the first via, and the second external metal layer is electrically connected to the second via, such that the first and second external metal layers are electrically connected to the metal layers of the internal laminated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

[0014]FIG. 1 is a schematic cross-sectional view of a conventional flip-chip ball grid array packaging substrate;

[0015]FIG. 2 is a schematic, cross-sectional view of a semiconductor packaging substrate according to one preferred embodiment of the present invention;

[0016]FIG. 3 is a schematic enlarged view showing the layout of a first metal layer 230 of FIG. 2;

[0017]FIG. 4 is a schematic enlarged view showing the layout of a sixth metal layer 236 of FIG. 2; and

[0018]FIG. 5 schematically shows a bump pad of a semiconductor packaging substrate according to one preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0020]FIG. 2 is a schematic cross sectional view of a semiconductor packaging substrate according to a preferred embodiment of the present invention. A semiconductor packaging substrate 200 includes a core 202, and metal layers 204, 206 formed on a top and a bottom surfaces of the core 202, respectively. The core 202 can be made of glass epoxy resin, bismaleimide-triazine (BT) resin or epoxy resin. The metal layers 204, 206 are formed by providing a copper layer on the core 202 and patterning the copper layer. An insulation layer 208 having a patterned metal layer 212 thereon, and an insulation layer 210 having a patterned metal layer 214 thereon are provided. The insulation layers 208, 210 are adhered to the top and the bottom of the core 202, respectively, with the patterned metal layers 212, 214 exposed. At least one contact via is formed through the insulation layers 208, 210 and the core 202 for electrically connecting the metal layers 204, 206, 212 and 214. A laminated internal circuit 218 is therefore accomplished.

[0021] Thereafter, build-up circuits 224, 226 are formed on a top and a bottom of the laminated internal circuit 218, respectively. The build-up circuit 224 consists of an insulation layer 228, a patterned metal layer 230 and a plurality of vias 232. Similarly, the build-up circuit 226 consists of an insulation layer 234, a patterned metal layer 236 and a plurality of vias 238. The build-up circuit 224 is formed in the following steps. The insulation layer 228 is formed on a top surface 220 of the laminated circuit 218. An opening is formed in the insulation layer 228 in a non-mechanic way, such as by a photo via forming, laser ablating or plasma etching. A plating process is performed to form a metal layer 230 on the insulation layer 228 and a via 232 filling the opening at the same time. The via 232 electrically connects the metal layer 230 to the metal layer 212 of the laminated circuit 218. The opening formed by laser ablating has a smaller diameter than the contact via formed by mechanically drilling.

[0022] Subsequently, a solder mask 240 is formed on the insulation layer 228 and the metal layer 230, exposing a portion of the metal layer 230 for forming pads 244. Similarly, a solder mask 242 is formed on the insulation layer 234 and the metal layer 236, exposing a portion of the metal layer 236 for forming pads 246. In this embodiment of the present invention, such a semiconductor packaging substrate 200 is used in flip-chip BGA packaging; therefore, the pads 244 serve as bump pads, and the pads 246 serve as solder ball pads for attaching solder balls.

[0023] The embodiment of the present invention shown in FIG. 2 is illustrated by exemplifying a six-layered semiconductor packaging substrate. However, the number of the internal laminated circuit layer or the external build-up circuit layer can be varied according to the number of bumps for easier circuit layout. After most of the circuit structure of the package substrate 200 is achieved by the lamination, the pads 244, 246 are respectively formed by build-up technology for external connections. Lamination technology is well known and used in the art to produce semiconductor packaging substrates. Therefore, the yield of producing the packaging substrates, especially a Flip Chip BGA packaging substrate, is substantially increased by forming the internal circuit by lamination and forming the external circuits and pads by build-up fabrication.

[0024]FIG. 3 is a schematic, local layout of a first metal layer 230 of the substrate as shown in FIG. 2. FIG. 4 is a schematic, local layout of a sixth metal layer 236 of the substrate as shown in FIG. 2. FIG. 5 is a schematic, local layout of the (bump pads of the substrate as shown in FIG. 2. As shown in FIG. 5, the bump pads of the substrate 200 are arranged in array. The bump pads 244 in FIG. 2 are the same as the bump pads 304 in FIGS. 3 and 5. The ball pads 246 in FIG. 2 are the same as the ball pads 404 in FIG. 4. It is noted that the internal pads serve as power/ground bump pads 310, 320, the middle pads serve as first signal bump pads 330, 340, and the outer pads serve as second signal bump pads 350, 360, as shown in FIG. 5.

[0025] In FIG. 3, reference numeral 300 is an edge of the substrate 200, and reference numeral 302 is a chip edge on the substrate 200. The power/ground bump pads 310, 320 are routed to the third metal layer 204 and the fourth metal layer 206 through a via 306 (i.e. 232 in FIG. 2), and then routed to the ball pad 246 (i.e. 404 of FIG. 4) through the contact via 216, the fifth metal layer 214, the via 238 (i.e.406 in FIG. 4), and the trace 408 on the sixth metal layer 236. The third and fourth metal layers 204, 206 serve as power/ground planes.

[0026] The first signal pads 330, 340 are routed to the sixth metal layer 236 sequentially through the via 306 (i.e.232 of FIG. 2), the second metal layer 212 of FIG. 2, the contact via 216 of FIG. 2, the fifth metal layer 214 of FIG. 2, and the via 238 (i.e.406 of FIG. 4), and then fanned out through trace 408 to the ball pad 404 of FIG. 4 (i.e. 246 on the sixth metal layer 236).

[0027] The second signal bump pads 350, 360 are fanned out to the chip edge 302 by trace 308 on the first metal layer 230, and then connect to the ball pad 246 (i.e.404 of FIG. 4) through the via 306 (i.e.232 of FIG. 2), the second metal layer 212, the contact via 216, the fifth metal layer 214, the via 238 (i.e.406 of FIG. 4) and the sixth metal layer 236 (i.e.408 of FIG. 4).

[0028] The layout of the package substrate according to the present invention is achieved by fanning the second signal bump pads out to the chip edge through the trace on the first metal layer and then routing to the ball pads, as well as by routing the first signal bump pads to the sixth metal layer and then fanning out to the ball pads on the sixth metal layer. When the first and sixth metal layers can not provide enough space for routing, the second, fourth and fifth metal layers can be used for routing, thereby downwardly routing the first metal layer and then fanning out to the sixth metal layer.

[0029] In view of the foregoing, the invention preferably uses lamination technology to form a laminated circuit. Then, the external circuit is formed by build-up technology. The package substrate thus obtains characteristics such as high circuit density and small pitch, which is advantageously used as a flip-chip ball grid array package substrate. Since the lamination technology has been well used in the art, with a laminated circuit as a portion of the package substrate the yield of the substrate is increased, with reduced production cost.

[0030] Furthermore, the bump pads on the top of the semiconductor packaging substrate of the invention serve as power/ground bump pads, the first signal bump pads and the second signal bump pads. The power/ground bump pads are located near the center of the substrate. The first signal bump pads are distributed around the power/ground bump pads. The second signal bump pads are located around the first signal bump pads. The substrate has several metal layers arranged sequentially from the top to the bottom. Among the layers, the middle layers of the substrate serve as power/ground planes.

[0031] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US6933613 *Jan 6, 2004Aug 23, 2005Kabushiki Kaisha ToshibaFlip chip ball grid array package
US7208403 *Mar 21, 2006Apr 24, 2007Silicon Integrated Systems Corp.Tile-based routing method of a multi-layer circuit board and related structure
US7368374 *Oct 12, 2004May 6, 2008Micron Technology Inc.Super high density module with integrated wafer level packages
US7579681Jun 11, 2002Aug 25, 2009Micron Technology, Inc.Super high density module with integrated wafer level packages
US7884007Jul 30, 2007Feb 8, 2011Micron Technology, Inc.Super high density module with integrated wafer level packages
US8065796Feb 22, 2007Nov 29, 2011Edwards Lifesciences CorporationMethod and apparatus for using flex circuit technology to create an electrode
US8304894Feb 28, 2007Nov 6, 2012Micron Technology, Inc.Super high-density module with integrated wafer level packages
US8546701Oct 19, 2011Oct 1, 2013Edwards Lifesciences CorporationMethod and apparatus for using flex circuit technology to create an electrode
US8698295Feb 28, 2007Apr 15, 2014Micron Technology, Inc.Super high-density module with integrated wafer level packages
EP2131635A1 *Feb 22, 2007Dec 9, 2009Edwards Lifesciences CorporationActive electrode and method for manufacturing it using flex circuit technology
WO2007098187A2 *Feb 22, 2007Aug 30, 2007Edwards Lifesciences CorpActive electrode and method for manufacturing it using flex circuit technology
Classifications
U.S. Classification257/786, 438/612, 257/E23.07, 257/E23.062
International ClassificationH05K3/46, H01L23/498, H05K1/11
Cooperative ClassificationH05K1/114, H01L2924/0002, H05K3/4602, H01L23/49838, H01L23/49822, H05K2201/09536
European ClassificationH05K3/46A, H01L23/498D, H01L23/498G