Publication number | US20040196171 A1 |

Publication type | Application |

Application number | US 10/405,191 |

Publication date | Oct 7, 2004 |

Filing date | Apr 1, 2003 |

Priority date | Apr 1, 2003 |

Also published as | US6798372 |

Publication number | 10405191, 405191, US 2004/0196171 A1, US 2004/196171 A1, US 20040196171 A1, US 20040196171A1, US 2004196171 A1, US 2004196171A1, US-A1-20040196171, US-A1-2004196171, US2004/0196171A1, US2004/196171A1, US20040196171 A1, US20040196171A1, US2004196171 A1, US2004196171A1 |

Inventors | Yaohua Yang, Ruoxin Jiang, Rumin Yin |

Original Assignee | Yaohua Yang, Ruoxin Jiang, Rumin Yin |

Export Citation | BiBTeX, EndNote, RefMan |

Patent Citations (1), Referenced by (4), Classifications (8), Legal Events (4) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 20040196171 A1

Abstract

A frequency-to-current converter operative to convert a clock frequency to an output current is described; the frequency-to-current converter ensures that the output current increases linearly with the clock frequency. The frequency-to-current converter may be incorporated in analog-to-digital converters driven by clocks with variable frequencies. The frequency-to-current converter employs an integrator circuit, used to compare an input reference voltage and a current feedback into a sampling capacitor. At steady state, the feedback current is just sufficient to discharge the sampling capacitor to a fixed voltage. The core of the frequency-to-current conversion circuit includes one opamp, two capacitors, one feedback transistor and a few switches.

Claims(36)

an operational amplifier;

a feedback capacitor coupled to the negative input of the operational amplifier and an output of the operational amplifier;

a sampling capacitor coupled to the negative input of the operational amplifier, via a first switch;

a reference voltage coupled to a positive input of the operational amplifier; and

wherein a current output of the integrator circuit varies linearly with a clock frequency of the master clock.

a clock detector, the clock detector operative to disable the frequency-to-current converter when the clock halts.

an input from a master clock;

a first output for a first phase of the multi-phase clock generator, the first phase comprising a reset phase for the frequency-to-current converter;

a second output for a second phase of the multi-phase clock generator, the second phase comprising a charge phase for the frequency-to-current converter;

a third output for a third phase, the third phase comprising a comparison phase for the frequency-to-current converter.

receiving the variable clock frequency; and

biasing one or more amplifiers in the frequency-to-current converter circuit with one or more currents proportional to the variable clock frequency.

an integrator circuit for determining the output current;

an input reference voltage coupled to the integrator circuit;

a current feedback from the integrator circuit;

a sampling capacitor receiving the current feedback; and

wherein the feedback current is sufficient to discharge the sampling capacitor to a fixed voltage.

a master clock;

one or more analog circuit blocks operative to receive an analog input to the analog-to-digital converter;

a frequency-to-current converter supplying a current to the one or more analog circuit blocks, such that the current is proportional to the frequency of the master clock.

Description

- [0001]The invention relates to the field of electronics, and more specifically to circuits for frequency to current conversion.
- [0002]Frequency-to-voltage and frequency-to-current converters are employed in numerous types of applications. One such application is the field of analog-to-digital conversion, in which power consumption by analog-digital processors is a persistent and increasingly complicated issue. Applications such as Analog-to-Digital converters (ADCs), require features such as an adaptive bias current, which enable analog-to-digital conversion while saving power consumption. Tools such as a frequency-to-current converter may be employed in such applications to supply an adaptive bias current.
- [0003]Standard implementations of frequency-to-current converters, however, are inadequate to such tasks. Frequency-to-current converters are often implemented by coupling a frequency-to-voltage converter to a voltage-to-current converter. Many conventional frequency-to-voltage and voltage-to-current converters are well known in the art. This combination of circuits, however, is often inadequate for the purposes outlined above; in particular, such combinations are complicated to be embedded in a single integrated circuit, and demand too much power for host applications, such as an ADC converter.
- [0004]As such, there is a need for a frequency-to-current converter which is simple in implementation, and which ensures that a linear relationship is maintained between output current and input clock frequency, for suitability in host applications.
- [0005]The invention comprises a frequency-to-current converter operative to convert a clock frequency to an output current, such that the output current increases linearly with the clock frequency. The frequency-to-current converter is designed to minimize power consumption in hardware applications. Examples of hardware applications which may incorporate the converter of the present invention include digital-to-analog converters (DAC) or analog-to-digital converters (ADC). These applications may be driven by clocks with variable frequencies.
- [0006]In embodiments of the invention, the frequency-to-current converter employs an integrator circuit, which is used to compare an input reference voltage and a current feedback into a sampling capacitor. At steady state, the feedback current is just sufficient to discharge the sampling capacitor to a fixed voltage. Thus, the current only depends on the clock frequency, the sampling capacitor value and the reference voltage. The current is linearly proportional to each of the factors listed above.
- [0007]In many applications employing the frequency-to-current converter—such as, by way of non-limiting example, the analog-to-digital converter—the clock frequency driving the circuit is variable. In one version of the analog-to-digital converter, the clock frequency may vary from 7.5 MHz to 22 MHz. In embodiments of the invention, the variable clock frequency is accommodated by biasing the amplifiers in the frequency-to-current converter with currents proportional to the clock frequency, thereby ensuring that the unity-gain bandwidth of the amplifiers is adaptively adjusted to track the clock frequency, and saving power concurrently.
- [0008]Circuits employed by embodiments of the invention are simple in design, particularly by comparison to standard frequency-to-current converters. In embodiments of the invention, the core of the frequency-to-current conversion circuit includes one opamp, two capacitors, one feedback transistor and a few switches. The elegant design facilitates lower cost, complexity, and power consumption in the host application, and allows the frequency-to-current converter to be resident with the host application on a single integrated circuit. These and other embodiments are described in further detail infra.
- [0009][0009]FIG. 1 schematically illustrates a circuit diagram for a frequency-to-current converter according to embodiments of the invention.
- [0010][0010]FIG. 2 illustrates a plurality of clock phases employed by the frequency-to-current converter according to embodiments of the invention.
- [0011][0011]FIG. 3 illustrates a linear relationship between an input clock frequency of a frequency-to-current converter, and an output current of the frequency-to-current converter according to embodiments of the invention.
- [0012][0012]FIG. 4 schematically illustrates a clock detection circuit used by the frequency-to-current converter in embodiments of the invention.
- [0013]The invention comprises a frequency-to-current converter operative to convert a clock frequency to an output current, such that the output current increases linearly with the clock frequency. In embodiments of the invention, the frequency-to-current converter uses an integrator to compare an input reference voltage and a current feedback into a sampling capacitor. At steady state, the feedback current is just enough to discharge the sampling capacitor to a fixed voltage. Thus, the current only depends on the clock frequency, the sampling capacitor value and the reference voltage.
- [0014]This circuit employed is simple in design, particularly by comparison to standard frequency-to-current converters. In embodiments of the invention, the core of the frequency-to-current conversion circuit includes one opamp, two capacitors, one feedback transistor and a few switches. An output current of the frequency-to-current converter linearly increases with the clock frequency. The simplicity of the design facilitates lower cost, complexity, and power consumption in the host application.
- [0015]The frequency-to-current converter is designed for use in applications such as an analog-to-digital converter, which are intended to operate at low power. As a non-limiting example, the frequency-to-current converter may be used to reduce power consumption in an analog-to-digital converter with a varying clock frequency. An illustrative, non-limiting example of such an analog-to-digital converter is the Max 1195™ ADC, produced by Maxim Integrated Products, Inc. of Sunnyvale, Calif. This ADC comprises a dual, 8-bit, ADC optimized for low power, operating at a 2.7 v to 3.6 v power supply, and which consumes 87 mW, and has a sampling rate of 40 Msps. By providing an adaptive bias current, the frequency-to-current converter ensures that the current in critical analog blocks in the analog-to-digital converter varies proportionally to a sample clock frequency.
- [0016][0016]FIG. 1 schematically illustrates an example of a circuit
**100**used to implement the frequency-to-current converter according to embodiments of the invention. The circuit**100**includes a first opamp op**1****102**, which receives a first reference voltage VREF**1****104**at a positive input. The circuit further includes a sampling capacitor C_{s }**128**, and a feedback capacitor C_{f }**130**. The feedback capacitor C_{f }**130**is operatively coupled to the negative input of a second opamp OP**2****125**. A second reference voltage V_{ref2 }**132**is operatively coupled to the positive input of the second op amp OP**2****125**. The circuit**100**further includes multiple switches, SW**1**, SW**2**, SW**3**, SW**4**, SW**5**, SW**6**, SW**7**, SW**8**, SW**9**, SW**10**, SW**11**, which are operated by clock pulses from a clock generator**116**coupled to a master clock**118**; these clock pulses include phi**1****120**, phi**2****122**, phi**3****124**, NCK, and NCK bar, which are further described herein. The circuit also includes several MOSFET transistors M**1****134**, M**2****138**, M**3****140**. - [0017]In embodiments of the invention, the opamp op
**1****102**is used as a buffer for a first reference voltage, VREF**1****104**. A resistor R_{1 }**106**and a capacitor C_{1 }**108**are specifically used to relax the driving capability of the opamp op**1****102**. A clock detector**110**is used to turn off the frequency-to-current converter when a clock**114**stops. This ensures that the circuit**100**will not be biased at high current. When the clock detector**110**detects that the clock has stopped, the signal NCK**112**drops to a low state, and all switches in the circuit**100**which are controlled by NCK SW**10**SW**9**are subsequently opened. - [0018]A clock generator
**116**is also illustrated in FIG. 1. The clock generator**116**receives input from a master clock MASTER CLK**118**, and produces three timing waveforms, phi**1****120**, phi**2****122**, and phi**3****124**. FIG. 2 illustrates the clock timing of phi**1****202**, phi**2****204**, and phi**3****206**, relative to that of the master clock**200**. Note that in the embodiments shown in FIG. 2, phi**2****204**has a pulse width which is twice that of ph**1****202**and phi**3****206**. The clock pulse phi**3****206**has a period T**208**equal to four periods of the master clock MASTER CLK**200**. These clock pulses operate various switches in the integrator circuit, as elaborated further herein. - [0019]With reference to FIG. 1, a second opamp op
**2****125**, a sampling capacitor C_{s }**128**, and a feedback capacitor C_{f }**130**comprise an integrator. The sampling capacitor C_{s }**128**is coupled via a switch SW**7**to the negative input of the second op amp OP**2****125**. The positive input of the second op amp**125**receives a second reference voltage VREF**2****132**. The feedback capacitor C_{f }**130**forms a feedback to the second op amp OP**2****125**. - [0020]During the clock pulse phi
**1****120**, the sampling capacitor Cs**128**is shorted. During the clock pulse phi**2****122**, the top plate of the sampling capacitor C_{s }**128**is connected to the first reference voltage VREF**1****104**, and the bottom plate of the sampling capacitor C_{s }**128**is discharged by a drain current of a transistor M**1****130**. At the end of the pulse phi**2****122**, the voltage across the sampling capacitor C_{s }**128**is reduced to a voltage V_{x}. During the clock pulse phi**3**, the sampling capacitor C_{s }**128**is connected to the negative input of the opamp op**2****125**. The opamp Op**2****125**compares the voltage V_{5 }with the reference voltage VREF**2****132**and adjusts the output Vout accordingly. At steady state, the voltage V_{x }is identical to the reference voltage VREF**2****132**. The drain current of M**1****134**is given by the relation Equation 1 below:$\begin{array}{cc}I=\frac{2\ue89e\text{\hspace{1em}}\ue89e{C}_{s}\ue8a0\left(\mathrm{VREF1}-\mathrm{VREF2}\right)}{T}=\frac{{C}_{s}\ue8a0\left(\mathrm{VREF1}-\mathrm{VREF2}\right)\ue89e{f}_{\mathrm{master}}}{2}& \mathrm{Equation}\ue89e\text{\hspace{1em}}\ue89e1\end{array}$ - [0021]
- [0022]and f
_{master }is the master clock frequency**200**, as shown in FIG. 2. - [0023]Thus, per the relation given by Equation 1, the current I varies linearly with the frequency of the master clock, f
_{master }**200**. The output voltage Vout**136**is low-pass filtered by a passive filter**150**. The current of M**1****134**is mirrored to M**2****138**. The transistors M**2****138**and M**3****140**form a high impedance current source, which can be used, in embodiments of the invention, to bias other circuitry in the respective application. Since the current is proportional to the clock frequency**200**, the bandwidth (or the g_{m}/C) of the circuit**100**is proportional to the square root of the clock frequency**200**. This implies that the circuit**100**saves power when the clock frequency**200**is low, and speeds up as the clock frequency**200**increases. - [0024]The stability of the frequency-to-current converter
**100**depends on the clock frequency**200**. If the voltage Vin on the top plate of the capacitor C**1****108**is input and the output of the opamp op**2****125**Vout is the output, the transfer function is given by Equation 2 below:$\begin{array}{cc}H\ue8a0\left(Z\right)=\frac{A\ue89e\text{\hspace{1em}}\ue89e{Z}^{-1/4}}{1-\left(1-B\right)\ue89e{Z}^{-1}}& \mathrm{Equation}\ue89e\text{\hspace{1em}}\ue89e2\end{array}$ - [0025]where A=C
_{s}/C_{f}, B=g_{m1}*T/(2*C_{f}). Z^{−1 }corresponds to a delay of period T**208**; in the illustrative example shown in FIG. 2, the period T comprises four periods of the master clock**200**. The factor g_{m1 }represents the transconductance of M**1****134**, as shown in FIG. 1. Since the factor g_{m1 }is proportional to the square root of the current,${g}_{\mathrm{m1}}\ue89e\alpha \ue89e\sqrt{I}\ue89e\text{\hspace{1em}}\ue89e\mathrm{and}\ue89e\text{\hspace{1em}}\ue89eI\ue89e\text{\hspace{1em}}\ue89e\alpha \ue89e\sqrt{f},B\ue89e\text{\hspace{1em}}\ue89e\alpha \ue89e\frac{1}{\sqrt{f}}.$ - [0026]When the frequency
**200**increases, the pole will asymptotically rise to Z=1 but will never reach Z=1. When the frequency**200**decreases and B≧2, the pole will go outside the unity circle. This indicates the existence of a minimum clock frequency, below which the circuit will be unstable. - [0027]Simulations demonstrate that the frequency-to-current converter has a substantially linear relationship between the master clock frequency
**200**and the output current. FIG. 3 illustrates the output current**302**as a function of the master clock frequency**200**. In such embodiments, the non-linearity is within a threshold of 0.5% with a 3× frequency variation. - [0028]To prevent the circuit from generating a large output current when the clock stops, embodiments of the invention also employ a clock detection circuit
**450**. A schematic diagram illustrating the clock detection circuit**450**is shown in FIG. 4. The clock detection circuit**450**includes a plurality of Schmidt triggers**440****442**, which comprise the input to a NOR gate. Capacitors C**1****400**and C**2****402**are charged and discharged periodically by the clock signal phi**2****404**. As the clock frequency decreases, the peak voltages on node A**406**and node B**408**increase. - [0029]In embodiments of the invention, when the frequency is below a threshold frequency, the peak voltage on either node A
**406**or node B**408**is high enough to trigger one of a plurality of Schmidt triggers**440****442**, and the output signal NCK**410**decreases accordingly. The Schmidt triggers**440****442**bistable device used to square-up waveforms with slow rise and fall times; the operation characteristics of the Schmidt triggers**440****442**shall be apparent to those skilled in the art. - [0030]When NCK
**410**is sufficiently low, the opamp op**2****125**of the frequency-to-current converter**100**is tied in a voltage follower configuration, the switch SWI**1****160**is opened, and the output current goes to zero. - [0031]In many of the applications which may employ the frequency-to-current converter—such as, by way of non-limiting example, an Analog-to-Digital converter (ADC)—the clock frequency
**200**may be variable. In such embodiments, by biasing the amplifiers with currents proportional to the clock frequency**200**, the unity-gain bandwidth of the amplifiers is adaptively adjusted to track the clock frequency**200**and to save power concurrently. - [0032]The frequency-to-current converter described herein is particularly well suited to low power applications, of which analog-to-digital converters are one -non-limiting example. The embodiments described herein are for illustrative purposes only; many equivalents and variants will be apparent to those skilled in the art.

Patent Citations

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US5457458 * | Feb 13, 1995 | Oct 10, 1995 | Honeywell Inc. | High resolution analog current-to-frequency converter |

Referenced by

Citing Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US7627072 * | Mar 22, 2006 | Dec 1, 2009 | Cadence Design Systems, Inc. | Frequency-to-current converter |

US20070172013 * | Mar 22, 2006 | Jul 26, 2007 | Cadence Design Systems, Inc. | Frequency-to-current converter |

EP1679575A2 * | May 4, 2005 | Jul 12, 2006 | Fujitsu Limited | Signal detection method, frequency detection method, power consumption control method, signal detecting device, frequency detecting device, power consumption control device and electronic apparatus |

EP1679575A3 * | May 4, 2005 | Oct 1, 2008 | Fujitsu Limited | Signal detection device, frequency detection device, power consumption control device, corresponding methods and electronic apparatus using the same |

Classifications

U.S. Classification | 341/157 |

International Classification | H03D13/00, H03K9/06, H03M1/60 |

Cooperative Classification | H03D13/003, H03K9/06 |

European Classification | H03D13/00B, H03K9/06 |

Legal Events

Date | Code | Event | Description |
---|---|---|---|

Aug 4, 2003 | AS | Assignment | Owner name: MAXIM INTEGRATED PRODUCTS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YANG, YAOHUA;JIANG, RUOXIN;YIN, RUMIN;REEL/FRAME:014349/0662 Effective date: 20030707 |

Mar 19, 2008 | FPAY | Fee payment | Year of fee payment: 4 |

Feb 28, 2012 | FPAY | Fee payment | Year of fee payment: 8 |

Mar 28, 2016 | FPAY | Fee payment | Year of fee payment: 12 |

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