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Publication numberUS20040212025 A1
Publication typeApplication
Application numberUS 10/425,511
Publication dateOct 28, 2004
Filing dateApr 28, 2003
Priority dateApr 28, 2003
Also published asUS7208366, US20050012164
Publication number10425511, 425511, US 2004/0212025 A1, US 2004/212025 A1, US 20040212025 A1, US 20040212025A1, US 2004212025 A1, US 2004212025A1, US-A1-20040212025, US-A1-2004212025, US2004/0212025A1, US2004/212025A1, US20040212025 A1, US20040212025A1, US2004212025 A1, US2004212025A1
InventorsWilman Tsai
Original AssigneeWilman Tsai
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
High k oxide
US 20040212025 A1
Abstract
A technique for producing a thin gate oxide having a relatively high dielectric constant. Embodiments relate to the structure and development of a gate oxide having a thickness of less than 1 nm, having a dielectric constant greater than twenty, and being substantially free of undesired electrical characteristics caused by exposure of the gate oxide to high complementary metal-oxide-semiconductor processing temperatures.
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Claims(14)
1. A semiconductor device comprising:
a dielectric including a second material, which when combined with a first material produces a third material having a dielectric constant greater twenty.
2. The semiconductor device of claim 1 wherein the first and second materials each have a dielectric constant greater than twenty.
3. The semiconductor device of claim 1 wherein one of the first and second materials has a dielectric constant greater than twenty and the other material has a dielectric constant less than twenty.
4. The semiconductor device of claim 2 wherein the first material is chosen from a group consisting of ZrO2 and HfO2.
5. The semiconductor device of claim 4 wherein the second material is chosen from a group consisting of Y2O3, La2O3, and TiO2.
6. The semiconductor device of claim 1 wherein the third material is substantially free of oxygen-deficient defects.
7. The semiconductor device of claim 6 wherein the third material is doped with nitrogen.
8-15. (canceled)
16. An apparatus comprising:
a gate oxide comprising a material chosen from a group consisting of HfO2—TiO2, HfO2—Y2O3, HfO2—La2O3, ZrO2—TiO2, ZrO2—Y2O3, and ZrO2—La2O3.
17. The apparatus of claim 16 wherein the material has a dielectric constant greater than twenty.
18. The apparatus of claim 16 wherein the gate oxide has a dielectric constant greater than twenty.
19. The apparatus of claim 17 wherein the material is substantially free of oxygen-deficient defects.
20. The apparatus of claim 19 wherein the material is doped with nitrogen.
21-27. (canceled)
Description
FIELD

[0001] Embodiments of the invention relate to semiconductor manufacturing. More particularly, embodiment of the invention relate to the formation of a thin, thermally stable, substantially defect-free gate oxide within a complementary metal-oxide-semiconductor (“CMOS”) device.

BACKGROUND

[0002] As CMOS devices continue to decrease in size, the need for smaller gate oxides increases, while the need for a relatively high overall oxide dielectric constant remains. Gate oxides typically consist of a combination of a relatively high k (dielectric constant) dielectric and a relatively moderate k dielectric to produce an overall oxide dielectric constant that is somewhere in between the two. Furthermore, the use of typical oxides, such as zirconium-dioxide (“ZrO2”) and hafnium-dioxide (“HfO2”), by themselves is generally undesirable, because volumetric expansion from thermal anneal cycles in semiconductor processing can result in the formation of defects in the oxide, causing leakage and reliability problems in the transistor.

[0003] Therefore, additives, such as aluminum-trioxide (“Al2O3”), are typically combined with the oxide to help it remain amorphous during exposure to high temperatures in processing. The combination of additives, such as Al2O3, and typical oxides, such as ZrO2 and HfO2, however, can result in an overall effective dielectric constant (k) that is lower than necessary to accommodate thinner oxides (<1 nm) required in modern CMOS processes. Furthermore, additives, such as Al2O3, can possess fixed charge problems as a result of the bonding configuration between the additive and the oxide.

[0004] Typical gate oxides in modern CMOS processes require a dielectric constant of at least twenty in order to support a dielectric thickness of 1 nm or less reliably. Furthermore, gate oxides must be able to withstand deteriorating effects, such as oxygen-deficient defects and thermal instability, caused by exposure to high temperatures during processing.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Embodiments of the invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

[0006]FIG. 1 is a typical CMOS semiconductor device in which at least one embodiment of the invention may be used.

[0007]FIG. 2 is a graph displaying the dielectric constant of an oxide as a function of its TiO2 content, according to one embodiment of the invention.

[0008]FIG. 3 is a flow diagram illustrating a portion of a semiconductor process that may be used in conjunction with one embodiment of the invention.

DETAILED DESCRIPTION

[0009] Embodiments of the invention described herein relate to complementary metal-oxide-semiconductor (“CMOS”) processing. More particularly, embodiments of the invention relate to the creation of a gate oxide being sufficiently thin, possessing appropriate physical reliability, and having a suitable dielectric constant so as to be compatible with modern CMOS processing technology.

[0010]FIG. 1 illustrates a CMOS device in which one embodiment of the invention may be used. The device of FIG. 1 is an inverter, which consists of an n-type transistor 105 and a p-type transistor 110. In each of the transistors is a gate oxide 115, across which an electric field is created when a gate voltage is applied to the gate 125 while the body 120 is biased at a lower potential than the gate.

[0011] The gate oxide in typical modern CMOS devices is less than 1 nm thick, but should also have a dielectric constant greater than twenty in order to support the electric field applied from the gate to the substrate. Because thinner oxides require less dielectric material than thicker oxides, the dielectric constant (k) should be sufficiently high to compensate for the thinner dielectric.

[0012] The n-type dielectric typically consists of ZrO2, whereas the p-type dielectric typically consists of HfO2. In order to achieve the dielectric constant required by a gate oxide of less than 1 nm, high k additives, such as yttrium-trioxide (“Y2O3”), lanthanum-trioxide (“La2O3”), and titanium-dioxide (“TiO2”), are combined with the oxides, ZrO2 and HfO2, in one embodiment of the invention. The combined dielectric constant of ZrO2 or HfO2 and any one of the above high k additives is sufficiently high (>20) to support an electric field across a gate oxide of less than 1 nm. Furthermore, the above additives are substantially free of the fixed charge problems associated with additives, such as Al2O3, when bonded with the oxides.

[0013] Other additives in other embodiments of the invention may be used that can be bonded with ZrO2 and HfO2 without the combination suffering from fixed charge problems while yielding an overall effective dielectric constant necessary to support a particular gate oxide thickness. Furthermore, the particular ratio between one of the above additives and the combined oxide depends upon the dielectric constant that is desired for the application and not limited to the embodiment of the invention discussed above.

[0014]FIG. 2, for example, is a graph illustrating the effective gate oxide's dielectric constant as a function of the percentage of TiO2 combined with HfO2. Advantageously, the relationship between the TiO2 content and the gate oxide dielectric constant is substantially linear when TiO2 is combined with any one of the oxides, ZrO2 or HfO2.

[0015]FIG. 3 is a flow diagram illustrating at least some of the process operations that may be used to carry out one embodiment of the invention. The particular point in the process in which these operations are used is dependent upon the particular process being used. At operation 301, ZrO2 and HfO2 are combined with any one of the additives, Y2O3, La2O3, and TiO2, in order to form a gate oxide having a high crystallization onset and sufficient dielectric constant of at least twenty while not displaying the fixed charge problems associated with some additives, such as Al2O3.

[0016] In order to avoid oxygen-deficient defects that can result in various undesirable electrical properties of the gate oxide when used in a transistor, the combination is cured by exposing the gate oxide to a low oxygen partial pressure anneal at operation 305. The anneal operation exposes the gate oxide to a minimum oxygen ambient atmosphere to cure defects while minimizing interfacial oxide growth, which can happen rapidly at certain atmospheric pressures for high k materials. For the embodiment illustrated in FIG. 3, a partial pressure of <1×10−3 Torr is used in order to avoid undesirable oxide leakage and interfacial oxide growth. The particular anneal pressure and temperature to be used depends upon the particular oxide and additive combination used to form the gate oxide.

[0017] At operation 310, the combination is doped with nitrogen in order to promote thermal stability at high temperatures, such as >1000 C, during CMOS processing. Nitrogen may be introduced to the combination via various process techniques, including plasma nitridation, thermal nitrogen anneal containing an ambient, such as nitrogen-hydroxide (“NH3”), nitrous-oxide (“NO”), nitrous-dioxide (“NO2”), and nitrogen (“N2”), and implantation. The particular doping technique as well as the ambient to be used with the thermal nitrogen anneal is dependent upon the needs of the particular semiconductor process being used.

[0018] While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the spirit and scope of the invention.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7763511Dec 29, 2006Jul 27, 2010Intel CorporationDielectric barrier for nanocrystals
Classifications
U.S. Classification257/411, 257/E21.639
International ClassificationH01L29/51, H01L21/8242, H01L21/469, H01L31/062, H01L27/082, H01L21/8238, H01L29/76, H01L31/11, H01L21/28
Cooperative ClassificationH01L21/823857, H01L21/28185, H01L21/28194, H01L29/518, H01L21/28202, H01L29/517
European ClassificationH01L21/28E2C2C, H01L21/28E2C2D, H01L21/8238J, H01L29/51N, H01L29/51M, H01L21/28E2C2N
Legal Events
DateCodeEventDescription
Aug 11, 2003ASAssignment
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TSAI, WILMAN;REEL/FRAME:014364/0110
Effective date: 20030717