|Publication number||US20040223397 A9|
|Application number||US 10/098,262|
|Publication date||Nov 11, 2004|
|Filing date||Mar 15, 2002|
|Priority date||Aug 31, 1995|
|Also published as||US6445605, US6826071, US20030185080|
|Publication number||098262, 10098262, US 2004/0223397 A9, US 2004/223397 A9, US 20040223397 A9, US 20040223397A9, US 2004223397 A9, US 2004223397A9, US-A9-20040223397, US-A9-2004223397, US2004/0223397A9, US2004/223397A9, US20040223397 A9, US20040223397A9, US2004223397 A9, US2004223397A9|
|Inventors||Patick Mullarkey, Casey Kurth, Jason Graalum, Daryl Habersetzer|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (1), Classifications (10), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
 1. Field of the Invention
 The present invention relates generally to integrated circuit memory products, and, more particularly, to circuitry for programming antifuse bits in such products.
 2. Description of the Prior Art
 Contemporary memory products, e.g. DRAMs, require a high degree of redundancy in order to improve manufacturing yields. Present redundancy techniques in such memory products include providing extra memory array columns and/or extra memory array rows which can be used to replace defective columns and/or rows.
 One application in which antifuses have been used is as nonvolatile programmable memory elements to store logic states which would be used in DRAMs for row and column redundancy implementation. An antifuse is, by definition, a device which functions as an open circuit until programmed to be a permanent short circuit. Antifuses for redundancy implementation are usually constructed in the same manner as the memory cell capacitors in the DRAM array.
 In contemporary memory products, banks of antifuse elements are typically provided, and one such bank is illustrated in FIG. 1. Each such bank includes a plurality, n, of antifuse elements AF0, AF1,. . . AFn, the top plates of which are joined in a common connection to the programming voltage CGND. The bottom plate of each antifuse element AFi, is connected to the drain of a protection transistor PTi. The source of each protection transistor PTi is connected to the drain of selection transistor STi, and the sources of the selection transistors STi are joined in a common connection to ground. The function of each protection transistor PTi is to protect the selection transistor from breakdown between its N + region and gate when the high programming voltage is applied to the drain. The gate of each selection transistor STi is respectively connected to the outputs of NOR gate NGi, the inputs of which are the signal PGM* and the selection signals Ai*. The selection signals Ai* are the complements of the signals Ai and may correspond to the address of a row in the memory product which is to be repaired.
 A particular antifuse element, e.g. AFi, is selected for programming when Ai* and PGM* are both zero volts. In this condition the output of NGi is approximately +5 volts which turns on the selection transistor STi to which it is connected. When this selection occurs, a path exists between the bottom plate of the selected antifuse device and ground. Hence, the selected antifuse device AFi sees a large voltage CGND, e.g. 9 to 12 volts, between its top and bottom plates, which is a sufficient voltage to program the antifuse element. When two or more antifuse elements are to be programmed, the same voltage CGND is applied in parallel to the antifuse elements to be programmed.
 Several shortcomings exist in utilizing the programming technique for antifuse elements such as shown in FIG. 1. First, programming of the antifuse elements is slow using the technique shown in FIG. 1, because each antifuse element has to be programmed one at a time. This is due to the fact that each antifuse element needs a minimum amount of current and voltage to program correctly. If two antifuse elements are enabled for programming at the same time, one most assuredly will breakdown (i.e., become programmed) before the other. The programmed antifuse thus creates a path to ground for the current from CGND, which may impact the voltage and current needed for programming of the other antifuse element. In other words, the voltage across the slower-to-program antifuse element may be reduced to a level that no programming of this element is realized. Additionally, the problem may become acute when one attempts to program three or four antifuse elements in such a bank at once. Accordingly, the prior art solution to these problems was to program the antifuse elements in a bank one at a time, which results in the speed of redundancy repair of a memory product being reduced.
 Once programming of antifuse elements is completed, it is important that the user verify that those elements which are to be programmed are in fact programmed. Also, it is important that the user verify that antifuse elements which are not to be programmed are functioning properly. In the latter regard, unprogrammed antifuse devices may leak and appear to be programmed devices. No such verification circuitry has heretofore been available.
 In accordance with the present invention, improved circuitry is provided for programming antifuse devices. With the present invention, the speed of programming antifuse elements is enhanced, because all of the antifuse elements in a bank may be programmed simultaneously.
 In one embodiment of the present invention, the same programming voltage CGND is still applied in parallel across all antifuse elements to be programmed by enabling this respective selection transistors. However, in this embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current from CGND through the antifuse element once it is programmed. With this feedback circuitry, a programmed antifuse element can no longer affect the voltage across and current through antifuse elements which are slower to program.
 In another embodiment of the present invention, circuitry is provided which generates a separate programming voltage pulse for each antifuse element in a bank which is selected for programming. In this embodiment, the same voltage source is not applied in parallel across all of the antifuse elements that are to be programmed, and the programming voltage across and current through an antifuse element that is to be programmed is unaffected by other antifuse elements which may have programmed more quickly.
 In accordance with the present invention, method and apparatus are provided to verify that an antifuse element is programmed properly. The method and apparatus also verify if a nonprogrammed antifuse element is functioning properly.
 In the accompanying drawings:
FIG. 1 is a schematic diagram which illustrates a prior art technique for programming antifuse elements.
FIG. 2 is a schematic diagram which illustrates one embodiment of circuitry in accordance with the present invention for programming antifuse elements.
FIG. 3 is a schematic diagram in block diagram form of another embodiment of circuitry in accordance with the present invention for programming antifuse elements.
FIG. 3A is a schematic diagram in block diagram form which depicts circuitry for decoding inputs to select one of the banks of antifuse elements shown in FIG. 3.
FIG. 4 is a schematic diagram depicting elements in a bank of antifuse elements shown in FIG. 3.
FIG. 5 is a schematic diagram of one embodiment of each driver circuit of FIG. 3.
FIG. 6 is a schematic diagram of a second embodiment of each driver circuit of FIG. 3.
FIG. 7 is a schematic diagram of circuitry that may be used to ascertain that antifuse elements are functioning properly, once the programming process is completed.
 It will be appreciated that the present invention may take many forms and embodiments. Some embodiments of the invention are described so as to give an understanding of the invention. It is not intended that the limited embodiments described herein should affect the scope of the present invention.
 With reference to FIG. 2, an embodiment of the present invention is illustrated. In this embodiment the same programming voltage CGND is applied in parallel across all antifuse elements in a bank which are to be programmed in integrated circuit 200. Each bank of elements contains a plurality, n, of antifuse elements, and each of the n antifuse elements in each bank has associated with it circuitry as illustrated in FIG. 2.
 In FIG. 2, a protection transistor PTi is provided, and the function of this transistor is identical to the function of transistor PTi in FIG. 1. Also, in FIG. 2 the gate of the selection transistor STi for antifuse element AFi is connected to the output of three-input NOR gate 201. One input to NOR gate 201 is PGM* which is the complement of the signal PGM, which is a logic 1, e.g. +5 volts, when programming of antifuse elements is to occur. Another input to NOR gate 201 is connected to Ai*, which is the complement of Ai, for i =1, . . . n. The signals Ai, i =1 . . . n, may, for example, be provided on the address inputs to the memory on the falling edge of CAS and additionally may comprise the n least significant bits of the address of the row of the memory to be repaired. When any Ai is a logic 1, e.g. +5 volts, antifuse element AFi is to be programmed. The third input to NOR gate 201 is connected to node TNi. Also connected to node TNi is the drain of transistor 202.
 In operation, each node TNi for i =0, 1 . . . n is precharged to zero volts just prior to the beginning of a programming operation when the signal PGMPCHRG enables transistor 202 to connect node TNi to ground. When programming is to occur, the output of NOR gate 201 enables selection transistor STi for each antifuse element to be programmed. The enablement of transistor STi causes the voltage CGND to appear across antifuse element AFi, and this voltage is sufficient to cause programming of antifuse element AFi.
 When programming of antifuse element AFi occurs, current flows through antifuse element AFi, and transistors PTi and STi. The voltage developed across the serial combination of transistors PTi and STi from this current causes the voltage at node TNi to rise to a positive level which is sufficient to be detected as a logic 1. This positive voltage at node TNi is feedback to the third input of NOR gate 201. At this time, the output of NOR gate 201 falls zero volts, which disables transistor STi, stopping the flow of current through programmed antifuse element AFi. Thus, through the use of the feedback circuit shown in FIG. 2, an antifuse element AFi stops conducting current once it is programmed, and the full programming voltage and current are available for other antifuse elements in the bank which are slower to program.
 Referring now to FIG. 3, a portion of another embodiment of the present invention is illustrated. Integrated circuit memory 300 includes a plurality, m, of banks of antifuse elements, designated BANK0, BANKl,. . . . BANKm in FIG. 3. Each bank contains a plurality, n, of antifuse elements. A separate driver circuit DRVRi (i =0 to n) is provided to supply separate programming pulses to each antifuse elements in each bank, as described in more detail below.
 Referring to FIG. 4, the circuit components included in each bank of antifuse elements of FIG. 3 is shown. Each antifuse element AFi in a bank is connected through a protection transistor PTi to the drain of a selection transistors STi, where i=0, 1, . . . n. Protection transistor PTi in FIG. 4 performs the same function as protection transistor PTi in FIGS. 1 and 2.
 Only one bank of antifuse elements in FIG. 3 is selected for programming at any given time. A bank select signal BSELj, j =1 . . . m is connected to all of the gates of the bank select transistors STi in a given bank as shown in FIG. 4. The bank select signal BSELj may be generated, for example, by decoding the most significant bits of the row address to be repaired. These most significant bits are available to the memory product on the falling edge of the RAS* signal as shown in FIG. 3A. The circuitry to make this bank selection is decoder 301 as shown in FIG. 3A.
 In accordance with the present invention, each driver DRVRi, t =0,. . . n, of FIG. 3 provides a separate programming pulse CGNDi to an antifuse element in the bank that is selected for programming. Referring to FIG. 5, one embodiment of each driver circuit DRVRi for i =0, . . . n of FIG. 3 is shown. Each such driver circuit comprises NAND gate 501, inverters 502-04, capacitor 505, P-channel transistors 506 and 507 and N-channel transistors 508 and 509. As illustrated, one input to NAND gate 501 is connected to the selection signal Ai for the antifuse AFi with which it is associated. If an antifuse element AFi is to be programmed, the Ai signal associated with it is a logic 1. As noted above, the Ai signals may correspond to n least most significant bits of the address of the row in a memory to be repaired.
 Another input to NAND gate 501 is connected to the signal PGM, which is normally 0 volts and which is brought to a logic one level, e.g. +5 volts, when antifuse elements are to be programmed. The logical value of the signal at the output of inverter 504 is the complement of the signal PGM.
 The circuitry of FIG. 5 operates as follows to generate a programming pulse CGNDi for each antifuse element AFi, i =0, . . . n, to be programmed. When the signal PGM is brought to a logic 1 value, e.g. +5 volts, to begin programming of antifuses, the output of inverter 504 is a logic 1 based on the logic zero state of PGM before programming began. The output of NAND gate 501 becomes a logic 0 (i.e., 0 volts) for each AF, which is to be programmed. The output of NAND gate 501 is an input to level translator 510, which includes p-channel transistors 506 and 507 and N-channel transistors 508 and 509 all connected as shown. As shown in FIG. 5, the programming voltage CGND is also an input to level translator 510.
 The output of NAND gate 501 is a logic zero when programming of its associated antifuse is to occur. At this time transistor 509 is disabled and p-channel transistor 506 is enabled since the voltage on its gate is zero volts. At this time, a high voltage programming signal CGNDi is generated for each antifuse AFi to be programmed.
 The duration of each programming signal CGNDi is determined by the width of the logic zero pulse at the output of its associated NAND gate 501, which in turn is determined by the propagation delay of the combination of inverters 502-04 and capacitor 505. When the duration of the logic zero pulse at the output of NAND gate 501 is completed, (i.e., when the output of NAND gate 501 rises from a logic 0 to a logic 1), transistor 509 is enabled which pulls each programming pulse CGNDi to zero volts. At this time, p-channel transistor 507 is enabled, and the full programming voltage CGND is applied to the gate of p-channel transistor 506, and this programming voltage ensures that transistor 506 is disabled at the end of the programming pulse CGNDi.
 If any of the antifuses AFi in the selected bank is programmed before the others in the selected bank, the programming of that antifuse element cannot adversely affect the programming of the other elements. Since the programming pulses CGNDi that are provided by drivers DRVRi are independent of one another, all antifuse elements that are to be programmed will be provided a sufficient voltage to effect programming, even though some of the antifuse elements in the selected bank are slower to program than others.
 The circuitry of FIG. 5 is acceptable for use in programming antifuse elements that require only a fairly short duration pulse for programming. As the duration of the programming signal CGNDi for programming to occur increases, the number of delay elements such as inverters 502-04 and capacitor 505 also increases. Hence, for those antifuse elements requiring a longer duration pulse for programming, it has been found that the circuitry of FIG. 6 is preferable to that shown in FIG. 5.
 Referring to FIG. 6, a preferred embodiment of the driver circuits DRVRi of FIG. 3 is shown. This embodiment comprises transistors 602-604 each of which is connected as a diode, inverters 605-07, capacitor 608, NOR gate 609, NOR gates 610 and 611, NAND gate 612 and NOR gate 613, all connected as shown in FIG. 6. This embodiment also includes level translator 620, which is identical to level translator 510 in FIG. 5. Transistors 602-04, inverters 605-07, capacitor 608 and NOR gate 609 form a sense circuit for sensing when an antifuse has been programmed. NOR gates 610 and 611 are cross-coupled to form a latch having an output Q.
 Prior to beginning an operation to program antifuses, the RESET signal is generated, which forces the output Q of NOR gate 610 to a logic 1. For each antifuse element AFi to be programmed, Ai* will be a logic zero. When programming is to begin, PGM* is a logic zero, which results in the output of NAND 612 being a logic zero. Transistor 623 is disabled, and p-channel transistor 621 is enabled, since the voltage on its gate is zero volts. A high voltage programming signal CGNDi is thus generated. The magnitude of CGNDi is about 9 to 12 volts, which is sufficient to effect programming of antifuse AFi.
 Before antifuse AFi is programmed, the voltage drop across transistors 602-604 is such that the voltage at the output of transistor 604 is slightly higher than the minimum voltage that can be recognized as a logic 1. For example, when CGNDi is the high programming voltage, the voltage on the output of transistor 604 may be about +3 volts.
 When the selected antifuse element AFi does program, the magnitude of CGNDi drops, which results in the voltage at the output of transistor 604 decreasing to a level which is lower than the maximum voltage level that can be recognized as a logic zero. The falling edge of the signal which is at the output of transistor 604. is detected by the sense circuit comprising inverters 605 - 607, capacitor 608 and NOR gate 609, with the output of NOR gate 609 pulsing to a logic 1 upon detection of that falling edge. This logic 1 pulse forces the output Q of the latch composed of NOR gates 610 and 611 to a logic zero and the output of NAND 612 to a logic 1. At this time, transistor 623 is enabled, and the programming signal CGNDi is pulled to zero volts. P-channel transistor 624 is thus enabled, and the full programming voltage CGND appears on the gate of p-channel transistor 621, thereby assuring that p-channel transistor 621 is disabled once programming of the antifuse AFi has been effected.
 In this embodiment, the programming pulses CGNDi that are provided by drivers DRVRi are also independent of one another, and all antifuse devices that are to be programmed will be provided a sufficient voltage to effect programming, even though some of the antifuse elements in the selected bank are slower to program than others.
 The circuitry 725 of FIG. 7 has been used in prior memories of Micron. In such memories, the antifuses would be read and constantly compared to the address values supplied to the memory. If a match occurred, a match signal was triggered which caused the real row or column at that address to be replaced with a redundant row or column. However, this operation was not apparent to the user, so a test mode was designed so that when the memory was in this test mode and a match occurred, a signal would be triggered to activate circuitry attached to the output of the integrated circuit memory. The test mode circuitry in the prior memories was developed to check if a particular address had already been repaired prior to programming an antifuse, and was not developed to ensure that an antifuse was programmed correctly.
 In accordance with the present invention, verification circuitry is provided for verifying that: (a) an unprogrammed antifuse does not have a resistive short, i.e., is not leaky; and (2) a programmed antifuse is programmed properly. This useful result is realized in a preferred embodiment combining P-channel transistor 704 with circuitry 725 as illustrated in FIG. 7. This verification circuitry is provided for and connected to each antifuse AFi.
 With reference still to FIG. 7, the source of transistor 700, which is designated 708, is connected to one side of antifuse element AFi, as shown. The other side of the antifuse element AFi is connected to the signal CGND, if the programming circuitry of FIG. 2 is used, or to CGNDi, if the programming circuitry as illustrated in FIGS. 3-6 is utilized for programming. During the verification process, the signals CGND and CGNDi are at zero volts.
 During the programming operation, transistor 700 was disabled. However, once the programming operation is completed transistor 700 is enabled by the signal in FUSEISO*. In series with transistor 700 is transistor 701 whose gate is driven by the signal DVC2E. The magnitude of the signal DVC2E is approximately 1.5 to 2 volts which enables transistor 701 to act as a current limiter. Thus, during the verification process, one side of antifuse AFi is connected to the node constituting the input to inverter 706. Each transistor 700, 701 has a width/length of 10/2.
 The verification circuitry of FIGS. 7 also includes P-channel transistors 702, 703, 704, and 705, all connected as shown in FIG. 7. P-Channel transistor 702 is enabled during the verification process by the signal FUSERD*. The width/length ratio of transistor 703 is preferably 5/25 and the width/length ratio of transistor 704 is preferably 5/50.
 In operation, the verification circuitry of FIG. 7 operates as follows to detect an unprogrammed antifuse that has a resistive short, i.e., to detect an antifuse which is leaky. In this mode of operation, transistor 704 is enabled into a conduction state using the signal B. At this time transistor 703 is turned off. The voltage on the node which is the input to inverter 706 will attempt to charge via transistors 704 and 702. If the unprogrammed antifuse AFi i that is being tested is functioning properly, the voltage on the node which is the input to inverter 706 will charge to Vcc. The output of inverter 706 under this condition is zero volts, which turns on transistor 705 thereby improving the charge path to the input to inverter 706. In this situation, the signal F is a logic 1, while the signal F* is a logic 0. However, if an unprogrammed antifuse element is leaky, it will have a resistance of less than 86 Kohms, and the voltage on the node at the input to inverter 706 will not be charged to +5 volts. This results in the signal F being a logic 0, while the signal F* is a logic 1. This state of the signals F and F* thus indicates that an unprogrammed antifuse is leaky.
 To verify that a programmed antifuse element is correctly programmed, both transistors 703 and 704 are enabled by signals A and B to attempt to charge the voltage at the input to inverter 706. The charge presented to the input to inverter 706 from enabling both transistors 703 and 704 is greater than the charge at the input to inverter 706 from just enabling transistor 704.
 If the antifuse element AFi is properly programmed, its resistance will be less than 27 Kohms, which is sufficiently low to prevent the voltage on the node at the input to inverter 706 from being charged to +5 volts. In this situation, the signal F is a logic 0, while the signal F* is a logic 1. On the other hand, if the antifuse element AFi did not program properly, it will have a resistance greater than 27 Kohms, and the voltage on the node at the input to inverter 706 will charge to a level that is detected as a logic 1. Hence, in this situation, the signal F will be a logic 1 and the signal F* will be a logic 0. This state of the signals F and F* thus indicate that an antifuse which was to be programmed did not program properly.
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7424346||Dec 15, 2005||Sep 9, 2008||Mks Instruments, Inc.||Apparatus and method for pressure fluctuation insensitive mass flow control|
|International Classification||G01F25/00, G01F1/86, G01F1/696, G01F5/00, G01F1/66, G01F1/684, G11C17/18|
|Jan 18, 2007||AS||Assignment|
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MULLARKEY, PATRICK J.;KURTH, CASEY R.;GRAALUM, JASON;ANDOTHERS;REEL/FRAME:018767/0826
Effective date: 19950829
|May 16, 2008||FPAY||Fee payment|
Year of fee payment: 4
|May 2, 2012||FPAY||Fee payment|
Year of fee payment: 8