BACKGROUND OF THE INVENTION

[0001]
1. Field of the Invention

[0002]
The present invention relates generally to the design of integrated circuits. More specifically, but without limitation thereto, the present invention relates to the routing of clock trees in an integrated circuit design to avoid injected crosstalk delay.

[0003]
2. Description of the Prior Art

[0004]
Clock signals are typically used in integrated circuit designs to control the timing of various functions performed by the integrated circuit. The clock signals are distributed to various locations in the integrated circuit by path structures called clock trees. The design and routing of clock trees in the integrated circuit design impacts all aspects of the integrated circuit design. Variations in arrival time of the clock signal may decrease performance of the integrated circuit and may even result in a functional failure due to a setup or hold time violation.
SUMMARY OF THE INVENTION

[0005]
In one aspect of the present invention, a method of protecting a net of an integrated circuit against injected crosstalk delay includes steps of:

[0006]
(a) receiving a synthesized signal path structure and a value of maximum allowable injected crosstalk delay for a selected net in the signal path structure;

[0007]
(b) analyzing the signal path structure to calculate a skew correction and a net ramptime for the selected net;

[0008]
(c) estimating an injected crosstalk delay of the selected net from a net aggressor; and

[0009]
(d) selecting a crosstalk protection scheme for the selected net to minimize chip area of the integrated circuit while ensuring that the injected crosstalk delay of the selected net does not exceed the value of maximum allowable injected crosstalk delay.

[0010]
In another aspect of the present invention, a computer program product for optimizing a bond out design includes:

[0011]
a medium for embodying a computer program for input to a computer; and

[0012]
a computer program embodied in the medium for causing the computer to perform steps of:

[0013]
(a) receiving a synthesized signal path structure and a value of maximum allowable injected crosstalk delay for a selected net in the signal path structure;

[0014]
(b) analyzing the signal path structure to calculate a skew correction and a net ramptime for the selected net;

[0015]
(c) estimating an injected crosstalk delay of the selected net from a net aggressor; and

[0016]
(d) selecting a crosstalk protection scheme for the selected net to minimize chip area of the integrated circuit while ensuring that the injected crosstalk delay of the selected net does not exceed the value of maximum allowable injected crosstalk delay.
BRIEF DESCRIPTION OF THE DRAWINGS

[0017]
The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements throughout the several views of the drawings, and in which:

[0018]
[0018]FIG. 1A illustrates an unprotected clock net of the prior art with minimal spacing between net aggressors;

[0019]
[0019]FIG. 1B illustrates a typical plot of incremental injected crosstalk delay as a function of the clock net length;

[0020]
[0020]FIG. 2 illustrates a grid spacing crosstalk protection scheme of the prior art;

[0021]
[0021]FIG. 3 illustrates a metal shielding crosstalk protection scheme of the prior art;

[0022]
[0022]FIG. 4 illustrates a partial grid spacing crosstalk protection scheme according to an embodiment of the present invention;

[0023]
[0023]FIG. 5 illustrates a partial metal shielding crosstalk protection scheme according to an embodiment of the present invention;

[0024]
[0024]FIG. 6 illustrates an alternative partial grid spacing crosstalk protection scheme according to an embodiment of the present invention;

[0025]
[0025]FIG. 7 illustrates a mixed partial crosstalk protection scheme according to an embodiment of the present invention with both partial grid spacing and partial metal shielding;

[0026]
[0026]FIG. 8 illustrates a flow chart of a method of protecting a net of an integrated circuit against injected crosstalk delay according to an embodiment of the present invention;

[0027]
[0027]FIG. 9A illustrates a illustrates a typical clock tree of the prior art;

[0028]
[0028]FIG. 10 illustrates a flow chart of a method of selecting an optimal partial protection scheme according to an embodiment of the present invention;

[0029]
[0029]FIG. 10A illustrates a histogram of a typical distribution of clock nets having n path segments used to calculate the probability Q_{n }according to an embodiment of the present invention;

[0030]
[0030]FIG. 10B illustrates the geometrical probability of overlap between a clock transition and the timing window of a net aggressor according to an embodiment of the present invention;

[0031]
[0031]FIG. 11 illustrates a plot of a probability mass function as a function of wire density along a path segment used to calculate P_{D>90% }according to an embodiment of the present invention;

[0032]
[0032]FIG. 12A illustrates a plot of P_{D>90% }as a function of average design wire density calculated from FIG. 11;

[0033]
[0033]FIG. 12B illustrates a plot of the relaxation crosstalk multiplier M_{xt }(n) as a function of the number of path segments n in the selected clock net according to an embodiment of the present invention;

[0034]
[0034]FIG. 13 illustrates a flow chart of a method of calculating an optimum protected path length for a selected clock net according to an embodiment of the present invention; and

[0035]
[0035]FIGS. 14A and 14B illustrates a flow chart for an intelligent engine according to an embodiment of the present invention.

[0036]
Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to point out distinctive features in the illustrated embodiments of the present invention.
DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

[0037]
One of the most significant factors that may affect the clock arrival time, or propagation delay, in a clock tree of an integrated circuit design is the crosstalk generated from signals carried in wires adjacent to the clock net. The crosstalk may inject an incremental crosstalk delay (positive or negative) in a clock net. In previous design flows, the clock tree implementation is designed and a crosstalk analysis is performed afterward to determine whether the crosstalk results in any timing violations in the clock net. If timing violations are found, the clock tree design is modified, and another crosstalk analysis is performed. This cycle is iterated until all timing violations are removed, which may be an extremely timeconsuming process.

[0038]
An intelligent engine for protection against injected crosstalk delay of the present invention anticipates timing violations injected by crosstalk signals so that the clock tree design may be completed in a single pass without requiring a crosstalk analysis. Crosstalk analysis may be an extremely timeconsuming task in itself. Although a clock tree is used herein to illustrate an example of how an intelligent engine for protection against injected crosstalk delay of the present invention may be used, other signal path structures may be used to practice the present invention within the scope of the appended claims.

[0039]
In one aspect of the present invention, a method of protecting a net of an integrated circuit against injected crosstalk delay includes steps of: (a) receiving a synthesized signal path structure and a value of maximum allowable injected crosstalk delay for a selected net in the signal path structure; (b) analyzing the signal path structure to calculate a skew correction and a net ramptime for the selected net; (c) estimating an injected crosstalk delay of the selected net from a net aggressor; and (d) selecting a crosstalk protection scheme for the selected net to minimize chip area of the integrated circuit while ensuring that the injected crosstalk delay of the selected net does not exceed the value of maximum allowable injected crosstalk delay.

[0040]
One approach to ensuring adequate protection against injected crosstalk in a clock tree or other signal path structure is to provide a spacing or a shield around the clock net after constructing the clock tree. However, this approach may require a significant amount of chip area in the integrated circuit design and may not be necessary for all the clock nets of the clock tree in terms of providing adequate protection. For example, shorter nets of the clock tree may not be subject to levels of injected crosstalk delay that exceed the maximum allowable injected crosstalk delay value of the shorter nets. Because there may be several hundred thousand flipflops and associated wiring in a clock tree, the chip area required to provide complete protection for the entire clock tree may require a chip area that is relatively large compared to the chip area required to perform the functions of the integrated circuit design.

[0041]
In a method of protecting a net of an integrated circuit against injected crosstalk delay of the present invention, adequate clock protection against injected crosstalk delay is provided while advantageously minimizing the chip area of the integrated circuit. Also, clock skew is reduced and ramptime is improved for long nets. The minimization of chip area, reduction of clock skew, and improved ramptime for long nets is achieved by an intelligent engine that determines the amount of protection required for each clock net in the clock tree to ensure that the injected crosstalk delay in each net does not exceed a maximum allowable injected crosstalk delay value in the integrated circuit design. By affording the needed amount of partial protection for each clock net, the design goals of the integrated circuit may be satisfied while minimizing the chip area. The intelligent engine of the present invention may be incorporated, for example, into software tools used in commercially available integrated circuit design platforms.

[0042]
Crosstalk delay is injected into a clock net from adjacent wires in other signal nets, called net aggressors. Depending on the waveform of the signal in the net aggressors, the injected crosstalk delay may be either positive or negative. Various protection schemes for avoiding injected crosstalk delay are described as follows.

[0043]
[0043]FIG. 1A illustrates an unprotected clock net of the prior art with minimal spacing between net aggressors. Shown in FIG. 1A are a clock net 102 having three net segments 104, 106 and 108, a routing grid 110, net aggressors 112 and 114, a clock buffer 116, and a clock destination 118.

[0044]
In FIG. 1A, the clock net 102 extends from the clock buffer 116 to the clock destination 118 along the three net segments 104, 106 and 108 that follow the routing grid 110. Each change in direction of the clock net 102 from vertical to horizontal or the reverse defines a new net segment. In this example, there are three net segments.

[0045]
The net aggressors 112 and 114 are routed along the nearest available grid lines next to the clock net 102. While this arrangement results in minimum chip area, it also results in maximum injected crosstalk delay, which may result in setup time or hold timing violations. The value of injected crosstalk delay above which timing violations may occur in a selected clock net is referred to herein as the maximum allowable injected crosstalk delay value. Because the timing violations may result in a malfunction of the integrated circuit, a crosstalk analysis generally performed to detect timing violations. If a timing violation is found, the clock net routing is rerouted and another crosstalk analysis is performed, and so on, until a routing of the clock net is found that does not result in a timing violation. In some cases, no solution may be found, and an even more timeconsuming circuit redesign must be performed.

[0046]
[0046]FIG. 1B illustrates a typical plot of incremental injected crosstalk delay as a function of the clock net length. Shown in FIG. 1B are a plot 152 for an unprotected clock net, a plot 154 for a clock net with one additional grid spacing, and a plot 154 for a shielded clock net. In this example, the incremental crosstalk delay dD is equal to 25 picoseconds when the length of an unprotected clock net reaches 1.05 millimeters. At a net length of about 2 millimeters, the shielded clock net has an incremental delay of about 15 picoseconds, the clock net with grid spacing has an incremental delay of about 55 picoseconds, and the unprotected clock net has an incremental delay of about 145 picoseconds. Plots such as that illustrated in FIG. 1B may be generated from empirical data and used to construct a library of precharacterized crosstalk protection parameters.

[0047]
[0047]FIG. 2 illustrates a grid spacing crosstalk protection scheme of the prior art. Shown in FIG. 2 are a clock net 102 having three net segments 104, 106 and 108, a routing grid 110, net aggressors 112 and 114, a clock buffer 116, and a clock destination 118.

[0048]
In FIG. 2, the clock net 102 is spaced apart from the net aggressors 112 and 114 by one grid unit spacing Δ_{S}. The spacing Δ_{S }between the clock net 102 and the net aggressor nets 112 and 114 may also be multiples of a grid unit. While this arrangement reduces injected crosstalk delay in the clock net 102 from the net aggressors 112 and 114, the chip area is increased significantly.

[0049]
[0049]FIG. 3 illustrates a metal shielding crosstalk protection scheme of the prior art. Shown in FIG. 3 are a clock net 102 having three net segments 104, 106 and 108, a routing grid 110, net aggressors 112 and 114, a clock buffer 116, a clock destination 118, a power wire 120, and a ground wire 122.

[0050]
In FIG. 3, the power wire 120 and the ground wire 122 provide a lowimpedance path to ground for the crosstalk emitted from the net aggressors 112 and 114. This arrangement provides even greater attenuation of injected crosstalk in the clock net 102 than the grid spacing protection scheme of FIG. 2 for the same increase in chip area, however, the capacitance between the clock net and the power wire 120 and between the clock net 102 and the ground wire 122 results in increased clock skew and ramptime.

[0051]
[0051]FIG. 4 illustrates a partial grid spacing crosstalk protection scheme according to an embodiment of the present invention. Shown in FIG. 4 are a clock net 102 having three net segments 104, 106 and 108, a routing grid 110, net aggressors 112 and 114, a clock buffer 116, and a clock destination 118.

[0052]
In FIG. 4, the clock net 102 is partially protected by a length L_{p }of the total length L_{tot }of the first net segment 104 of the clock net 102, while the remaining length L_{up }of the total length L_{tot }including net segments 106 and 108 of the clock net 102 is unprotected. The degree of protection may be adjusted by adjusting the protected length L_{p }of the clock net 102.

[0053]
[0053]FIG. 5 illustrates a partial metal shielding crosstalk protection scheme according to an embodiment of the present invention. Shown in FIG. 5 are a clock net 102 having three net segments 104, 106 and 108, a routing grid 110, net aggressors 112 and 114, a clock buffer 116, a clock destination 118, a power wire 120, and a ground wire 122.

[0054]
In FIG. 5, the clock net 102 is partially protected by a length L_{p }of the total length L_{tot }of the first net segment 104 of the clock net 102, while the remaining length L_{up }of the total length L_{tot }of the clock net 102 including net segments 106 and 108 is unprotected. The degree of protection may be adjusted by adjusting the protected length L_{p }of the clock net 102. By only using the degree of protection required to satisfy the maximum allowable injected crosstalk delay for the clock net 102, the increase in clock skew and ramptime may be minimized.

[0055]
[0055]FIG. 6 illustrates an alternative partial grid spacing crosstalk protection scheme according to an embodiment of the present invention. Shown in FIG. 6 are a clock net 102 having three net segments 104, 106 and 108, a routing grid 110, net aggressors 112 and 114, a clock buffer 116, and a clock destination 118.

[0056]
In FIG. 6, the clock net 102 is partially protected by a length L_{p }of the total length L_{tot }of the last net segment 108 of the clock net 102. In the same manner, the protected length L_{p }may be placed in the middle net segment 106. By placing the protected length L_{p }in the net segment or segments where the greatest amount of injected crosstalk delay may occur, the amount of protection required for the clock net 102 may be significantly reduced without exceeding the maximum allowable injected crosstalk delay.

[0057]
[0057]FIG. 7 illustrates a mixed partial crosstalk protection scheme according to an embodiment of the present invention with both partial grid spacing and partial metal shielding. Shown in FIG. 7 are a clock net 102 having three net segments 104, 106 and 108, a routing grid 110, net aggressors 112 and 114, a clock buffer 116, a clock destination 118, a power wire 120, and a ground wire 122.

[0058]
In FIG. 7, metal shielding is used over a length L_{m }in the first segment 104 of the clock net 102, and grid spacing protection is used over a length L_{s }in the last segment 108 of the clock net 102.

[0059]
In a general partial crosstalk protection scheme according to an embodiment of the present invention, each net segment or portion of a net segment of the clock net 102 may be unprotected or protected by one of the types of partial crosstalk protection schemes described with reference to FIGS. 47.

[0060]
The problem of finding the optimum partial crosstalk protection is a complex one. For example, more crosstalk protection requires more chip area, improved crosstalk protection using metal shielding increases net capacitance that results in greater ramptime, and so on.

[0061]
In one aspect of the present invention, a method of protecting a net of an integrated circuit against injected crosstalk delay includes steps of: (a) receiving a synthesized signal path structure and a value of maximum allowable injected crosstalk delay for a selected net in the signal path structure; (b) analyzing the signal path structure to calculate a skew correction and a net ramptime for the selected net; (c) estimating an injected crosstalk delay of the selected net from a net aggressor; and (d) selecting a crosstalk protection scheme for the selected net to minimize chip area of the integrated circuit while ensuring that the injected crosstalk delay of the selected net does not exceed the value of maximum allowable injected crosstalk delay.

[0062]
Given a design for a clock tree or other signal path structure and the maximum allowable injected crosstalk delay value for each clock net in the clock tree or net in the signal path structure, optimum partial crosstalk protection may be found to satisfy the following conditions:

[0063]
(1) the injected crosstalk delay for any clock net under worst case conditions does not exceed the maximum allowable injected crosstalk delay;

[0064]
(2) the chip area required to provide the partial crosstalk protection is a minimum;

[0065]
(3) the partial crosstalk protection decreases the amount of clock skew correction required; and

[0066]
(4) signal ramptime is improved in the longest clock nets of the clock tree.

[0067]
The worst case conditions include the combination of net aggressors and signal switching within the net aggressors, however, the worst case conditions may be limited to those that may occur in the clock net during approximately two years of functioning to avoid increasing the chip cost unnecessarily. The worst case conditions for a selected clock net may then be expressed as a function of the number of net segments, the net length, and the net aggressor.

[0068]
[0068]FIG. 8 illustrates a flow chart 800 of a method of protecting a net of an integrated circuit against injected crosstalk delay according to an embodiment of the present invention.

[0069]
Step 802 is the entry point of the flow chart 800.

[0070]
In step 804, a clock tree synthesized according to wellknown techniques is received as input along with a maximum allowable injected crosstalk delay for each net in the clock tree.

[0071]
In step 806, the clock tree is analyzed. The functions of the clock tree analyzer are described below in detail.

[0072]
In step 808, a first clock net in the clock tree is selected.

[0073]
In step 810, an optimum crosstalk protection scheme for the selected clock net is selected from a library of precharacterized crosstalk protection parameters according to the clock tree analysis. The library of precharacterized crosstalk protection parameters and the selection process are described below in detail.

[0074]
In step 812, if an optimum crosstalk protection scheme for every clock net in the clock tree has been selected, control is transferred to step 816, otherwise control is transferred to step 814.

[0075]
In step 814, the next clock net in the clock tree is selected, and control is transferred to step 810.

[0076]
Step 816 is the exit point of the flow chart 800.

[0077]
For each selected clock net in the clock tree, the clock analyzer calculates a clock skew correction, a clock net length, a clock net wire segment number, a clock net fanout, and an estimate of clock net ramptime as follows.

[0078]
[0078]FIG. 9A illustrates a typical clock tree 900 of the prior art. Shown in FIG. 9A are a clock root driver 902, clock buffers 904, a clock net 906, clock destination flipflops 908, and path segments (s,t) 910.

[0079]
The clock tree 900 may be synthesized according to wellknown techniques and received as input as described in step 802. The clock root driver 902 buffers the clock signal to the top level of clock buffers 904 in the clock tree 900. The clock net 906 includes a set of path segments (s,t) 910 between each level of clock buffers 904 from the top level down to one of the destination flipflops 908. In the set of path segments (s,t) 910, each output of a clock buffer 904 is represented by s. The corresponding input of the clock buffer 904 on the next lower level to which the output of the clock buffer 904 on the higher level is connected is represented by t.

[0080]
The synthesized clock tree is received as input and is analyzed by a clock tree analyzer as follows. The clock skew correction dS(s, t) is defined as the desired change in clock delay for each path segment (s,t). If dS(s, t) is equal to zero, then no correction is desired or needed. If dS(s, t) is greater than zero, then increasing the delay in the corresponding path segment (s,t) by dS(s, t) is desirable. If dS(s,t) is less than zero, then decreasing the delay in the corresponding path segment (s,t) by dS(s, t) is desirable. If dS(s,t) is equal to an interval [dS1,dS2], then the interval [dS1,dS2] defines the range of tolerance to injected crosstalk delay. The higher the range of dS(s, t), the less crosstalk protection is needed for the corresponding clock net 906.

[0081]
The clock skew S is the maximum difference in clock arrival time between the clock root driver 902 in FIG. 9A and each of the destination flipflops 908, that is, S=D_{max}−D_{min}, where D_{max }is the maximum clock delay from the clock root driver 902 to a destination flipflop 908 in the path P_{max}, and D_{min }is the minimum clock delay from the clock root driver 902 to a destination flipflop 908 in the path P_{min}. Each path P has a corresponding propagation delay D_{p}, where D_{min}≦D_{P}≦D_{max}. The paths P_{max }and P_{min }are the most sensitive to injected crosstalk delay, because these paths are on the boundaries of the range of values of the clock skew S and are therefore most likely to increase the range of values for the propagation delays D_{P}. The other paths P are less sensitive to injected crosstalk delay, because a change in the corresponding propagation delay D_{P }is less likely to alter the clock skew S and the functionality of the integrated circuit design.

[0082]
If a clock net path (s,t) belongs to the path P, and if P is not P_{max }or P_{min}, then small changes in the propagation delay D(s,t) that may result from a crosstalk protection scheme may calculated as a difference D_{min}−D_{P }and a difference D_{max}−D_{P }along the path segment (s,t) will not alter the clock skew S. Accordingly, dS(s, t) may be set equal to a range of possible changes as follows:

dS(s,t)=[k(D _{min} −D _{P}),k(D _{max} −D _{P})] (1)

[0083]
where k=D(s,t)/D_{P}. As a result, the range [(D_{min}−D_{P}), (D_{max}−D_{P})] for the path segments (s, t) in the path P is distributed proportionally in the propagation delay D(s,t). If the delay in the path segment (s,t) is decreased by less than −k(D_{min}−D_{P}), then D_{min }is unchanged, and if the delay in the path segment (s,t) is increased by less than k(D_{max}−D_{P}), then D_{max }is unchanged. The greater the range of dS(s,t), the less crosstalk protection is needed for the clock net 906.

[0084]
If any path segment (s,t) belongs to both paths P_{max }and P_{min}, then any change in the delay along the path segment (s,t) will not alter the clock skew S. Accordingly, no delay correction is needed, and dS(s,t) may be set equal to zero.

[0085]
A clock net length L(s,t) for each path segment (s,t) is calculated according to wellknown techniques.

[0086]
A wire segment number N(s,t) for each path segment (s,t) in the clock net 906 is assigned according to wellknown techniques. For example, a clock net with three path segments (s, t) may be assigned wire segment numbers 1, 2 and 3.

[0087]
The clock net fanout is equal to the number of clock destination flipflops 908. The signal ramptime of each clock net at each corresponding clock destination flipflop 908 is estimated according to wellknown techniques as a function of net resistance, total capacitance, and clock buffer drive capability.

[0088]
The library of precharacterized crosstalk protection parameters in step 808 is constructed as follows. For each crosstalk protection scheme described in FIGS. 27, the following function of incremental crosstalk delay is generated by simulation:

dD=F(L _{tot} , T, B, M, prot) (2)

[0089]
where L_{tot }is equal to the path segment length L(s,t), T is representative of the packaging technology, B is the clock driver strength, M is the metal layer (for example, the metal layer may be M2 or M5), and prot is the type of crosstalk protection scheme. The simulation of each crosstalk protection scheme is performed according to wellknown techniques for a fanout equal to one under worst case conditions, that is, the clock net is surrounded by the strongest net aggressors, and all net aggressors switch simultaneously in the same direction. For example, the crosstalk protection scheme may be 1grid additional spacing, 2grid additional spacing, or metal shielding. The incremental crosstalk delay dD defined in equation (2) may be conservatively approximated by:

dD=a*L _{tot} (3)

[0090]
where a is equal to a constant evaluated for each set of variables {T,B,M,prot} for a fanout equal to one. By storing the set of constants

a={a(T,B,M,prot)} (4)

[0091]
in a library of precharacterized crosstalk protection parameters for each unprotected and protected clock net wiring scheme, the incremental crosstalk delay dD may be calculated for each path segment (s,t) in a clock net having a total length L_{tot }from the appropriate crosstalk protection parameters.

[0092]
The incremental crosstalk delay dD for a path segment (s,t) having a total length L_{tot }for a given packaging technology, metal layer, and a partial crosstalk protection scheme may be calculated from the library of precharacterized crosstalk protection parameters as follows. The total length L_{tot }includes a partially protected length L_{p}≦L_{tot }and an unprotected length L_{up}=L_{tot}−L_{p}. The following linear functions may be calculated from equation (3):

dD _{up} =a _{up} *L _{tot} (5)

dD _{p} =a _{p} *L _{tot} (6)

[0093]
where a_{p }and a_{up }are constants from the library of precharacterized crosstalk protection parameters for unprotected and protected clock nets, respectively, dD_{up }and dD_{p }is used for all protected incremental delays. The incremental delay dD in a clock net having partial protection may be calculated as follows from equation (7):

dD=dD _{p}(L _{p})+dD _{up}(L _{up})=dD _{p}(L _{p})+dD _{up}(L _{tot} −L _{p}) (7)

[0094]
Substituting the linear equations (5) and (6) into equation (7) yields equation (8):
$\begin{array}{cc}\begin{array}{c}d\ue89e\text{\hspace{1em}}\ue89eD=\ue89e{a}_{p}*{L}_{p}+{a}_{u\ue89e\text{\hspace{1em}}\ue89ep}*\left({L}_{\mathrm{tot}}{L}_{p}\right)\\ =\ue89e\left({a}_{p}{a}_{u\ue89e\text{\hspace{1em}}\ue89ep}\right)*{L}_{p}+{a}_{u\ue89e\text{\hspace{1em}}\ue89ep}*{L}_{\mathrm{tot}}\end{array}& \left(8\right)\end{array}$

[0095]
[0095]FIG. 9B illustrates a plot 950 of incremental crosstalk delay for a specific technology using various crosstalk protection schemes according to an embodiment of the present invention. Shown in FIG. 9B are an incremental crosstalk curve 952 with minimum grid spacing (no crosstalk protection), an incremental crosstalk curve 954 with 1grid spacing crosstalk protection, and an incremental crosstalk curve 956 with metal shielding crosstalk protection. As shown in the plot 950, using a metal shielding crosstalk protection scheme results in the minimum incremental crosstalk delay dD for increasing values of the clock net length.

[0096]
An intelligent engine selects an optimum protection scheme for the selected clock net against injected crosstalk delay according to the clock tree analysis by determining how adequate partial crosstalk protection may be provided using minimum chip area while taking into consideration clock skew and ramptime, and further minimizing chip area by taking into account possible reduction in protection where the clock net has many net aggressors, that is, where the probability of simultaneous switching by all the net aggressors is reduced.

[0097]
In the following example, a clock net having a fanout of one with a driver s and a receiver t is selected using an additional 1grid protection scheme selected from the library of precharacterized crosstalk protection parameters. Also, possible changes in the clock propagation delay, or clock skew, are ignored, the possible effect of implementing partial protection in the front end or the back end of the clock net on dD is ignored, and possible changes in the clock ramptime are ignored. A protected length L_{p}≦L is desired such that the limitation on the incremental crosstalk delay dD given by

dD=dD_{max} (9)

[0098]
is satisfied, where dD_{max }is the maximum allowed incremental crosstalk delay, for example, 25 picoseconds. Also, the minimum chip area required for protection is desired, which means minimizing the protected length L_{p}.

[0099]
For dD=dD_{max}, the protected length L_{p }may be found by rearranging equation (8):

L _{p}=(dD _{max} −a _{up} *L _{tot})/(a _{p} −a _{up}) (10)

[0100]
Depending on the value of the total net length L_{tot}, there are three possible solutions for the protected net length L_{p}. If L_{p}>L_{tot}, then protecting the entire net will be insufficient to satisfy the limitation on the maximum allowable crosstalk delay dD_{max}. In this case, a stronger crosstalk protection scheme may be attempted, for example, greater grid spacing or metal shielding. If 0>L_{p}≦L_{tot }then partial protection of the clock net may be used. Additional information may be used to decide whether the best place to implement this protection is in the front end or the back end of the clock net. For example, if the clock protection is additional grid spacing, and if the propagation delay would be improved by a decreasing the value of dS(s, t), then the net protection should be implemented in the front end of the clock net, because capacitance at the front end of the clock net is less than capacitance at the back end of the clock net, and reducing front end capacitance has a greater effect on incremental delay than does reducing back end capacitance. If metal shielding is used, then the net protection should be placed in the back end of the net, because increasing capacitance at the back end of the clock net has less effect on incremental delay than does increasing back end capacitance. If L_{p}≦0, no net protection is needed.

[0101]
[0101]FIG. 10 illustrates a flow chart 1000 of a method of selecting an optimal partial protection scheme according to an embodiment of the present invention.

[0102]
Step 1002 is the entry point of the flow chart 1000.

[0103]
In step 1004, the total net length L_{tot }of a selected clock net is received as input and an initial crosstalk protection scheme is selected, for example, additional 1grid spacing.

[0104]
In step 1006, the protected net length L_{p }is calculated from the library of precharacterized crosstalk protection parameters according to equation (10).

[0105]
In step 1008, if L_{p}≦0, then no protection is needed for the selected clock net, and control is transferred to step 1018; else if L_{p}=L_{tot}, then control is transferred to step 1010; else if L_{p}<L_{tot}, then control is transferred to step 1012; else if L_{p}>L_{tot}, then control is transferred to step 1016.

[0106]
In step 1010, the current crosstalk protection scheme is selected to protect the entire length of the selected clock net, and control is transferred to step 1018.

[0107]
In step 1012, the current protection scheme is selected for the protected net length L_{p }of the clock net.

[0108]
In step 1014, the placement of the protected net length L_{p }in the front end, near the clock driver s, or near the back end, near the receiver t, of the selected clock net is determined as described above, and control is transferred to step 1018.

[0109]
In step 1016, a stronger type of crosstalk protection scheme is selected, and control is transferred to step 1006.

[0110]
Step 1018 is the exit point of the flow chart 1000.

[0111]
The protected net length L_{p }and the corresponding required chip area may be advantageously reduced by taking into account stochastic properties that affect the probability of the worst case crosstalk incremental delay in a selected clock net. When the selected clock net includes a number n of several path segments between the driver s and the receiver t as shown in FIG. 1, then for some larger n′>n, it is reasonable to decrease the amount of crosstalk protection based on the small probability of certain crosstalk events.

[0112]
For a clock net (s,t) having n linear path segments, the number of net aggressors N may be expressed as:

N=f(n)=m*n (11)

[0113]
where m is the average number of net aggressors in a single linear path segment. In the worst case scenario, m=2, that is, there is a net aggressor on both sides of every path segment. Alternatively, a more complex model may be used, for example, m=m(L), where L is the path segment length, in which there may be more than an average of two net aggressors for every path segment. The function m(L) may be approximated by rL, where r is a constant. For example, a value of five may be used for r, if L is in millimeters.

[0114]
The crosstalk incremental delay dD in the selected clock net may be modeled as dD=F(N), where the function F(N) is a nonincreasing function of N. Initially, that is, for small values of N, dD has a nearly constant value, then at some point, dD decreases for increasing values of N:

dD=dD(2) if M_{xt}≧1 (12)

dD=dD(2)*M_{xt }if M_{xt}<1

[0115]
where dD(2) is the incremental crosstalk delay dD in the selected clock net for one linear path segment and two net aggressors, which is the worst case simulation used to calculate the values in the library of precharacterized crosstalk protection parameters. The values of the incremental crosstalk delay dD are therefore available for all net protection lengths Lp, and dD may have different values for an unprotected net, a net protected by grid spacing, and a net protected by metal shielding.

[0116]
M_{xt }is the mathematical expectation of the number of crosstalk risk situations in all clock nets of the clock tree in a selected period equal to TIME. For example, M_{xt }may be equivalent to one crosstalk failure for a value of TIME equal to 72×10^{6 }seconds, which is the industry standard used equivalent to 2.28 years. The mathematical expectation M_{xt }may be calculated as follows:

M _{xt} =M ^{(1)} M ^{(2)} (13)

[0117]
where M^{(1) }is the mathematical expectation of the number of clock nets with n linear path segments (N is equal to m*n net aggressors) having a transition overlapping the timing windows of all net aggressors, that is, the clock signal changes state at or near the same time each of the net aggressors changes state, and M^{(2) }is the mathematical expectation of the number of overlaps between the clock transition and each of N net aggressors within their respective timing windows during a time period TIME of, for example, 2.28 years.

[0118]
The mathematical expectation M^{(1) }may be expressed as:

M ^{(1)} =P ^{(1)} N ^{(1)} (14)

[0119]
where p^{(1) }is the probability that one clock net in the clock tree with n linear path segments (N is equal to m*n net aggressors) has a transition that overlaps with the timing windows of all net aggressors, and N^{(1) }is the number of clock nets with n linear path segments in the clock tree. N^{(1) }is equal to Q_{n}*N_{clock}, where Q_{n }is the probability that a certain clock net has n linear path segments, and N_{clock }is the number of clock nets in the clock tree.

[0120]
[0120]FIG. 10A illustrates a histogram of a typical distribution of clock nets having n path segments used to calculate the probability Q_{n }according to an embodiment of the present invention. In this example, the distribution is a normal distribution having a mean of n=3. The probability Q_{n }is equal to the number of clock nets having n path segments divided by the total number of all path segments, that is, the sum of the number of path segments for every clock net in the clock tree.

[0121]
The mathematical expectation M^{(2) }may be expressed as:

M ^{(2)} =P ^{(2)} N ^{(2)} (15)

[0122]
where p^{(2) }is the probability that there is an overlap between a clock transition and a transition of each of N net aggressors within their respective timing windows during one clock cycle, and N^{(2) }is the number of clock transitions during the period TIME, that is, N^{(2)}=TIME*F=72×10^{6}* F, where F is the design clock frequency.

[0123]
The following assumptions may be made to estimate the probability p^{(1) }that one clock net in the clock tree with n linear path segments (N is equal to m*n net aggressors) has a transition that overlaps with a timing window of a net aggressor: (1) all net aggressors may be considered independent events; (2) every net aggressor is independent of every clock signal, including any clock signals in multiple clock domains and stages of clock nets; and (3) the worst case scenario is always considered on the conservative side, that is, the average timing window of net aggressors is greater than the clock ramptime:

TW>τ_{clk} (16)

[0124]
where TW is the average timing window of a net aggressor and τ_{clk }is the clock ramptime.

[0125]
[0125]FIG. 10B illustrates the geometrical probability of overlap between a clock transition and the timing window of a net aggressor according to an embodiment of the present invention. The timing window of a net aggressor TW_{s }is not generally a random function with respect to the net aggressor s, however, the clock transition within the timing window may be considered as a random function. Accordingly, the number of clock transitions will not affect the mathematical expectation when accounting for different locations of the timing window with respect to the number of number of clock transitions.

[0126]
If the timing window of a net aggressor plus the net aggressor ramptime (TW_{s}+τ_{s}) overlaps with the clock transition or ramptime τ_{clk }interval, then the timing window of the net aggressor s is said to overlap the clock transition. It is assumed that a net aggressor s overlaps the clock transition so that the clock ramptime τ_{clk }is inside the timing window TW_{s }of the net aggressor s. The number of net aggressors for a single path segment is assumed to be two, that is, m=2.

[0127]
The path segments are assumed to have a normal length distribution with a small standard deviation, for example, less than five percent of the mean. This means that each path segment is assumed to have about the same length.

[0128]
Using the assumptions set forth above, the probability P^{(1) }that a clock net in the clock tree with n linear path segments (N is equal to m*n net aggressors) has a transition that overlaps with a timing window of a net aggressor may be estimated according to:

P^{(1)}=(P_{D>90%}*P^{m})^{n} (17)

[0129]
where P_{D>90% }is the probability that the wire density along a selected path segment is greater than 90 percent as a function of the average design wire density. If the probability that the wire density along a selected path segment is greater than 90 percent, the selected path segment is said to be completely surrounded by net aggressors.

[0130]
[0130]FIG. 11 illustrates a plot 1100 of a probability mass function as a function of wire density along a path segment used to calculate P_{D>90% }according to an embodiment of the present invention. Shown in FIG. 11 are a density distribution of a path segment for an average design wire density of 60 percent 1102, a density distribution of a path segment for an average design wire density of 70 percent 1104, a density distribution of a path segment for an average design wire density of 80 percent 1106, and a density distribution of a path segment for an average design wire density of 90 percent 1108.

[0131]
[0131]FIG. 12A illustrates a plot of P
_{D>90% }as a function of average design wire density calculated from FIG. 11. Note that P
_{D>90%}=0.15 for designs having an average wire density of 80 percent. The probability P of a clock net overlapping a timing window of a net aggressor s may be expressed according to geometric probability properties as:
$\begin{array}{cc}\begin{array}{ccc}P=\lambda \ue8a0\left({\tau}_{\mathrm{clk}}+{\tau}_{s}+T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\right)/T\ue89e\text{\hspace{1em}}& \mathrm{if}& \left({\tau}_{\mathrm{clk}}+{\tau}_{s}+T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\right)\le T\ue89e\text{\hspace{1em}}\\ P=\lambda \ue89e\text{\hspace{1em}}& \mathrm{if}& \left({\tau}_{\mathrm{clk}}+{\tau}_{s}+T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\right)>T\end{array}& \left(18\right)\end{array}$

[0132]
where T=1/F is the clock signal period, and λ≦1 indicates the reduction in probability of the overlap between the clock signal and the timing window of a net aggressor s compared to the probability of overlap between two independent random signals. Substituting equation (17) into equation (18) to solve for P
^{(1) }yields:
$\begin{array}{cc}\begin{array}{cc}{P}^{\left(1\right)}={\left({P}_{D>90\ue89e\text{\hspace{1em}}\ue89e\%}\ue89e{P}^{m}\right)}^{n}& \left({\tau}_{\mathrm{clk}}+{\tau}_{s}+T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\right)\le T\\ \text{\hspace{1em}}\ue89e={\left({{P}_{D>90\ue89e\text{\hspace{1em}}\ue89e\%}\ue8a0\left(\lambda \ue8a0\left({\tau}_{\mathrm{clk}}+{\tau}_{s}+T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\right)/T\right)}^{m}\right)}^{n}& \text{\hspace{1em}}\\ {P}^{\left(1\right)}={\left({P}_{D>90\ue89e\text{\hspace{1em}}\ue89e\%}\ue89e{P}^{m}\right)}^{n}& \left({\tau}_{\mathrm{clk}}+{\tau}_{s}+T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\right)>T\\ \text{\hspace{1em}}\ue89e={\left({P}_{D>90\ue89e\text{\hspace{1em}}\ue89e\%}\ue89e{\lambda}^{m}\right)}^{n}& \text{\hspace{1em}}\end{array}& \left(19\right)\end{array}$

[0133]
Substituting for worst case conditions, that is, for m=2 in equations (19), yields:
$\begin{array}{cc}\begin{array}{cc}{P}^{\left(1\right)}={\left({P}_{D>90\ue89e\text{\hspace{1em}}\ue89e\%}\ue89e{P}^{2}\right)}^{n}& \left({\tau}_{\mathrm{clk}}+{\tau}_{s}+T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\right)\le T\\ \text{\hspace{1em}}\ue89e={\left(0.15\ue89e{\left(\lambda \ue8a0\left({\tau}_{\mathrm{clk}}+{\tau}_{s}+T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\right)/T\right)}^{2}\right)}^{n}& \text{\hspace{1em}}\\ {P}^{\left(1\right)}={\left({P}_{D>90\ue89e\text{\hspace{1em}}\ue89e\%}\ue89e{P}^{2}\right)}^{n}& \left({\tau}_{\mathrm{clk}}+{\tau}_{s}+T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\right)>T\\ \text{\hspace{1em}}\ue89e={\left(0.15\ue89e\text{\hspace{1em}}\ue89e{\lambda}^{2}\right)}^{n}& \text{\hspace{1em}}\end{array}& \left(20\right)\end{array}$

[0134]
Substituting equation (20) into equation (14) to solve for M
^{(1) }yields:
$\begin{array}{cc}\begin{array}{cc}{M}^{\left(1\right)}={P}^{\left(1\right)}\ue89e{N}^{\left(1\right)}& \left({\tau}_{\mathrm{clk}}+{\tau}_{s}+T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\right)\le T\\ \text{\hspace{1em}}\ue89e={\left({{P}_{D>90\ue89e\text{\hspace{1em}}\ue89e\%}\ue8a0\left(\lambda \ue8a0\left({\tau}_{\mathrm{clk}}+{\tau}_{s}+T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\right)/T\right)}^{m}\right)}^{n}\ue89e{N}^{\left(1\right)}& \text{\hspace{1em}}\\ \text{\hspace{1em}}\ue89e=({P}_{D>90\ue89e\text{\hspace{1em}}\ue89e\%}(\lambda ({\tau}_{\mathrm{clk}}+{\tau}_{s}+& \text{\hspace{1em}}\\ {{\text{\hspace{1em}}\ue89eT\ue89e\text{\hspace{1em}}\ue89e{W}_{s})/T)}^{m})}^{n}\ue89e{Q}_{n}\ue89e{N}_{\mathrm{clk}}& \text{\hspace{1em}}\\ {M}^{\left(1\right)}={P}^{\left(1\right)}\ue89e{N}^{\left(1\right)}={\left({P}_{D>90\ue89e\text{\hspace{1em}}\ue89e\%}\ue89e{\lambda}^{m}\right)}^{n}\ue89e{N}^{\left(1\right)}& \left({\tau}_{\mathrm{clk}}+{\tau}_{s}+T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\right)>T\\ \text{\hspace{1em}}\ue89e={\left({P}_{D>90\ue89e\text{\hspace{1em}}\ue89e\%}\ue89e{\lambda}^{m}\right)}^{n}\ue89e{Q}_{n}\ue89e{N}_{\mathrm{clk}}& \text{\hspace{1em}}\end{array}& \left(21\right)\end{array}$

[0135]
where Q_{n }is the probability that a selected clock net has n path segments, and N_{clk }is the number of clock nets in the clock tree.

[0136]
Substituting for worst case conditions, that is, for m=2 and λ=1 in equations (21) yields:

M ^{(1)}=(0.015((τ_{clk}+τ_{s} +TW _{s})/T ^{2})^{n} Q _{n} N _{clk}(τ_{clk}+τ_{s} +TW _{s})≦T (22)

[0137]
where T is the clock signal period.

[0138]
The probability P^{(2) }that a clock transition overlaps each of N net aggressors within their respective timing windows during one clock cycle may be expressed as:

P(^{2})=(0.5 P_{a}P_{s})^{N} (23)

[0139]
where 0.5 is the probability that a net aggressor signal s will switch in a direction opposite to that of the clock signal. The probability P_{a }is the probability that the net aggressor signal s will switch during a clock cycle, which typically has a value of about 7 percent. The probability P_{s }is the probability that the net aggressor signal s will overlap the clock signal, which, may be expressed as:

P_{S}=ξ(τ_{clk}τ_{s})>TW _{s}(τ_{clk}+τ_{s})≦TW _{s} P _{S}=ξ(τ_{clk}+τ_{s})<TW _{s} (24)

[0140]
where ξ≦1 indicates the reduction in the probability of overlap between the clock signal transition and the net aggressor s signal transition compared to the probability of overlap between two independent random signals.

[0141]
As stated above with regard to FIG. 10B, it is assumed that a net aggressor s overlaps the clock transition so that the clock ramptime τ_{clk }is inside the timing window TW_{s }of the net aggressor s, that is, there is full overlap between the timing window TW_{s }of the net aggressor signal and the clock signal. Accordingly, P^{(2) }may be expressed as:

P ^{(2)}=(0.5 P_{a}ξ(τ_{clk}+τ_{s})/TW _{s})^{mn }if (τ_{clk}+τ_{s})≦TW _{s}(0.5 P _{a}=ξ)^{mn }if (τ_{clk}+τ_{s})>TW_{s} (25)

[0142]
Substituting equations (25) into equation (15) to solve for M
^{(2) }yields:
$\begin{array}{cc}\begin{array}{cc}{M}^{\left(2\right)}={P}^{\left(2\right)}\ue89e{N}^{\left(2\right)}& \text{\hspace{1em}}\\ \text{\hspace{1em}}\ue89e={\left(0.5\ue89e\text{\hspace{1em}}\ue89e{P}_{a}\ue89e\xi \ue8a0\left({\tau}_{\mathrm{clk}}+{\tau}_{s}\right)/{\mathrm{TW}}_{s}\right)}^{m\ue89e\text{\hspace{1em}}\ue89en}\ue89e{N}^{\left(2\right)}& \text{\hspace{1em}}\\ \text{\hspace{1em}}\ue89e={\left(0.5\ue89e\text{\hspace{1em}}\ue89e{P}_{a}\ue89e\xi \ue8a0\left({\tau}_{\mathrm{clk}}+{\tau}_{s}\right)/{\mathrm{TW}}_{s}\right)}^{m\ue89e\text{\hspace{1em}}\ue89en}\ue89e{N}^{\left(2\right)}& \mathrm{if}\ue89e\text{\hspace{1em}}\ue89e\left({\tau}_{\mathrm{clk}}+{\tau}_{s}\right)\le T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\ue89e\text{\hspace{1em}}\\ {M}^{\left(2\right)}={P}^{\left(2\right)}\ue89e{N}^{\left(2\right)}={\left(0.5\ue89e{P}_{a}\ue89e\xi \right)}^{m\ue89e\text{\hspace{1em}}\ue89en}\ue89e{N}^{\left(2\right)}& \text{\hspace{1em}}\\ \text{\hspace{1em}}\ue89e={\left(0.5\ue89e{P}_{a}\ue89e\xi \right)}^{m\ue89e\text{\hspace{1em}}\ue89en}\ue89e72*{10}^{6}\ue89eF& \mathrm{if}\ue89e\text{\hspace{1em}}\ue89e\left({\tau}_{\mathrm{clk}}+{\tau}_{s}\right)>T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\end{array}& \left(26\right)\end{array}$

[0143]
where F is equal to the design clock frequency. Substituting m=2 for worst case conditions in equations (26) yields:
$\begin{array}{cc}\begin{array}{cc}{M}^{\left(2\right)}={P}^{\left(2\right)}\ue89e{N}^{\left(2\right)}& \text{\hspace{1em}}\\ \text{\hspace{1em}}\ue89e={\left(0.5\ue89e\text{\hspace{1em}}\ue89e{P}_{a}\ue89e\xi \ue8a0\left({\tau}_{\mathrm{clk}}+{\tau}_{s}\right)/{\mathrm{TW}}_{s}\right)}^{m\ue89e\text{\hspace{1em}}\ue89en}\ue89e{N}^{\left(2\right)}& \text{\hspace{1em}}\\ \text{\hspace{1em}}\ue89e={\left(0.5\ue89e\text{\hspace{1em}}\ue89e{P}_{a}\ue89e\xi \ue8a0\left({\tau}_{\mathrm{clk}}+{\tau}_{s}\right)/{\mathrm{TW}}_{s}\right)}^{m\ue89e\text{\hspace{1em}}\ue89en}\ue89e{N}^{\left(2\right)}& \mathrm{if}\ue89e\text{\hspace{1em}}\ue89e\left({\tau}_{\mathrm{clk}}+{\tau}_{s}\right)\le T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\ue89e\text{\hspace{1em}}\\ {M}^{\left(2\right)}={P}^{\left(2\right)}\ue89e{N}^{\left(2\right)}={\left(0.5\ue89e{P}_{a}\ue89e\xi \right)}^{m\ue89e\text{\hspace{1em}}\ue89en}\ue89e{N}^{\left(2\right)}& \text{\hspace{1em}}\\ \text{\hspace{1em}}\ue89e={\left(0.5\ue89e{P}_{a}\ue89e\xi \right)}^{m\ue89e\text{\hspace{1em}}\ue89en}\ue89e72*{10}^{6}\ue89eF& \mathrm{if}\ue89e\text{\hspace{1em}}\ue89e\left({\tau}_{\mathrm{clk}}+{\tau}_{s}\right)>T\ue89e\text{\hspace{1em}}\ue89e{W}_{s}\end{array}& \left(27\right)\end{array}$

[0144]
The following crosstalk protection scheme is considered for a clock net having a fanout of one for use with any fanout value. The length of a path segment i may be expressed as dL(i), where L(i) is the total length of the clock net from the driver s to the end of the path segment i, so that:

L(i)=L(i−1)+dL(i)=dL(1)+dL(2)+ . . . +dL(i) (28)

[0145]
Solution (1):
$\begin{array}{cc}\begin{array}{c}d\ue89e\text{\hspace{1em}}\ue89eD=\ue89e\left[{d}_{p}\ue8a0\left({L}_{p}\right)+d\ue89e\text{\hspace{1em}}\ue89e{D}_{u\ue89e\text{\hspace{1em}}\ue89ep}\ue8a0\left({L}_{\mathrm{tot}}{L}_{p}\right)\right]\ue89e{M}_{x\ue89e\text{\hspace{1em}}\ue89et}\ue8a0\left(n\right)\\ \approx \ue89e\left[\left({a}_{p}{a}_{u\ue89e\text{\hspace{1em}}\ue89ep}\right)\ue89e{L}_{p}+{a}_{u\ue89e\text{\hspace{1em}}\ue89ep}\ue89e{L}_{\mathrm{tot}}\right]\ue89e{M}_{x\ue89e\text{\hspace{1em}}\ue89et}\ue8a0\left(n\right)\end{array}& \left(29\right)\end{array}$

[0146]
where M_{xt}(n) is a relaxation crosstalk multiplier between the net aggressors and the clock net.

[0147]
[0147]FIG. 12B illustrates a plot of the relaxation crosstalk multiplier M_{xt}(n) as a function of the number of path segments n in the selected clock net according to an embodiment of the present invention. The plot 1200 reveals that as the number of net aggressors increases, the value of the crosstalk multiplier M_{xt}(n) increases to one for lower values of n.

[0148]
Solving equation (29) for L_{p }yields:

L _{p}=(dD _{max} /M _{xt}(n)−a _{up} L _{tot})/(a _{p} −a _{up}) (30)

[0149]
Solution (1) assumes that the path segment lengths have a normal distribution. If this is not the case, then sufficient crosstalk protection may not be available, for example, if the first path segment is 90 percent of the total length L_{tot }and the number of path segments n for the clock net is high, for example, more than four. A more conservative method of calculating the optimum protected path length is described as follows.

[0150]
Solution (2):

[0151]
[0151]FIG. 13 illustrates a flow chart 1300 of a method of calculating an optimum protected path length for a selected clock net according to an embodiment of the present invention.

[0152]
Step 1302 is the entry point of the flow chart 1300.

[0153]
In step 1304, an index i is initialized to zero, a path segment variable L(0) is initialized to zero, and an optimum protected path length L_{p }is initialized to zero.

[0154]
In step 1306, i is incremented by one.

[0155]
In step 1308, if i is greater than the number of path segments n, then control is transferred to step 1330.

[0156]
In step 1310, the path length from the driver s to the path segment i is calculated L(i)=L(i−1)+dL(i) is calculated according to equation (28).

[0157]
In step 1312, the protected path length L_{p}(i) for L_{tot}=L(i) is calculated by modifying equation (30) as follows:

L _{p}(i)=(dD _{max} /M _{xt}(i)−a _{up} L(i))/(a _{p} −a _{up}) (31)

[0158]
In step 1314, if L_{p}(i) is less than or equal to zero, then control is transferred to step 1306; otherwise, control is transferred to step 1316.

[0159]
In step 1316, a variable L_{rest }is calculated according to:

L _{rest} =L _{tot} −L(i) (32)

[0160]
In step 1318, the protected length L_{p }is calculated according to:

L _{p} =L _{p}(i)−L _{rest} M _{xt}(n) (33)

[0161]
In step 1320, if L_{p}≦0, then no protection is needed for the selected clock net, and control is transferred to step 1330; else if L_{p}=L_{tot}, then control is transferred to step 1322; else if L_{p}<L_{tot}, then control is transferred to step 1324; else if L_{p}>L_{tot}, then control is transferred to step 1328.

[0162]
In step 1322, the current crosstalk protection scheme is selected for the entire length of the selected clock net L_{tot}, and control is transferred to step 1330.

[0163]
In step 1324, the current protection scheme is selected for the protected net length L_{p }of the clock net.

[0164]
In step 1326, the placement of the protected net length L_{p }near the front end of the clock net, that is, near the clock driver s, or near the back end of the clock net, that is, near the receiver t, is determined as described above, and control is transferred to step 1330.

[0165]
In step 1328, a stronger type of crosstalk protection scheme is selected, and control is transferred to step 1304.

[0166]
Step 1330 is the exit point of the flow chart 1300.

[0167]
The following rules based on the delay model dD and the physics of signal propagation may be used individually and in combination to further optimize the crosstalk protection.

[0168]
Rule (1). Incorporate skew correction information

[0169]
Rule (1.1): If dS(s,t)=0, then no delay correction is required for the selected clock net. In this case, one of the following strategies may be selected: (a) use adequate crosstalk protection with optimization for the clock net as described above (default); or (b) protect the clock net as much as possible to avoid variations in D_{min }and D_{max }by using the strongest available type of crosstalk protection over the entire length L_{tot }of the selected clock net.

[0170]
Rule (1.2): If dS(s,t)ε[dS1,dS2], then the protected length L_{p }may be reduced as follows:

L _{p}=(dD _{max} +D _{tolerance} −a _{up} L _{tot})/(a _{p} −a _{up}) (34)

[0171]
where

D _{tolerace}=MIN{−dS1,dS2} (35)

[0172]
and dS1≦0.

[0173]
Rule (1.3): If dS(s,t) dS1<0, then adequate crosstalk protection should be implemented that decreases clock net delay. For example, if the crosstalk protection scheme used is grid spacing, then the protected length L_{p }should be implemented in front near the driver s of the clock net. On the other hand, if the crosstalk protection scheme used is metal shielding, then the protected length L_{p }should be implemented near the end of the clock net, because increasing capacitance at the back end of the clock net has less effect on incremental delay than does increasing back end capacitance.

[0174]
Rule (1.4): If dS(s,t)=dS2>0, then adequate crosstalk protection should be implemented that increases clock net delay. For example, if the crosstalk protection scheme used is grid spacing, then the protected length L_{p }should be implemented near the end of the clock net. On the other hand, if the crosstalk protection scheme used is metal shielding, then the protected length L_{p }should be implemented near the front of the clock net.

[0175]
Rule (2). Evaluate different types of crosstalk protection schemes and possibly mixed crosstalk protection schemes to find the optimum crosstalk protection.

[0176]
Rule (2.1): Any type of crosstalk protection scheme increases chip area.

[0177]
Rule (2.2): A metal shielding crosstalk protection scheme increases chip area in proportion to L_{p}.

[0178]
Rule (2.3): A grid spacing crosstalk protection scheme increases chip area in proportion to L_{P}*Δ_{s}.

[0179]
Rule (2.4): A metal shielding crosstalk protection scheme is superior to a grid spacing crosstalk protection scheme in terms of clock delay dD.

[0180]
Rule (2.5): If dS(s,t)=dS1<0, then a metal shielding crosstalk protection scheme is inferior to a grid spacing crosstalk protection scheme is inferior to a grid spacing crosstalk protection scheme in terms of clock delay dD.

[0181]
Rule (2.6): A grid spacing crosstalk protection scheme has a lower dD, D and clock signal ramptime with increasing values of Δ_{s}.

[0182]
Rule (2.7): A metal shielding crosstalk protection scheme having the same chip area as a grid spacing crosstalk protection scheme has less dD, but maximum values of D and clock signal ramptime.

[0183]
Rule (2.8): A metal shielding crosstalk protection scheme is inferior to a grid spacing crosstalk protection scheme in terms of clock signal ramptime.

[0184]
Rule (2.9): A crosstalk source coupled near the end of a clock net injects more crosstalk delay into the clock net than the same crosstalk source coupled near the front of the clock net, because the net aggressor is closer to the net destination.

[0185]
Rule (3). Consider implementing different types of crosstalk protection schemes in the front or the end of the clock net to find the optimum protection.

[0186]
Rule (3.1): Increasing the clock net capacitance by Δ_{C }near the front of the clock net increases the clock delay more than the same increase in clock net capacitance near the end of the clock net as explained above with regard to formula (10).

[0187]
Rule (3.2): Decreasing the clock net capacitance by Δ_{C }near the end of the clock net decreases the clock delay less than the same decrease in clock net capacitance near the front of the clock net as explained above with regard to formula (10).

[0188]
Rule (3.3): A crosstalk protection scheme implemented near the front of a clock net generally requires the least chip area, because all (s,t) paths in the clock net are protected.

[0189]
Rule (3.4): A crosstalk protection scheme implemented near the end of a clock net is generally the most effective, because the crosstalk protection is closest to the destination.

[0190]
Rule (3.5): A crosstalk protection scheme implemented near the front of a clock net is generally less effective than the same crosstalk protection scheme implemented near the end of a clock net.

[0191]
Rule (3.6): A metal shielding crosstalk protection scheme implemented near the front of a clock net generally results in a lower increase in clock signal ramptime than implementing the metal shielding crosstalk protection scheme near the end of the clock net.

[0192]
Rule (3.7): If dS(s,t)=dS1<0, then a metal shielding crosstalk protection scheme implemented near the front of a clock net generally results in a lower increase in total clock delay dD than implementing the metal shielding crosstalk protection scheme near the end of the clock net.

[0193]
Rule (3.8): A metal shielding crosstalk protection scheme implemented near the end of a clock net generally results in a lower increase in incremental delay dD than implementing the metal shielding crosstalk protection scheme near the front of the clock net.

[0194]
Rule (3.9): A grid spacing crosstalk protection scheme implemented near the end of a clock net generally results in a lower increase in total clock delay dD and clock signal ramptime than implementing the grid spacing crosstalk protection scheme near the front of the clock net.

[0195]
Rule (3.10): If dS(s,t)=dS1<0, then a grid spacing crosstalk protection scheme implemented near the end of a clock net generally results in a lower increase in total clock delay dD.

[0196]
Rule (4). Evaluate clock net fanout to find optimum crosstalk protection.

[0197]
Rule (4.1): Compare all driverreceiver net paths (s,t) to find total clock delay dD timing violations.

[0198]
Rule (4.2): Protect all net paths (s,t) with total clock delay dD timing violations.

[0199]
Rule (4.3): Select a crosstalk protection scheme or a combination of crosstalk protection schemes that avoids total clock delay dD timing violations for all net paths (s,t) and that requires minimum additional chip area.

[0200]
Rule (4.4): Always protect common path segments shared by two or more net paths (s,t) that have total clock delay dD timing violations.

[0201]
Rule (4.5): Because the common path segments are generally closer to the driver s in a clock tree, use a metal shielding crosstalk protection scheme near the front of the net if dS(s,t)=dS1<0.

[0202]
Rule (4.6): If a common path segment is protected with metal shielding, then use a grid spacing crosstalk protection scheme for the remaining portion of the protected path length L_{p }if adequate protection is possible, otherwise use a metal shielding crosstalk protection scheme for the remaining portion of the protected path length L_{p}.

[0203]
Some heuristics and user preferences (Hrules) may be specified by the user to resolve any possible conflicts among the rules given above, for example:

[0204]
Rule (H1). Apply only the following set of rules from Rules 1, 2, 3 and 4: 1.2, 2.5, 3.9 and 4.6.

[0205]
Rule (H2). Do not apply any of the following set of rules from Rules 1, 2, 3 and 4: 1.2, 2.5, 3.9 and 4.6.

[0206]
Rule (H3). Select a grid spacing crosstalk protection scheme instead of a metal shielding crosstalk protection scheme where possible.

[0207]
Rule (H4). Protect the front part of a clock net rather than the end part if the fanout is greater than one, and if there are multiple net paths (s,t) having total clock delay dD timing violations.

[0208]
Rule (H5). Use a heuristic relaxation multiplier M for L_{p }having a value equal to a number a less than one if the clock net fanout is greater than a number b, where a and b are selected by the user.

[0209]
Rule (H6). Use a combination of partial crosstalk protection schemes to resolve a conflict among the rules, for example, select a grid spacing crosstalk protection scheme near the front (driver s) of the clock net and a metal shielding crosstalk protection scheme near the end of the clock net (receiver t).

[0210]
In general, for each clock net there are several adequate partial crosstalk protection schemes that may differ in their quality characteristics according to a quality function Q=<chip area A, clock skew S, maximum ramptime R_{max}, maximum propagation delay dD_{max}>.

[0211]
An intelligent engine for selecting the optimum partial crosstalk protection for a selected net that optimizes the quality function Q is described below. In this example, the intelligent engine prioritizes the factors that determine the quality function Q in the following order: chip area A (highest priority), clock skew S, maximum ramptime R_{max}, and maximum propagation delay dD_{max }(lowest priority).

[0212]
[0212]FIGS. 14A and 14B illustrates a flow chart 1400 for an intelligent engine according to an embodiment of the present invention.

[0213]
Step 1402 is the entry point of the flow chart 1400.

[0214]
In step 1404, the clock skew and net ramptime of a selected clock net are estimated from the synthesized clock tree by the clock tree analyzer as described above.

[0215]
In step 1406, a best solution variable is initialized with no crosstalk protection, and a minimum value Q_{min }of the quality function Q is initialized for the maximum possible values of chip area A, clock skew S, maximum ramptime R_{max}, and maximum propagation delay dD_{max}.

[0216]
In step 1408, an initial type of partial crosstalk protection is selected for the selected clock net and an initial location in the selected clock net for placing the partial crosstalk protection is selected according to the Hrules and selected rules from Rules 14 as described above.

[0217]
In step 1410, the incremental propagation delay dD_{up }without crosstalk protection is calculated for each path segment (s,t) in the selected clock net from the library of precharacterized crosstalk protection parameters.

[0218]
In step 1412, if the number of timing violations in which the incremental propagation delay dD_{up }without crosstalk protection exceeds the maximum propagation delay dD_{max }is equal to zero, then control is transferred to step 1434; else if the number of timing violations in which incremental propagation delay dD_{up }without crosstalk protection exceeds the maximum propagation delay dD_{max }is equal to one, then control is transferred to step 1414; else if the number of timing violations in which incremental propagation delay dD_{up }without crosstalk protection exceeds the maximum propagation delay dD_{max }is greater than one, then control is transferred to step 1426.

[0219]
In step 1414, a crosstalk protection scheme for the current path segment (s,t) is selected according to the library of precharacterized crosstalk protection parameters, for example, as described in the flow chart 1300 of FIG. 13.

[0220]
In step 1416, the value of the quality function Q is estimated using the current values of chip area A, clock skew S, maximum net ramptime R_{max}, and maximum propagation delay dD_{max}.

[0221]
In step 1418, if the value of the quality function Q estimated in step 1416 is less than the minimum value Q_{min}, then control is transferred to step 1420. Otherwise, control is transferred to step 1422.

[0222]
In step 1420, the best solution variable is set to the current partial crosstalk protection scheme, and the minimum value Q_{min }is set to the value of the quality function Q estimated in step 1416.

[0223]
In step 1422, if all types of partial crosstalk protection schemes and locations in the clock net for placing the crosstalk protection have been checked, then control transfers to step 1434. Otherwise, control is transferred to step 1424.

[0224]
In step 1424, another type of partial crosstalk protection scheme or another location for placing the current partial crosstalk protection scheme is selected, and control is transferred to step 1412.

[0225]
In step 1426, the current path segment (s,t) is set to the path segment having the maximum value of dD−dD_{max}.

[0226]
In step 1428, a crosstalk protection scheme for the current path segment (s,t) is selected from the library of precharacterized crosstalk protection parameters, for example, as described in the flow chart 1300 of FIG. 13.

[0227]
In step 1430, if the number of path segments (s,t) remaining in the selected clock net for which the incremental propagation delay dD exceeds the maximum propagation delay dD_{max }is equal to zero, then control is transferred to step 1432. Otherwise, control is transferred to step 1416.

[0228]
In step 1432, the current path segment (s,t) is set to the unprotected part of the net path (s,t) having the maximum value of dD−dD_{max}, and control is transferred to step 1428.

[0229]
In step 1434, the selected crosstalk protection scheme is generated as output.

[0230]
Step 1436 is the exit point of the flow chart 1400.

[0231]
When the intelligent engine loops through steps 1428, 1430 and 1432 to protect the remaining path segments having an incremental clock propagation delay dD timing violation, the intelligent engine can design a net path (s,t) having mixed types of partial crosstalk protection schemes.

[0232]
Although the methods of the present invention illustrated by the flowchart descriptions above are described and shown with reference to specific steps performed in a specific order, these steps may be combined, subdivided, or reordered without departing from the scope of the claims. Unless specifically indicated herein, the order and grouping of steps is not a limitation of the present invention.

[0233]
In another aspect of the present invention, the method illustrated in the flowchart description above may be embodied in a computer program product and implemented by a computer according to well known programming techniques to perform steps of:

[0234]
(a) receiving a synthesized signal path structure and a value of maximum allowable injected crosstalk delay for a selected net in the signal path structure;

[0235]
(b) analyzing the signal path structure to calculate a skew correction and a net ramptime for the selected net;

[0236]
(c) estimating an injected crosstalk delay of the selected net from a net aggressor; and

[0237]
(d) selecting a crosstalk protection scheme for the selected net to minimize chip area of the integrated circuit while ensuring that the injected crosstalk delay of the selected net does not exceed the value of maximum allowable injected crosstalk delay.

[0238]
While the invention herein disclosed has been described by means of specific embodiments and applications thereof, other modifications, variations, and arrangements of the present invention may be made in accordance with the above teachings other than as specifically described to practice the invention within the spirit and scope defined by the following claims.