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Publication numberUS20040256679 A1
Publication typeApplication
Application numberUS 10/463,142
Publication dateDec 23, 2004
Filing dateJun 17, 2003
Priority dateJun 17, 2003
Also published asUS7101747, US7759183, US20050250275, US20060263963
Publication number10463142, 463142, US 2004/0256679 A1, US 2004/256679 A1, US 20040256679 A1, US 20040256679A1, US 2004256679 A1, US 2004256679A1, US-A1-20040256679, US-A1-2004256679, US2004/0256679A1, US2004/256679A1, US20040256679 A1, US20040256679A1, US2004256679 A1, US2004256679A1
InventorsYongjun Hu
Original AssigneeHu Yongjun J.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Dual work function metal gates and method of forming
US 20040256679 A1
Abstract
Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconductor substrate conductively doped for PMOS and NMOS regions. The metal silicon compound overlying the NMOS region is converted to a metal silicon nitride and the metal silicon compound overlying the PMOS region is converted to a metal suicide. NMOS transistor gate electrodes comprising metal silicon nitride and PMOS transistor gate electrodes comprising metal suicide can be formed.
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Claims(20)
1-22. (Canceled)
23. A complementary transistor pair on a semiconductor assembly comprising:
an NMOS transistor gate electrode comprising metal silicon nitride; and
a PMOS transistor gate electrode comprising metal silicide.
24. The complementary transistor pair of claim 23, wherein the metal silicon nitride comprises a metal selected from the group consisting essentially of Ta, Hf, Mo or W.
25. The complementary transistor pair of claim 23, wherein the metal silicide comprises a metal selected from the group consisting essentially of Ta, Hf, Mo or W.
26. The complementary transistor pair of claim 23, wherein the metal silicon nitride comprises tantalum silicon nitride.
27. The complementary transistor pair of claim 23, wherein the metal silicide comprises tantalum disilicide.
28. The complementary transistor pair of claim 23, wherein the tantalum silicon nitride comprises a work function of approximately 4.2 eV to 4.3 eV.
29. The complementary transistor pair of claim 23, wherein the tantalum disilicide comprises a work function of approximately 4.8 eV.
30-51. (Canceled)
52. A semiconductor memory device having a complementary transistor pair comprising:
an NMOS transistor gate electrode comprising metal silicon nitride; and
a PMOS transistor gate electrode comprising metal silicide.
53. The semiconductor memory device of claim 52, wherein the metal silicon nitride comprises a metal selected from the group consisting essentially of Ta, Hf, Mo or W.
54. The semiconductor memory device of claim 52, wherein the metal silicide comprises a metal selected from the group consisting essentially of Ta, Hf, Mo or W.
55. The semiconductor memory device of claim 52, wherein the metal silicon nitride comprises tantalum silicon nitride.
56. The semiconductor memory device of claim 52, wherein the metal silicide comprises tantalum disilicide.
57. The semiconductor memory device of claim 52, wherein the tantalum silicon nitride comprises a work function of approximately 4.2 eV to 4.3 eV.
58. The semiconductor memory device of claim 52, wherein the tantalum disilicide comprises a work function of approximately 4.8 eV.
59-70. (Canceled)
71. A semiconductor memory device having a complementary transistor pair comprising:
an NMOS transistor gate electrode comprising tantalum silicon nitride; and
a PMOS transistor gate electrode comprising tantalum disilicide.
72. The semiconductor memory device of claim 71, wherein the tantalum silicon nitride comprises a work function of approximately 4.2 eV to 4.3 eV.
73. The semiconductor memory device of claim 71, wherein the tantalum disilicide comprises a work function of approximately 4.8 eV.
Description
    FIELD OF THE INVENTION
  • [0001]
    This invention relates to semiconductor devices and fabrication processes thereof. The invention particularly relates to complementary transistors having dual work function transistor gate electrodes and methods to fabricate same.
  • BACKGROUND OF THE INVENTION
  • [0002]
    Complementary Metal Oxide Semiconductor (CMOS) devices are dominated by n-channel (NMOS) and p-channel (PMOS) transistor structures. Various physical characteristics of each type of transistor determine the threshold voltage (Vt) that must be overcome to invert the channel region and cause a given transistor to conduct majority carriers (either by electrons movement in an NMOS device or by hole movement in a PMOS device).
  • [0003]
    One of the controlling physical characteristics is the work function of the material used to form the gate electrode of the transistor device. In semiconductor devices, such as a Dynamic Random Access Memory (DRAM) device, the transistor gates are predominantly made of polysilicon and an overlying layer of tungsten silicide. However, polysilicon transistor gates are prone to polysilicon depletion effects such as unwanted voltage drops that reduce transistor performance.
  • [0004]
    Metal gate technology presents an alternate approach for CMOS transistor devices in that the traditional polysilicon gate electrodes are replaced with metal or metal alloy electrodes. In order to substitute the traditional p-type or n-type polysilicon transistor gate with a metal or metal compound it is desirable to use metals that have similar work function characteristics in order to obtain a comparable transistor threshold voltage. N-type doped silicon has a work function of approximately 4.15 electron-volts (eV). Metals having a similar work function include aluminum (Al), manganese (Mn), zirconium (Zr), niobium (Nb), hafnium (Hf), and tantalum (Ta). P-type doped silicon has a work function of approximately 5.2 eV. Metals having a similar work function include nickel (Ni), cobalt (Co), platinum (Pt) and ruthenium (Ru).
  • [0005]
    Currently, in the semiconductor fabrication, there is a need for a metal that can be used to form both the gates of both n-channel and p-channel transistors in semiconductor devices, a need of which is addressed by the following disclosure of the present invention that will become apparent to those skilled in the art.
  • SUMMARY OF THE INVENTION
  • [0006]
    Exemplary implementations of the present invention include complementary transistors and methods of forming the complementary transistors on a semiconductor assembly by forming a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconductor substrate conductively doped for PMOS and NMOS regions, converting the metal silicon compound overlying the NMOS region to a metal silicon nitride by introducing nitrogen ions thereto while the metal silicon compound overlying the PMOS region is unexposed, converting the metal silicon compound overlying the PMOS region to a metal silicide by introducing silicon thereto during an annealing step while the metal silicon compound overlying the NMOS region is unexposed, forming an NMOS transistor gate electrode comprising metal silicon nitride and forming a PMOS transistor gate electrode comprising metal silicide.
  • BRIEF DESCRIPTION OF THE DRAWING
  • [0007]
    [0007]FIG. 1 is a cross-sectional view of a semiconductor substrate section showing the early stages of an semiconductor assembly having NWell and PWell regions formed in a silicon substrate partially separated by an isolation material, a gate dielectric layer formed over the Well regions and a tantalum silicon (TaSix) layer formed on the gate dielectric layer, according to one embodiment of the present invention.
  • [0008]
    [0008]FIG. 2 is a subsequent cross-sectional view taken from FIG. 1 following the masking of a portion of the TaSix layer, followed by the implantation of nitrogen ions into the TaSix layer to convert that layer to tantalum silicon nitride (TaSiN).
  • [0009]
    [0009]FIG. 3 is a subsequent cross-sectional view taken from FIG. 2 following the removal of the mask in FIG. 2 and the masking of the TaSiN portion, followed by the implantation of silicon ions during an anneal to transform the exposed TaSix layer to tantalum disilicide (TaSi2).
  • [0010]
    [0010]FIG. 4 is a subsequent cross-sectional view taken from FIG. 3 following removal of the mask in FIG. 3, which shows the TaSi2 and TaSiN materials adjacent one another.
  • [0011]
    [0011]FIG. 5 is a subsequent cross-sectional view taken from FIG. 4 following the completion of a complementary transistor pair having transistor gates that possess differing work function values.
  • [0012]
    [0012]FIG. 6 is an overhead plan view of FIG. 5 showing a completed complementary transistor pair of first embodiment of the present invention.
  • [0013]
    [0013]FIG. 7 is a subsequent cross-sectional view following the process steps depicted in FIGS. 1 and 2 showing a TaSix portion adjacent to a TaSiN portion.
  • [0014]
    [0014]FIG. 8 is a subsequent cross-sectional view taken from FIG. 6 following the formation of a silicon layer on the TaSix and TaSiN portions.
  • [0015]
    [0015]FIG. 9 is a subsequent cross-sectional view taken from FIG. 7 following an anneal step to convert the TaSix portion in to TaSi2.
  • [0016]
    [0016]FIG. 10 is a subsequent cross-sectional view taken from FIG. 6 following the completion of a complementary transistor pair having transistor gates that possess differing work function values.
  • [0017]
    [0017]FIG. 11 is an overhead plan view of FIG. 10 showing a completed complementary transistor pair of a second embodiment of the present invention.
  • [0018]
    [0018]FIG. 12 is a simplified block diagram of a semiconductor system comprising a processor and memory device to which the present invention may be applied.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0019]
    The following exemplary implementations are in reference to the complementary transistors and the formation thereof. While the concepts of the present invention are conducive to transistor structures for semiconductor memory devices, the concepts taught herein may be applied to other semiconductor devices that would likewise benefit from the use of the process disclosed herein. Therefore, the depictions of the present invention in reference to transistor structures for semiconductor memory devices are not meant to so limit the extent to which one skilled in the art may apply the concepts taught hereinafter.
  • [0020]
    In the following description, the terms “wafer” and “substrate” are to be understood as a semiconductor-based material including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, silicon-on-insulator, silicon-on-saphire, germanium, or gallium arsenide, among others.
  • [0021]
    A first exemplary implementation of the present invention is depicted in FIGS. 1-6. Referring now to FIG. 1, substrate 10, is processed to the point where NWell region 12 and PWell region 13 are formed in substrate 10. Isolation material 11 partially separates and electrically isolates the upper portions of the Well regions from one another. Dielectric material 14 is deposited over the surfaces of NWell region 12, PWell region 13 and isolation material 11.
  • [0022]
    Next, a film that is a metal silicon compound deficient of silicon bonding atoms in the form of Msix, where M═Ta, Hf, Mo or W and x<2, is deposited for example by Physical Vapor Deposition (PVD), by Chemical Vapor Deposition (CVD), or by Atom Layer Deposition (ALD). It is preferred that the value of “x” is in the range of 0.4≦x≦1.0 and it is further preferred that the material deposited is TaSix, such as TaSi0.6.
  • [0023]
    Using TaSi0.6 as a preferred material, a TaSi0.6 layer 15 is formed on dielectric material 14. The NWell and PWell regions can be formed either before or after the formation of gate dielectric layer 14 and TaSi0.6 layer 15. The TaSi0.6 layer is deposited from a TaSi0.6 source by methods know to those skilled in the art. Dielectric material 14 will eventually serve as the gate dielectric for the subsequently formed transistor structures and is preferably a dielectric material possessing a high dielectric constant of at least seven or more, such nitride or metal oxides (i.e., Al2O3, SiO2/Al2O3 and Al2O3/HfOx) so the gate dielectric layer remains significantly thin. However, a material having a lower dielectric constant (around 3.8), such as silicon dioxide, may be used. The thickness of the silicon dioxide layer would have to be scaled in thickness in order to provide proper gate to channel separation.
  • [0024]
    Referring now to FIG. 2, a mask material 20, such as photoresist, is patterned to cover the portion of the TaSi0.6 layer 15 that overlies NWell region 12. Next, nitrogen ions (N+) are presented to (i.e., implanted) the uncovered portion of TaSi0.6 layer 15 to covert that portion of TaSi0.6 to tantalum silicon nitride (TaSiN) 30 as seen in FIG. 3.
  • [0025]
    Referring now to FIG. 3, a mask material 31, such as photoresist, is patterned to cover the portion of the TaSi0.6 layer 15 that overlies PWell region 13. Next, silicon ions (Si+) are presented to (i.e., implanted) the uncovered portion of TaSi0.6 layer 15, followed by rapid thermal processing (RTP) of approximately 600 C. for approximately 30 seconds, to covert that portion of TaSi0.6 layer 15 to tantalum disilicide (TaSi2) 40 as seen in FIG. 4. The low RTP temperature of 600 C. is sufficient to form fully crystallized TaSi2, which is well below 800 C., a temperature at which the nitrogen would begin to significantly denude out of the TaSiN. The RTP step of 600 C. for 30 seconds is preferred, however, the RTP temperature could range from 550 C. to 800 C. and the duration could range from 20 seconds to 30 minutes. (The RTP processing may be, in general, considered as an annealing step.)
  • [0026]
    Referring now to FIG. 4, TaSi2 40 and TaSiN 30 are shown adjacent one another and overlying NWell 11 and PWell 12, respectively. As now evident in FIG. 4, the presence of the original TaSi0.6 layer is a key step in providing a method to convert this material into two separate materials, namely TaSi2 and TaSiN, by the separate masking and implantation steps discussed in FIGS. 2 and 3.
  • [0027]
    Referring now to FIG. 5, a complementary pair of completed transistor structures having dual work function gates is depicted. Both transistors are formed using conventional fabrication techniques to pattern and etch each transistor gate, followed by implanting the source and drain regions 50 to a p-type conductivity to form a p-channel transistor and implanting the source drain regions 51 to an n-type conductivity to form an n-channel transistor. Completed transistor gate 54 comprises insulation (such as nitride) spacers 52 and cap 53 that provide physical isolation for TaSi2 gate 40. In like manner, completed transistor gate 55 comprises insulation (such as nitride) spacers 52 and insulation cap 53 that provide physical isolation for TaSiN gate 30. The gate material for each transistor exhibits a differing work function as the TaSi2 gate will have a work function of 4.8 eV, while TaSiN gate will have a work function of 4.2 eV to 4.3 eV.
  • [0028]
    [0028]FIG. 6 depicts an overhead view of a completed complementary pair of transistor structures having dual work function gates as described in the process steps taken in FIG. 1-5. As shown in FIG. 6, substrate 10 has been implanted with conductive dopants to form NWell 11 and PWell 12. Completed transistor gate 54 comprises insulation spacers 52 and cap 53 that provide physical isolation for TaSi2 gate 40 (not seen). In like manner, completed transistor gate 55 comprises insulation spacers 52 and insulation cap 53 that provide physical isolation for TaSiN gate 30 (not seen). The source and drain regions 50 are implanted with a p-type conductivity to form a p-channel transistor and the source drain regions 51 are implanted with to an n-type conductivity to form an n-channel transistor.
  • [0029]
    A second exemplary implementation of the present invention is depicted in FIGS. 1-2 and 7-11. Referring now to FIG. 7, process steps, as taught for FIGS. 1 and 2, are performed to create TaSi0.6 portion 15 and TaSiN portion 30 on dielectric material 14 overlying NWell region 12 and PWell region 13, respectively. The process steps of FIGS. 1 and 2 are not repeated to avoid redundant disclosure.
  • [0030]
    Referring now to FIG. 8, a polysilicon layer 80 is deposited directly on TaSi0.6 portion 15 and TaSiN portion 30. Polysilicon layer 80 will provide a source of silicon atoms for a subsequent material conversion step.
  • [0031]
    Referring now to FIG. 9, the semiconductor assembly is subjected to a rapid thermal anneal (in one embodiment at a temperature of 650 C. for 30 seconds), which causes silicon atoms to diffuse into the silicon starved TaSi0.6 portion 15 (of FIG. 8) and form TaSi2 portion 91. The TaSiN remains the same as it is a stable compound that does not require any additional silicon atoms. As in the first exemplary implementation of the present invention, two metallic materials TaSi2 and TaSiN are formed side-by-side and each metallic material possesses a different work function value where TaSi2 is known to have work function of 4.8 eV, while TaSiN has a work function of 4.2 eV to 4.3 eV.
  • [0032]
    Referring now to FIG. 10, a complementary pair of completed transistor structures having dual work function gates is depicted. Both transistors are formed using conventional fabrication techniques to pattern and etch each transistor gate, followed by implanting the source and drain regions 100 with a p-type conductivity to form a p-channel transistor and implanting the source drain regions 101 with an n-type conductivity to form an n-channel transistor. Completed transistor gate 104 comprises insulation (such as nitride) spacers 102 and cap 103 that provide physical isolation for TaSi2 gate 40. In like manner, completed transistor gate 105 comprises insulation (such as nitride) spacers 102 and cap 103 that provide physical isolation for TaSiN gate 30. The gate material for each transistor exhibits a differing work function as the TaSi2 gate will have a work function of 4.8 eV, while TaSiN gate will have a work function of 4.2 eV to 4.3 eV.
  • [0033]
    [0033]FIG. 11 depicts an overhead view of a completed complementary pair of transistor structures having dual work function gates as described in the process steps taken in FIG. 1-2 and 7-10. As shown in FIG. 11, substrate 10 has been implanted with conductive dopants to form NWell 11 and PWell 12. Completed transistor gate 104 comprises insulation spacers 102 and cap 103 that provide physical isolation for TaSi2 gate 40 (not seen). In like manner, completed transistor gate 105 comprises insulation spacers 102 and insulation cap 103 that provide physical isolation for TaSiN gate 30 (not seen). The source and drain regions 100 are implanted with a p-type conductivity to form a p-channel transistor and the source drain regions 101 are implanted with an n-type conductivity to form an n-channel transistor.
  • [0034]
    Exemplary implementations of the present invention present two alternative methods of forming dual work function gates that allows the use of a gate annealing temperature that is well below the temperature at which nitrogen will begin denuding out of TaSiN, which is approximately 800 C. It is important to stay at an annealing temperature of around 800 C. or less as the nitrogen will significantly denude out of the TaSiN, thus altering the work function of the metallic material.
  • [0035]
    The exemplary embodiments have been discussed in reference to forming a complementary transistor pair for use in CMOS applications, such as memory devices. However, these concepts, taught in the exemplary embodiments, may be utilized by one of ordinary skill in the art to form complementary transistor pairs for use in most all CMOS applications. For example, the present invention may be applied to a semiconductor system, such as the one depicted in FIG. 12, the general operation of which is known to one skilled in the art.
  • [0036]
    [0036]FIG. 12 represents a general block diagram of a semiconductor system comprising a processor 120 and a memory device 121 showing the basic sections of a memory integrated circuit, such as row and column address buffers, 123 and 124, row and column decoders, 125 and 126, sense amplifiers 127, memory array 128 and data input/output 129, which are manipulated by control/timing signals from the processor through control 122.
  • [0037]
    It is to be understood that, although the present invention has been described with reference to two exemplary embodiments, various modifications, known to those skilled in the art, may be made to the disclosed structure and process herein without departing from the invention as recited in the several claims appended hereto.
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Classifications
U.S. Classification257/371, 438/223, 257/E21.637
International ClassificationH01L21/8238
Cooperative ClassificationH01L21/823835, H01L21/823842
European ClassificationH01L21/8238G2, H01L21/8238G4
Legal Events
DateCodeEventDescription
Jun 17, 2003ASAssignment
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HU, YONGJUN J.;REEL/FRAME:014206/0274
Effective date: 20030611