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Publication numberUS20040257839 A1
Publication typeApplication
Application numberUS 10/465,161
Publication dateDec 23, 2004
Filing dateJun 18, 2003
Priority dateJun 18, 2003
Also published asCN1806380A, CN1806380B, US6836415, WO2004112227A1
Publication number10465161, 465161, US 2004/0257839 A1, US 2004/257839 A1, US 20040257839 A1, US 20040257839A1, US 2004257839 A1, US 2004257839A1, US-A1-20040257839, US-A1-2004257839, US2004/0257839A1, US2004/257839A1, US20040257839 A1, US20040257839A1, US2004257839 A1, US2004257839A1
InventorsTa-Yung Yang, Chern-Lin Chen, Jenn-yu Lin, Song-Yi Lin
Original AssigneeTa-Yung Yang, Chern-Lin Chen, Lin Jenn-Yu G., Song-Yi Lin
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Primary-side regulated pulse width modulation controller with improved load regulation
US 20040257839 A1
Abstract
The present invention provides a primary-side regulated PWM controller with improved load regulation. In every PWM cycle, a built-in feedback voltage samples and holds a flyback voltage from the auxiliary winding of the transformer via a sampling switch and generates a feedback voltage accordingly. A bias current sink pulls a bias current that is proportional to the feedback voltage. Via a detection resistor, the bias current will produce a voltage drop to compensate the voltage drop of an output rectifying diode as the output load changes. According to the present invention, the bias current can enable the PWM controller to regulate the output voltage very precisely without using a secondary feedback circuit.
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Claims(15)
What is claimed is:
1. A primary-side PWM controller in a switch mode power supply, said primary-side PWM controller comprising:
a DET input terminal for detecting a flyback voltage of an auxiliary winding of a transformer of said switch mode power supply, wherein said DET input terminal is connected to said auxiliary winding via a detection resistor;
a bias current sink for pulling a bias current from said DET input terminal;
a sampling switch controlled by a sampling pulse signal;
a sampler circuit for generating said sampling pulse signal;
a feedback voltage generator for generating a feedback voltage, wherein said feedback voltage generator is connected to said DET input terminal via said sampling switch; and
a pulse-width modulator for generating a PWM signal in response to said feedback voltage, wherein said PWM signal operates a switch coupled to a primary winding of said transformer.
2. The primary-side PWM controller according to claim 1, wherein said PWM controller operates to regulate an output voltage of said switch mode power supply.
3. The primary-side PWM controller according to claim 1, wherein the magnitude of said feedback voltage is inversely proportional to the magnitude of said output voltage.
4. The primary-side PWM controller according to claim 1, wherein the amplitude of said bias current is proportional to the magnitude of said feedback voltage.
5. The primary-side PWM controller according to claim 1, wherein said bias current sink comprises:
a first resistor;
a first transistor for converting said feedback voltage into a feedback current, wherein said first transistor has a source connected to the ground reference via said first resistor;
a first input buffer amplifier for controlling a gate of said first transistor, wherein said first input buffer amplifier has a positive input coupled to said feedback voltage and a negative input connected to the ground reference via said first resistor;
a first current mirror coupled to the supply voltage and a drain of said first transistor; and
a second current mirror for pulling said bias current, wherein said second current mirror is coupled to said first current mirror and the ground reference.
6. The primary-side PWM controller according to claim 1, wherein the amplitude of said bias current is proportional to the amplitude of said feedback current.
7. The primary-side PWM controller according to claim 1, wherein said feedback voltage generator comprises:
a second resistor;
a second input buffer amplifier having a positive input coupled to said flyback voltage via said sampling switch, wherein said second input buffer amplifier has a negative input coupled to said second resistor;
a third input buffer amplifier having a positive input connected to a first reference voltage and a negative input, wherein said negative input is coupled to an output of said third input buffer amplifier and said second resistor;
a first capacitor for sampling and holding said flyback voltage to generate a sampled voltage, wherein said first capacitor is connected to the ground reference and said positive input of said second input buffer amplifier;
a second transistor for converting said sampled voltage into a sampled current, wherein said second transistor has a gate connected to an output of said second input buffer amplifier and a source connected to said output of said third input buffer amplifier via said second resistor;
a third current mirror coupled to the supply voltage and a drain of said second transistor;
a fourth current mirror for generating a mirrored sampled current, wherein said fourth current mirror is coupled to said third current mirror and the ground reference; and
a third resistor for generating said feedback voltage from said mirrored sampled current, wherein said third resistor is coupled to said fourth current mirror and a second reference voltage.
8. The primary-side PWM controller to claim 7, wherein said mirrored sampled current is inversely proportional to said flyback voltage.
9. The primary-side PWM controller according to claim 1, wherein said sampler circuit comprises:
a first current source for generating a first charge current, wherein said first current source is coupled to the supply voltage;
a second capacitor coupled to the ground reference, wherein said second capacitor is charged by said first charge current;
a third transistor for switching said first charge current, wherein said third transistor has a gate controlled by said PWM signal, a drain coupled to said first current source and a source connected to the ground reference;
a first hysteresis comparator has an input terminal connected to said drain of said third transistor; and
a first NOT-gate for generating a delay-time signal, wherein said NOT-gate has an input connected to an output of said first hysteresis comparator.
10. The primary-side PWM controller according to claim 1, wherein said sampler circuit further comprises:
a second current source for generating a second charge current, wherein said second current source is connected to the supply voltage;
a third capacitor coupled to the ground reference, wherein said third capacitor is charged by said second charge current;
a fourth transistor for switching said second charge current, wherein said fourth transistor has a drain coupled to said second current source and a source connected to the ground reference;
a first NAND-gate for controlling a gate of said fourth transistor, wherein said first NAND-gate has a first input coupled to said delay-time signal;
a second NOT-gate for supplying an inverted PWM signal to a second input of said first NAND-gate, wherein said second NOT-gate has an input coupled to said PWM signal; and
a second hysteresis comparator for generating a sample-time signal, wherein said second hysteresis comparator has an input coupled to said third capacitor.
11. The primary-side PWM controller according to claim 1, wherein said sampler circuit further comprises:
a second NAND-gate for generating an inverted sampling pulse signal, wherein said second NAND-gate has a first input coupled to said delay-time signal, a second input coupled to said inverted PWM signal and a third input coupled to said sample-time signal; and
a third NOT-gate for generating said sampling pulse signal, wherein said third NOT-gate having an input connected to an output of said second NAND-gate.
12. The primary-side PWM controller according to claim 11, wherein a delay time of said sampling pulse signal is a function of the capacitance of said second capacitor and the amplitude of said first charge current, wherein said delay time occurs after the falling-edge of each PWM cycle.
13. The primary-side PWM controller according to claim 11, wherein a pulse width of said sampling pulse signal is a function of the capacitance of said third capacitor and the amplitude of said second charge current, wherein said sampling pulse signal is generated after said delay time.
14. The switch mode power supply according to claim 1, wherein said pulse-width modulator comprises:
a comparator for generating an reset signal, wherein said comparator has a positive input connected to said feedback signal and a negative input connected to a sense voltage, wherein said sense voltage is converted from a primary current of said transformer;
an oscillator for generating a pulse signal;
a RS flip-flop for generating an on-off signal, wherein said RS flip-flop is set by said pulse signal and reset by an output of said comparator;
an AND-gate for generating said PWM signal, said AND-gate having a first input connected to said pulse signal and a second input connected to said on-off signal.
15. The primary-side PWM controller according to claim 14, wherein a frequency of said oscillator determines a switching frequency of said PWM signal.
Description
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a switching mode power supply, and more particularly relates to a primary-side regulated pulse width modulation (PWM) controller of a switching mode power supply.

[0003] 2. Description of Related Art

[0004] Switching mode power supplies (SMPS) are commonly used as primary power supplies for computers, telecom devices, and many other products. SMPS designs have many advantages over other types of power supplies, including more efficient power conversion, smaller size, and lighter weight. However, the mass component counts of SMPS designs are still a problem for power supply manufacturers and engineers. Some solutions are provided in the art without secondary-side feedback control, in order to reduce the production costs of the power supply. The applicant of the present invention filed a corresponding patent application in United States, which was titled PWM controller regulating output voltage and output current in primary side, filed on Mar. 24, 2003 and assigned Ser. No. 10/249,214. All disclosures therein are incorporated herewith. In the corresponding application, as shown in FIG. 1, a flyback power supply without secondary-side feedback control is disclosed. This design couples the output voltage and the supply voltage via a main transformer, so that the supply voltage can be used for voltage regulation, while the output voltage is maintained within a fixed range. The output voltage can be regulated without a secondary-side feedback circuit, so the system cost can be reduced.

[0005] However, the load regulation in the invention is not considered. The precision of the load regulation deteriorates as the power supply load increases. At higher loads, the feedback signal from the auxiliary winding of the main transformer does not precisely follow the output voltage of the power supply. This happens because the rectifying diode of the auxiliary winding feedback signal causes a voltage drop proportional to the load current. FIG. 2A and FIG. 2B demonstrate the adverse effect of the rectifying diode (FIG. 1: D1) on load regulation in the corresponding patent application shown in FIG. 1. As the load current increases, so does the supply current of the auxiliary winding (ICC). This causes an increased voltage drop across the rectifying diode. Thus, as the power supply load changes, the relationship of the feedback signal (VCC) to the auxiliary winding voltage (V1) and output voltage (V2) will change. To those skilled in the art, it can be seen that because of the rectifying diode D1, the differential voltages ΔVCL (light load) and ΔVCH (heavy load) will not be identical. Thus the feedback signal (VCC) does not precisely follow variations to the transformer voltage. The voltage regulation of the prior-art primary-side power supply is not consistent for all power supply loads.

[0006] Furthermore, a heavy load current will also result in a larger voltage drop across the output rectifying diode (FIG. 1: D2). Though the auxiliary winding voltage is correlated with the secondary winding voltage, the correlation weakens as the power supply load current increases. This results in a further load regulation problem.

[0007] Traditional primary-side PWM controllers can reduce production costs, but they have poor load regulation. Therefore, there is a need for an improved primary-side PWM controller that is suitable for a wider range of power supply output load levels.

SUMMARY OF THE INVENTION

[0008] A principal object of the present invention is to provide a primary-side regulated PWM controller with improved load regulation over prior-art designs. The PWM controller uses a bias current that is modulated in response to different output loads to generate different voltage drops across a detection resistor to compensate for the variation of the voltage drop across the output rectifying diode.

[0009] According to one aspect of the present invention, voltage regulation is further improved by the addition of a feedback voltage generator. A feedback voltage generator detects the flyback voltage from the auxiliary winding during each PWM cycle via the control of a sampler circuit. A sampling pulse signal generated by the sampler circuit is synchronized by a PWM signal. Cycle-by-cycle monitoring the voltage at the auxiliary winding enables feedback control to be performed more precisely. The present invention substantially improves the stability of the output voltage with respect to load changes.

[0010] According to another aspect of the present invention, voltage regulation is further improved by properly selecting the detection resistor to accurately offset the voltage drop for different types of output rectifying diode. Since the voltage drop of the detection resistor is correlated with the voltage drop of the output rectifying diode, this improves the load regulation of the output voltage under changing load conditions.

[0011] Another object of the present invention is to reduce production costs. The primary-side feedback control apparatus according to the present invention eliminates the need for secondary-side feedback control circuitry. Therefore the device count, the size of the power supply, and the production cost can be greatly reduced.

[0012] According to an aspect of the present invention, the PWM controller with primary side regulation can improve load regulation and output voltage accuracy, while reducing production costs.

[0013] It is to be understood that both the foregoing general descriptions and the following detailed descriptions are exemplary, and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

[0015]FIG. 1 shows a prior-art PWM controller regulating the output voltage and the output current from the primary side of the transformer.

[0016]FIG. 2A shows the waveforms observed from the auxiliary winding and the secondary winding under light load conditions.

[0017]FIG. 2B shows the waveforms observed from the auxiliary winding and the secondary winding under heavy load conditions.

[0018]FIG. 3 shows a flyback power supply using a primary-side regulated PWM controller according to the present invention.

[0019]FIG. 4 shows the schematic diagram of the primary-side regulated PWM controller according to the present invention.

[0020]FIG. 5 shows a preferred embodiment of a feedback voltage generator and a bias current sink shown in FIG. 4, according to the present invention.

[0021]FIG. 6 shows a preferred embodiment of a sampler circuit shown in FIG. 4, according to the present invention.

[0022]FIG. 7 shows the waveform observed from the sampler circuit of FIG. 6, according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023]FIG. 3 shows a flyback power supply using a primary-side regulated PWM controller 101 according to the present invention. V1 is the flyback voltage of an auxiliary winding of a transformer 400. V2 is the flyback voltage of a secondary winding of the transformer 400. The auxiliary winding supplies the supply voltage VCC through a rectifying diode D1 while the PWM controller 101 is operating. The flyback voltage V1 of the auxiliary winding can be expressed by, V 1 = N A φ t ( 1 )

[0024] where NA is the turn number of the auxiliary winding and φ is the magnetic flux of the transformer 400.

[0025] The flyback voltage V2 of the secondary winding can be expressed by, V 2 = N S φ t ( 2 )

[0026] where NS is the turn number of the secondary winding, From equations (1) and (2), then V 1 = N A N S V 2 ( 3 )

[0027] As observed above, the flyback voltage V1 of the auxilliary winding is correlated with the flyback voltage V2 Since the flyback voltage of the auxiliary winding is correlated with the voltage of the secondary winding, the feedback control circuit can be built at the primary-side (auxiliary winding side) of the transformer 400.

[0028]FIG. 4 shows a detailed view of the PWM controller 101 according to the present invention. The PWM controller 101 comprises a feedback voltage generator 37, a bias current sink 36, a sampler circuit 31, a sampling switch 50 and a pulse-width modulator 38. A detection input DET of the PWM controller 101 is connected to a detection resistor 200 shown in FIG. 3. The input terminal of the sampling switch 50 is connected to the detection input DET. The output terminal of the sampling switch 50 is connected to an input of the feedback voltage generator 37. The feedback voltage generator 37 outputs a feedback voltage VFB, which is connected to an input of the bias current sink 36 and a first input of the pulse-width modulator 38. A second input of the pulse-width modulator 38 is a current-sense input VS of the PWM controller 101. The current-sense input VS is coupled to a sense resistor 210, which is connected to the source of a power MOSFET 300 shown in FIG. 3. An output of the pulse-width modulator 38 outputs a PWM signal to switch the power MOSFET 300. The sampler circuit 31 is driven by the output of the pulse-width modulator 38 and generates a sampling pulse signal SP. The sampling pulse signal SP is further connected to a control terminal of the sampling switch 50.

[0029] The pulse-width modulator 38 comprises a comparator 35, a RS flip-flop 34, an oscillator 32, and an AND-gate 33. The oscillator 32 generates a pulse signal Vp. The pulse signal Vp sets a set-input of the RS flip-flop 34 and is connected to a first input of the AND-gate 33. A positive input of the comparator 35 is the first input of the pulse-width modulator 38. A negative input of the comparator 35 is the second input of the pulse-width modulator 38. An output of the comparator 35 is connected to a reset-input of the RS flip-flop 34. An output of the RS flip-flop 34 is connected to a second input of the AND-gate 33. The AND-gate 33 output the PWM signal.

[0030] Since both flyback voltages V1 and V2 are correlated with the output load conditions, the flyback voltage V1 can reflect the output load status. Thus, the PWM controller 101 can detect the output load status from the primary side of the transformer 400. As load changes, the flyback voltage V1 of the auxiliary winding of the transformer 400 is sampled and held by the feedback voltage generator 37 via the sampling switch 50 and the detection resistor 200. The feedback voltage generator 37 will generate the feedback voltage VFB in response to the flyback voltage V1. As the voltage VS at the current-sense input VS is higher than the feedback voltage VFB, the PWM signal will be turned off. In the meantime, the bias current sink 36 will sink a bias current IM in response to the feedback voltage VFB. As load changes, the output current 10 will generate different voltage drops across the output rectifying diode. The bias current IM will generate different voltage drops across the detection resistor 200 to well compensate the different voltage drops across the output rectifying diode.

[0031]FIG. 5 shows one preferred embodiment of the feedback voltage generator 37 and the bias current sink 36 according to the present invention. The feedback voltage generator 37 comprises a capacitor 51, an operational amplifier (OPA) 52, an OPA 53, a transistor 56, a first current mirror composed of a transistor 54 and a transistor 55, a second current mirror composed of a transistor 58 and a transistor 59, a resistor 57 and a resistor 60. The capacitor 51 is connected between a positive input of the OPA 52 and a ground reference. An output of the OPA 52 is connected to a gate of the transistor 56. A negative input of the OPA 52 is connected to a source of the transistor 56. A first reference voltage VR1 is connected to a positive input of the OPA 53. A negative input of the OPA 53 is connected to an output of the OPA 53. The resistor 57 is connected between the negative input of the OPA 52 and the negative input of the OPA 53. The sources of the transistors 54 and 55 are connected to the supply voltage VCC. A gate of the transistor 54, a gate of the transistor 55, a drain of the transistor 54 and a drain of the transistor 56 are tied together. A drain of the transistor 55, a drain of the transistor 58, a gate of the transistor 58 and a gate of the transistor 59 are tied together. A source of the transistors 58 and a source of the transistor 59 are both connected to the ground reference. The resistor 60 is connected between a second reference voltage VR2 and a drain of the transistor 59. The feedback voltage VFB is derived from the drain of the transistor 59.

[0032] The bias current sink 36 comprises an OPA 61, a transistor 64, a resistor 65, a third current mirror composed of a transistor 62 and a transistor 63 and a fourth current mirror composed of a transistor 66 and a transistor 67. A positive input of the OPA 61 is connected to the drain of the transistor 59. An output of the OPA 61 is connected to a gate of the transistor 64. A negative input of the OPA 61 is connected to a source of the transistor 64. The resistor 65 is connected between the source of the transistor 64 and the ground reference. A drain of the transistor 62, a drain of the transistor 64, a gate of the transistor 62, and a gate of the transistor 63 are tied together. A source of the transistor 62 and a source of the transistor 63 are connected to the supply voltage VCC. A drain of the transistor 63, a drain of the transistor 66, a gate of the transistor 66 and a gate of the transistor 67 are tied together. A source of the transistor 66 and a source of the transistor 67 are connected to the ground reference. A drain of the transistor 67 is connected to the detection input DET to pull the bias current IM.

[0033] Referring to FIG. 3, when the output voltage VO decreases due to an increase in the load, the flyback voltage V2 of the secondary winding will be reduced. Because the flyback voltages of the auxiliary winding and the secondary winding are correlated, the reduction in the flyback voltage V1 will be proportional to the reduction in the flyback voltage V2. The flyback voltage V1 is coupled via the detection resistor 200 to the detection input DET of the PWM controller 101. The PWM signal drives the sampler circuit 31 to generate the sampling pulse signal SP to switch the sampling switch 50.

[0034] Further referring to FIG. 5, once the sampling switch 50 is turned on, the flyback voltage V1 will charge the capacitor 51 of the feedback voltage generator 37. A sampled voltage VSP can be obtained from the capacitor 51. The transistor 56 converts the sampled voltage VSP into a sampled current ISP, which can be expressed by the following equation,

I SP=(V SP −V R1)/R 57   (4)

[0035] where VR1 is the first reference voltage and R57 is the resistance of the resistor 57.

[0036] A first current mirror mirrors a first current I1, which can be expressed by the following equation,

I 1 =N 1 I SP   (5)

[0037] where N1 is the mirror ratio of the first current mirror.

[0038] A second current mirror mirrors a second current I2, which can be expressed by the following equation,

I 2 =N 2 I 1   (6)

[0039] where N2 is the mirror ratio of the second current mirror.

[0040] The feedback voltage VFB derived from the drain of the transistor 59 can be expressed by the following equation,

V FB =V R2 −I 2 R 60   (7)

[0041] where VR2 is the second reference voltage, and R60 is the resistance of the resistor 60.

[0042] The equations (4), (5), (6), and (7) show that as the load increases, the sampled voltage VSP will decrease, and the sampled current ISP will decreases too. The second current I2 will decrease, and an increased feedback voltage VFB will then be obtained. While the feedback voltage VFB is high, the on-time of the PWM signal will be extended to provide more power, to meet the needs of the increased load. The increased feedback voltage VFB is then converted into an increased feedback current IFB by the transistor 64.

[0043] Through a third current mirror, the increased feedback current IFB is mirrored into a third current I3, which can be expressed by the following equation,

I 3 =N 3 I FB   (8)

[0044] where N3 is the mirror ratio of the third current mirror.

[0045] A fourth current mirror pulls the bias current IM, which is proportional to the third current I3, wherein

I M =N 4 I 3   (9)

[0046] where N4 is the mirror ratio of the fourth current mirror.

[0047] The equations (7), (8), and (9) show that the bias current IM varies in direct proportion to the feedback voltage VFB. The output voltage is VO=V2−VD2, where VD2 is the voltage drop across the output rectifying diode D2

[0048] The flyback voltage V1 of the auxiliary winding can be expressed by the following equation,

V 1 =V RDET +V DET   (10)

[0049] where VRDET is the voltage drop across the detection resistor 200, and VDET is the voltage of the detection input DET.

[0050] Thus, V O = N S N A ( V RDET + V DET ) - V D2 ( 11 )

[0051] Select V D2 = N S N A V RDET = N S N A ( I M R DET ) then V O = N S N A V DET

[0052] Because VDET=K1VSP, if the resistance of the resistor 57 is small, then the result can be approximated as VSP=VR1. Therefore, a desired output voltage VO can be obtained and its voltage will not be affected by various load conditions. It will be expressed by the following equation: V O = N S N A K I V RI

[0053] where K1 is a constant, and the resistor 57 is used to reduce the feedback loop gain.

[0054] According to the present invention, the detection resistor 200 and the bias current IM compensate for variations to the voltage drop VD2 under different load conditions. Under heavy load conditions, the bias current IM will increase and generate a higher voltage drop VRDET. Thus, the flyback voltage V1 will increase to compensate for the high voltage drop VD2. Under light load conditions, the bias current IM will decrease and generate a lower voltage drop VRDET, to compensate for the low voltage drop VD2. Although different types of output rectifying diode D2 will generate different voltage drops VD2, proper selection of the resistor 200 (RDET) will accurately offset the voltage drop VD2 for different types of output rectifying diode D2.

[0055]FIG. 6 shows one preferred embodiment of the sampler circuit 31, which comprises a transistor 81, a transistor 89, a current source 80, a current source 90, a capacitor 82, a capacitor 91, a hysteresis comparator 83, a hysteresis comparator 92, a NOT-gate 84, a NOT-gate 87, a NOT-gate 86, a NAND gate 85 and a NAND gate 88. A gate of the transistor 81 is connected to the output of the AND-gate 33 shown in FIG. 4 and an input of the NOT-gate 87. A source of the transistor 81 is connected to the ground reference. The current source 80 is connected between the supply voltage VCC and a drain of the transistor 81. The drain of the transistor 81 is further connected to an input of the hysteresis comparator 83. The capacitor 82 is connected between the drain of the transistor 81 and the ground reference. An output of the hysteresis comparator 83 is connected to an input of the NOT-gate 84. An output of the NOT-gate 84 is connected to a first input of the NAND-gate 85 and a first input of the NAND-gate 88. An output of the NOT-gate 87 is connected to a second input of the NAND-gate 85 and a second input of the NAND-gate 88. An output of the NAND-gate 85 is connected to an input of the NOT-gate 86. An output of the NOT-gate 86 supplies the sampling pulse signal SP to the control terminal of the sampling switch 50. An output of the NAND-gate 88 is connected to a gate of the transistor 89. A source of the transistor 89 is connected to the ground reference. A current source 90 is connected between the supply voltage VCC and a drain of the transistor 89. An input of the hysteresis comparator 92 is connected to the drain of the transistor 89. The capacitor 91 is connected between the drain of the transistor 89 and the ground reference. An output of the hysteresis comparator 92 is connected to a third input of the NAND-gate 85.

[0056] As the PWM signal coupled to the gate of the transistor 81 becomes logic-high, the transistor 81 will be turned on and the current source 80 will be grounded. No current will flow into the capacitor 82. The output of the hysteresis comparator 83 will be logic-high. The NOT-gate 84 converts this logic-high signal and outputs a logic-low signal to set the output of the NAND-gate 85 to logic-high. The NOT-gate 86 converts this logic-high signal and outputs a logic-low sampling pulse signal SP. The logic-low sampling pulse signal SP will keep the sampling switch 50 shown in FIG. 5 open, so that the flyback voltage of the auxiliary winding will not be conducted to the feedback voltage generator 37. Once the PWM signal becomes logic-low, the second input of the NAND-gate 88 will become logic-high. In the meantime, the transistor 81 will be turned off, and the current source 80 will start to charge the capacitor 82. Until the voltage in the capacitor 82 reaches the upper-threshold voltage VUT1 of the hysteresis comparator 83, the first input of the NAND-gate 88 will remain logic-low. Thus, the output of the NAND-gate 88 will be logic-high, which will ground the current source 90. The hysteresis comparator 92 will output a logic-high signal to the third input of the NAND-gate 85. The output of the NOT-gate 86 will remain logic-low. The current source 80 will charge the capacitor 82 continuously, and generates a delay time td starting from the falling-edge of the PWM signal. Since Q=CV=It, the delay time td can be expressed by the following equation, t d = C 82 V UT 1 I 80 ( 12 )

[0057] where C82 is the capacitance of the capacitor 82, VUT1 is the upper-threshold voltage of the hysteresis comparator 83, and I80 is the current of the current source 80.

[0058] As the voltage in the capacitor 82 reaches the upper-threshold voltage VUT1 of the hysteresis comparator 83, the output of the NOT-gate 84 will become logic-high. Therefore, the NOT-gate 86 will output a logic-high sampling pulse signal SP in response to the end of the delay time td. Meanwhile, both of the two inputs of the NAND-gate 88 will be logic-high. This will make the output of the NAND-gate 88 become logic-low. Thus, the transistor 89 will be turned off and the current source 90 will start to charge the capacitor 91, and determine a sample time tS for the pulse width of the sampling pulse signal SP. The following equation can express the charge of the capacitor 91: t S = C 91 V UT 2 I 90 ( 13 )

[0059] where C91 is the capacitance of the capacitor 91, VUT2 is the upper-threshold voltage of the hysteresis comparator 92, and I90 is the current of the current source 90.

[0060] Until the voltage of the capacitor 91 reaches the upper-threshold voltage VUT2, the output of the hysteresis comparator 92 will remain logic-high and the sampling pulse signal SP will remain logic-high as well. After the sample time tS the hysteresis comparator 92 will output a logic-low signal to the third input of the NAND-gate 85. Thus, the sampling pulse signal SP becomes logic-low. The correlation of the sampling pulse signal SP and the PWM signal is shown in FIG. 7.

[0061] As described above, the feedback voltage generator 37 built in the PWM controller 101 generates the feedback voltage VFB by sampling the flyback voltage of the auxiliary winding during every PWM cycle to keep the voltage of the detection input DET constant. The bias current sink 36 pulls the bias current IM in response to load conditions. This varies the voltage drop across the detection resistor 200 to compensate for variations in the voltage drop across the output rectifying diode D2. This results in a more a precise output voltage and greatly improves load regulation.

[0062] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

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Classifications
U.S. Classification363/21.12
International ClassificationH02M3/28, H02M3/335
Cooperative ClassificationH02M3/33507, H01F2038/026, H02M2001/0006
European ClassificationH02M3/335C
Legal Events
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Apr 21, 2008FPAYFee payment
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Apr 5, 2005CCCertificate of correction
Jun 18, 2003ASAssignment
Owner name: SYSTEM GENERAL CORP., TAIWAN
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Effective date: 20030521
Owner name: SYSTEM GENERAL CORP. 3F, NO. 1, ALLEY 8, LANE 45,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YANG, TA-YUNG /AR;REEL/FRAME:014204/0920