US 20050016861 A1
Methods are provided for planarizing a work piece such as a semiconductor wafer. One such method comprises the steps of providing a semiconductor wafer having an insulating layer on a surface thereof, the insulating layer comprising a field region and a plurality of features. A barrier layer is formed overlying at least the field region and then a layer comprising copper and having a substantially planar upper surface is formed overlying the barrier layer and filling the features in the insulating layer. The layer comprising copper and the barrier layer are then planarized or polished on a single polishing pad to remove the layer comprising copper and the barrier layer from the field region.
1. A method for planarizing a semiconductor wafer having an insulating layer on a surface thereof, the insulating layer comprising a field region and a plurality of features, the method comprising the steps of:
forming a barrier layer overlying at least the field region;
electrodepositing a layer comprising copper having a substantially planar upper surface overlying the barrier layer and filling the features in the insulating layer; and
polishing the layer comprising copper and the barrier layer on a single polishing pad to remove the layer comprising copper and the barrier layer from the field region.
2. The method of
3. The method of
4. The method of
5. The method of
chemical mechanical planarizing in the presence of a first slurry having a selectivity of copper:barrier greater than 1:1 to remove a first portion of the layer comprising copper; and
chemical mechanical planarizing in the presence of a second slurry having a copper:barrier layer selectivity of substantially 1:1.
6. The method of
7. The method of
8. The method of
9. The method of
10. The method of
11. The method of
forming a first seed layer comprising copper overlying the barrier layer; and
electrodepositing over the first seed layer a second layer comprising copper having a thickness less than about 300 nm as measured over the field region.
12. The method of
13. A method for planarizing a semiconductor wafer having an insulating layer on a surface thereof, the insulating layer comprising a low-k dielectric material having a field region and a plurality of features, the method comprising the steps of:
forming a barrier layer overlying the insulating layer;
forming a seed layer comprising copper overlying and contacting the barrier layer;
electrochemical mechanical plating a layer comprising copper having a substantially planar upper surface overlying the seed layer and filling the features;
chemical mechanical polishing the layer comprising copper and the barrier layer on a single polishing platen to remove the layer comprising copper and the barrier layer from the field region.
14. The method of
15. The method of
chemical mechanical polishing in the presence of a first slurry having a selectivity of copper:barrier layer greater than 1:1 to remove a first portion of the layer comprising copper; and
chemical mechanical polishing in the presence of a second slurry having a copper:barrier layer selectivity of substantially 1:1.
16. The method of
17. A method for planarizing a work piece having a surface comprising a plurality of features and a field region, the method comprising the steps of:
forming a barrier layer overlying the field region and extending into the features;
electrodepositing a metal layer overlying the barrier layer and filling the features, the metal layer having a substantially planar upper surface over the features and the field region;
polishing the metal layer and the barrier layer on a single polishing pad to remove the metal layer and the barrier layer from the field region.
18. The method of
19. The method of
electrodepositing a metal layer at a first platen of the multi-platen apparatus;
robotically moving the work piece to a second platen of the multi-platen apparatus; and
polishing the metal layer and the barrier layer at the second platen.
20. The method of
aligning the work piece carrier with respect to a first platen of the multi-platen apparatus;
electrodepositing a metal layer at the first platen;
aligning the work piece carrier with respect to a second platen of the multi-platen apparatus; and
polishing the metal layer and the barrier layer at the second platen.
21. The method of
The present invention generally relates to a method for planarizing a work piece, and more particularly relates to a method for planarizing a work piece such as a semiconductor wafer having a metal layer such as a copper containing metal layer on a surface thereof.
The production of integrated circuits begins with the creation of high-quality semiconductor wafers. During the wafer fabrication process, the wafers may undergo multiple dielectric and conductor deposition processes followed by the masking and etching of the deposited layers. Some of these steps relate to metallization, which generally refers to the materials, methods and processes of wiring together or interconnecting the component parts of an integrated circuit located on or overlying the surface of the wafer. Typically, the “wiring ”of an integrated circuit involves etching trenches and “vias ” in a planar dielectric (insulator) layer and filling the trenches and vias with a conductive material, typically a metal.
In the past, aluminum was used extensively as a metallization material in semiconductor fabrication due to ease with which aluminum could be applied and patterned and due to the leakage and adhesion problems experienced with the use of gold. Other metallization materials have included such materials as Ni, Ta, Ti, W, Ag, Cu/Al, TaN, TiN, CoWP, NiP and CoP, alone or in various combinations.
Recently, techniques have been developed which utilize copper to form conductive contacts and interconnects because copper is less susceptible to electromigration and exhibits a lower resistivity than aluminum. Since copper does not readily form volatile or soluble compounds, the patterned etching of copper is difficult, and the copper conductive contacts and interconnects are therefore often formed using a damascene process. In accordance with the damascene process, the copper conductive contacts and interconnects are usually formed by creating a via within an insulating material, depositing a barrier layer onto the surface of the insulating material and into the via, depositing a seed layer of copper onto the barrier layer, and electrodepositing a copper layer onto the seed layer to fill the via. The excess copper and the barrier layer overlying the insulating material are then removed, for example by a process of chemical mechanical planarization or chemical mechanical polishing, each of which will hereafter be referred to as chemical mechanical planarization or CMP.
As the size of integrated circuit components continues to decrease and the density of microstructures on integrated circuits increases, the feature sizes found on the integrated circuit can vary widely from, for example, less than 100 nanometers (nm) to more than 1 micrometer (μm). Such features are generally spaced apart by otherwise substantially planar field regions. Filling the wide variety of features, especially the wide features, is difficult. To fill such wide features with a metal, it is often necessary to deposit relatively thick layers of the metal, typically 700 nm and greater, over the field regions of the wafer. A subsequent planarization process then is required to remove the thick excess deposited metal layers, to electrically isolate the metal in spaced apart features, and to level the surface for subsequent steps in the integrated circuit manufacturing process. Planarization of the thick metal layers by CMP is usually accomplished in a “soft landing CMP process ” that involves several steps with each of the steps carried out on a different platen. First, the bulk of the excess metal is removed in a rapid removal process that uses a hard polishing pad attached to a polishing platen and employs a high pressure exerted between the wafer surface and the pad. The high pressure and the hard pad effect a rapid removal rate of the metal, but if continued to the completion of the metal removal, would result in damage to the underlying insulator, especially if that insulator is a low-k dielectric material. The hard pad also is effective for achieving a planar surface free from “dishing ” of the metal in the vicinity of large features. In a second step, the final portion of the excess metal is removed using a hard polishing pad attached to a second platen but with a lower pressure exerted between the wafer surface and the polishing pad. The lower pressure is used to minimize dishing and erosion. A third step using yet another pad on another platen may then be required to remove the barrier layer overlying the field regions of the insulator. A final buff step may also be required to remove a damaged upper layer of the insulator, to remove contaminants, and to clean the resulting polished surface of the metal and the exposed insulator. Deposition of such thick layers of metal followed by a multi-step planarization process to subsequently remove the thick excess metal layer increases the costs of the planarization process and decreases throughput.
Accordingly, a need exists for an improved method for planarizing a work piece, and especially for planarizing a work piece having a deposited metal layer on a surface thereof. In addition, there is a need for a method for planarizing a semiconductor wafer having a deposited copper layer thereon. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein
The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.
The invention disclosed and claimed herein is applicable to the planarization of a surface of a variety of work pieces, but will be described and illustrated with reference to only a single illustrative work piece, namely a semiconductor wafer having a layer of copper deposited thereon. Although the invention is illustrated with reference to its application only to one particular work piece and to one particular metal deposited on that work piece, it is not intended that the invention be limited to that particular application.
In contrast to the prior art conventional method, in accordance with an embodiment of the invention, a copper layer 30 having a substantially planar upper surface 34 is deposited overlying the seed layer by an electrodeposition process such as that disclosed in the copending, commonly assigned application filed Feb. 27, 2003 and identified by attorney docket number 004.0029, the disclosure of which is herein incorporated in its entirety by reference. As used herein the term “substantially planar surface” shall mean a surface having no step height greater than about 100 nm and as used hereinafter, the term “electrodeposition” includes both the processes of electroplating and electrochemical mechanical deposition, also known as planar deposition. Electroplating typically involves conventional metal deposition using an electrolyte solution containing a metal, an anode, and a cathode. Electrochemical mechanical deposition uses a dedicated apparatus that selectively deposits the metal on the work piece by a process that combines electroplating with a mechanical aspect to obtain a planar metal surface of a desired thickness.
The following example illustrates a method, in accordance with one embodiment of the invention, for performing substantially planar deposition of a copper layer on semiconductor wafer 10. The copper layer can be deposited in a variety of different deposition apparatuses that are well known in the industry such as, for example, an electrochemical mechanical deposition apparatus 60 schematically illustrated in
Platen 64 may be connected to a driver or motor assembly (not shown) that is operative to rotate platen 64 and contact surface 62 about a vertical axis. It will be appreciated by those of skill in the art, however, that the driver or motor assembly may be operative to move platen 64 and contact surface 62 in an orbital, linear or oscillatory pattern or any combination thereof. Similarly, wafer carrier 68 may be connected to a driver or motor assembly (not shown) that is operative to rotate wafer carrier 68 and the semiconductor wafer about a vertical axis 76 or to move wafer carrier 68 and the semiconductor wafer in an orbital, linear or oscillator pattern or any combination thereof.
Platen 64 may have one or more channels 74 for the transportation of a plating composition to contact surface 62 from a manifold apparatus (not shown) or any suitable distribution system. Alternatively, it will be appreciated that the plating composition may be deposited directly on or through contact surface 62 by a conduit or any suitable application mechanism. As a further alternative, the platen and contact surface may be immersed in the plating solution which is contained within a receptacle or container that partially surrounds the platen.
The method for performing substantially planar deposition of a metal on a semiconductor wafer, in accordance with one exemplary embodiment of the invention, comprises selecting a deposition temperature, that is, the predominant or average temperature at which the deposition process will be conducted. An electrodeposition composition is formulated comprising a metal salt, a suppressor, an accelerator, and an electrolyte with the suppressor chosen so that it has a cloud point that is no greater than the selected deposition temperature. In accordance with a particular embodiment of the invention, the suppressor is selected so that the cloud point matches the deposition temperature. If the cloud point is greater than the deposition temperature, an anion may be added to the composition to lower the cloud point to a temperature no greater than the electrodeposition temperature. For example, for a deposition temperature of 21° C., the composition may comprise 67 g/L CuSO4.5H2O, 180 g/L H2SO4, 10 ml/L of 2% Pluronic® 31R1 (available from BASF Corporation of Mount Olive, N.J.), 7 ml/L of 0.1%/ of the sodium salt of 3-mercaptopropane sulfonic acid and 50 ppm bromide. The components of the composition may be combined in any suitable order by any convenient method of mixing, such as, for example, by rapidly stirring with a mechanical stirrer or by agitating with a mechanical agitator.
Next, metal is electrodeposited onto the semiconductor wafer from the electrochemical deposition composition. The electrodeposition occurs at the selected deposition temperature. Wafer carrier 68 urges the semiconductor wafer against contact surface 62 such that the semiconductor wafer engages contact surface 62 at a desired pressure. Preferably, wafer carrier 68 applies a uniform and constant pressure of approximately 1 pound per square inch (psi) or less, although it may be appreciated that any suitable pressure that promotes substantially planar deposition may be used. During the deposition process, the electrodeposition composition is delivered to the surface of contact surface 62 through channels 74. An electric potential is also applied to create a circuit between platen 64, the electrodeposition composition and the semiconductor wafer. The power source 70 may apply a constant current or voltage to the apparatus or, alternatively, the current or voltage could be modulated to apply different currents or voltages at predetermined times in the process or to modulate between a predetermined current or voltage and no current or no voltage. Wafer carrier 68 and the semiconductor wafer may rotate about axis 76 while platen 64 and contact surface 62 move in a rotational, orbital or linear pattern. In addition, wafer carrier 68 and the semiconductor wafer may oscillate relative to contact surface 62. The electrodeposition process continues for a predetermined amount of time or until an endpoint detection apparatus indicates that a desired deposition thickness has been achieved.
Following the deposition of copper layer 30 having a thin overburden and a substantially planar upper surface 34, the excess copper and barrier layer overlying the field regions of layer 14 of dielectric material are removed by a chemical mechanical planarization (CMP) process to achieve the desired structure illustrated in
In accordance with one embodiment of the invention, the planarization of copper layer 30 can be accomplished in a CMP apparatus such as a Momentum CMP apparatus available from Novellus Systems Inc., CMP Division, of Chandler, Ariz. A representative CMP apparatus 80 in which the planarization can be carried out is schematically illustrated in cross section, in
As a specific exemplary illustration, consider a semiconductor wafer prepared in the manner described above and having a barrier layer of TaN having a thickness of about 25 mn, a seed layer of copper having a thickness of about 80 nm, and a copper overburden on the field regions of the dielectric material having a thickness of less than about 300 nm and preferably less than about 200 nm. Such a semiconductor wafer can be planarized on a Momentum CMP apparatus using a soft polishing pad such as a Politex© polishing pad, a polishing pressure of about 0.5-2.5 pounds per square inch (psi) and preferably a pressure of about 1 psi, a wafer rotation of about 600 revolutions per minute and an orbital platen motion with an orbit radius of about 1.25 inches. The planarization process proceeds for about 100 seconds and then the wafer is transferred to a buff station or directly to a cleaning station. The complete planarization process is carried out on the single polishing pad, preferably a soft polishing pad affixed to a single platen to remove the excess copper overburden and the barrier layer overlying the field regions of the insulating layer. In accordance with one embodiment of the invention the slurry preferably is selected to have substantially the same selectivity to copper as it does to the barrier layer. That is, the removal rate of the copper and the removal rate of the barrier layer are substantially in the ratio of 1:1. For example, a slurry such as Hitachi T-805-H can be employed with the concentration of hydrogen peroxide oxidizing agent adjusted to about 0.5% . The planarization process can also be continued on the same soft polishing pad to planarize the field regions of the dielectric material. The use of a soft polishing pad and low pressures between the wafer surface and the polishing pad are especially advantageous in avoiding scratching or otherwise causing damage to the dielectric layer if the layer of dielectric material includes a low-k dielectric.
In accordance with a further embodiment of the invention, the planarization of copper layer 30 is carried out as above except that the slurry composition is adjusted during the process to first provide an enhanced copper removal rate and then a reduced and controlled copper removal rate. For example, Hitachi T-805-H slurry can be employed with the hydrogen peroxide oxidizing agent adjusted to about 3% at the point of use to enhance the copper removal rate during the bulk copper removal step and then reduced to about 0.5% to achieve a selectivity of about 1:1 with the barrier material. During the bulk copper removal rate step the selectivity of the removal of copper with respect to the removal of the barrier layer can be greater than 1:1. The change in concentration of the oxidizing agent can be made based on time of polishing or based on end point detection in known manner. When the slurry composition is to be changed, the pad and associated apparatus can be flushed with water to purge the system of the first slurry composition.
The resulting wafer is found to have a substantially planar upper surface. The remaining copper regions are planar and free from dishing. The field regions of the dielectric layer are substantially planar and substantially free from defects and scratches.
Although the exemplary CMP apparatus described above is of the type generally referred to as a front referenced apparatus, the method of the invention is also applicable to other types of CMP apparatus such as, for example, back referenced apparatus. In such an apparatus the planar removal of the copper layer and the underlying barrier layer are carried out on a single platen using a soft polishing pad and preferably a slurry having a copper:barrier selectivity of about 1:1. In accordance with yet another embodiment of the invention, the processes of planarized deposition and subsequent CMP can also be performed in a single continuous operation. That is, the apparatus for planarized deposition of a metal such as copper can also be used for the planarization of the resulting copper layer by switching from an electrochemical deposition composition applied to the polishing pad or contact surface to a polishing slurry applied to the polishing pad. The pressure of the semiconductor wafer against the polishing pad during the two operations can be adjusted to the appropriate pressure as described above.
In accordance with a further embodiment of the invention, following the planarization of the deposited copper layer by any of the above described processes, the surface of the planarized semiconductor wafer, including both the planarized copper regions filling the features in the dielectric material and the field regions of the dielectric material can be cleaned and buffed at a buffing station to complete the planarization of the field regions and to remove contaminants, CMP residue, residual damage, and the like from the surface of the wafer.
In accordance with an embodiment of the invention, the deposition apparatus as illustrated in
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope of the invention as set forth in the appended claims and the legal equivalents thereof.