|Publication number||US20050018494 A1|
|Application number||US 10/625,298|
|Publication date||Jan 27, 2005|
|Filing date||Jul 22, 2003|
|Priority date||Jul 22, 2003|
|Also published as||US6853594|
|Publication number||10625298, 625298, US 2005/0018494 A1, US 2005/018494 A1, US 20050018494 A1, US 20050018494A1, US 2005018494 A1, US 2005018494A1, US-A1-20050018494, US-A1-2005018494, US2005/0018494A1, US2005/018494A1, US20050018494 A1, US20050018494A1, US2005018494 A1, US2005018494A1|
|Inventors||Chung-Hsiao Wu, Jyh-Ming Jong|
|Original Assignee||Wu Chung-Hsiao R., Jyh-Ming Jong|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Referenced by (9), Classifications (10), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention generally relates to semiconductor devices. More specifically, the present invention relates to data strobe receivers.
There has increasingly been a demand for faster, higher capacity random access memory (RAM) devices. At one time, dynamic random access memory (DRAM) was typically used as the main memory in computer systems. Although the operating speed of DRAM improved over the years, this speed did not reach the operating speed of the processors used to access the DRAM. In a computer system, for example, the slow access and cycle times of the DRAM led to system bottlenecks. These bottlenecks slowed down the throughput of the system despite the very fast operating speed of the computer system's processor.
As a result, a new type of memory known as synchronous dynamic random access memory (SDRAM) was developed to provide faster operation in a synchronous manner. SDRAMs are designed to operate synchronously with the computer system's clock. That is, the input and output data of the SDRAM are synchronized to an active edge of the computer system's clock.
Although SDRAMs have overcome some of the timing disadvantages of other memory devices, such as DRAMs, there is still a need for faster memory devices. Double data rate (DDR) SDRAMs provide twice the operating speed of conventional SDRAMs. These devices allow data transfers on both the rising and falling edges of the computer system's clock and thus provide twice as much data as the conventional SDRAM. DDR SDRAMs are also capable of providing burst data at a high-speed data rate.
Due to the high-speed data transfers, DDR SDRAMs use a bi-directional data strobe (DQS) to register the data being input or output on both edges of the computer system's clock. Industry standards define several states of DQS before, during, and after a burst transfer of data. Before a burst transfer of data, DQS is in a high-impedance state that is known as Hi-Z. When DQS is in Hi-Z, DQS is at a voltage level between logic high and logic low.
One clock cycle before a burst data transfer, DQS transitions from Hi-Z to logic low. This logic low state is known as “data strobe preamble.” After the data strobe preamble, DQS transitions (both low-to-high transitions and high-to-low transitions) are utilized to synchronize the transferred data. One half clock before the data transfer is completed, DQS remains in a logic low state. This state is known as “postamble.” After the completion of the postamble, DQS enters the Hi-Z state.
Thus, a need exists for a simple DQS receiver that can accurately determine DQS transitions and can avoid false determinations due to electrical noise.
One embodiment of the invention is a data strobe receiver that includes a first comparator. The first comparator has a first input that is coupled to a first reference voltage. The first comparator has a second input that is coupled to a data strobe. The first comparator also has an output. The data strobe receiver also includes a delay element. The delay element has an input that is coupled to the output of the first comparator. The delay element also has an enable input and an output. The data strobe receiver also includes a second comparator. The second comparator has a first input that is coupled to a second voltage reference. The second comparator has a second input that is coupled to the data strobe. The second comparator also has an output. The data strobe receiver also includes a divide-by-X-counter, where X is an integer greater than 1 and less than 129 (such as 2, 4, 8, 16, 32, 64, or 128). The divide-by-X-counter has an input that is coupled to the output of the second comparator.
The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
5.1 Data Strobe Receiver
As shown in
As shown in
Referring again to
The DQS receiver 100 also includes a divide-by-4-counter 140. The divide-by-4-counter 140 contains a clock input, an inverted reset input and an inverted output. The clock input to the divide-by-4-counter 140 is coupled to DQS-Detect. As shown in
The DQS receiver 100 also includes a set-reset-flip-flop 150. The set-reset-flip-flop 150 contains an inverted set input, an inverted reset input, and an output. Set-reset-flip-flops are known to those of skill in the art and can be constructed by many different combinations of logic gates. One embodiment of the invention utilizes the combination of logic gates such as shown in
The DQS receiver 100 also includes a first AND gate 160. The first AND gate 160 contains two inputs and one output. The first input of the first AND gate 160 is coupled to the output of the set-reset-flip-flop 150 (and the inverted input of the divide-by-4-counter 140). The second input of the AND gate 160 is coupled to an inverted Output_Enable signal. The inverted Output_Enable signal is high when the memory controller is reading memory and is low when the memory controller is writing to memory. The output of the first AND gate 160 is coupled to the enable input of the delay element 120.
The DQS receiver 100 also includes a first OR gate 170. The first OR gate 170 contains two inputs and one output. The first input of the first OR gate 170 is coupled to the inverted output of the divide-by-4-counter 140. The second input of the first OR gate 170 is coupled to DQS_90.
The DQS receiver 100 also includes a second OR gate 180. The second OR gate 180 contains two inputs and an output. The first input of the second OR gate 180 is coupled to a Continuous_Read signal. As shown in
The DQS receiver 100 also contains a second AND gate 190. The second AND gate 190 contains three inputs and an output. The first input of the second AND gate 190 is coupled to a Reset_Low signal. The Reset_Low signal, which is active when low, resets the DQS receiver 100. The second input of the second AND gate 190 is coupled to the output of the second OR gate 180. The third input of the second AND gate 190 is coupled to the inverted Output_Enable signal. The output of the second AND gate 190 is coupled to the inverted reset input of the set-reset-flip-flop 150.
The DQS receiver 100 is coupled to a first-in-first-out buffer (FIFO) 192. The FIFO 192 contains a data input, which will be referred to as DQ, an insert input, and a Reset_Low input. The data input is coupled to the output of a third comparator 195, which has two inputs. One input of the third comparator 195 is coupled to a third voltage reference and the second input of the third comparator 195 is coupled to a DQ input. As is shown in
5.2 A Method of Operating a Data Strobe Receiver
One method of operating the DQS receiver 100 is shown in
At time 610, the DQS signal falls below (V-X) ref. Thus, the output of the second comparator 130, DQS_Detect, begins to enter a low logic state. Thus, the output of the set-reset-flip-flop 150 enters a logic high state at time 615, the divide-by-4-counter 140 is released from its reset mode, and the delay element 120 is enabled. As a result, the divide-by-4-counter 140 begins counted transitions of DQS_Detect, and the Delay Element 120 begins outputting DQS 90.
At time 620, the divide-by-4-counter 140 has counted four state transitions of DQS_Detect. Thus, the inverted output of the divide-by-4-counter 140 begins to enter a logic low state. As a result, at time 625, the output of the first OR gate 170 begins to transition to a low logic state. Even though the output of the first OR gate 170 is low at this time, the Continuous_Read signal is high. Thus, the output of the second OR gate 180, remains high.
At time 630, the divide-by-4-counter 140 has detected anther transition of DQS_Detect. Thus, its inverted output begins to transition to a high logic state. This transition causes the output of the first OR gate to begin to transition to a high logic state at time 635.
At time 640, the divide-by-4-counter 140 has counted another four state transitions of DQS_Detect. Thus, the inverted output of the divide-by-4-counter 140 begins to enter a logic low state. However, the output of the first OR gate 170 remains high until DQS_90 transitions to a low logic state at time 645. At that time, the output of the first OR gate 170 begins to transition to a low logic state. Because at time 650, the Continuous_Read signal is low, the output of the second OR gate 180 begins to transition to a low logic state. When the output of the second OR gate 180 reaches its low logic state at time 655, the output of the second AND gate begins to transition to a low logic state. When the output of the second AND gate reaches its low logic state at time 660, the set-reset-flip-flop 150 is reset, thereby causing the output of the set-reset-flip-flop 150 to begin to transition to a low logic state.
When the set-reset-flip-flop 150 enters its low logic state at time 665, the delay element 120 is disabled and the divide-by-4-counter is reset. Thus, DQS_90 is held at a low logic state regardless of the logic state of DQS.
The foregoing descriptions of embodiments of the present invention have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention. The scope of the present invention is defined by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5881007 *||Nov 7, 1997||Mar 9, 1999||Hyundai Electronics Industries Co., Ltd.||Sense amplifier enable signal generator for semiconductor memory device|
|US6233180 *||Feb 4, 1999||May 15, 2001||Saifun Semiconductors Ltd.||Device for determining the validity of word line conditions and for delaying data sensing operation|
|US6512704 *||Sep 14, 2001||Jan 28, 2003||Sun Microsystems, Inc.||Data strobe receiver|
|US20030210575 *||Oct 23, 2002||Nov 13, 2003||Seo Seong-Young||Multimode data buffer and method for controlling propagation delay time|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7508723 *||May 24, 2007||Mar 24, 2009||Entorian Technologies, Lp||Buffered memory device|
|US7596053 *||Oct 4, 2006||Sep 29, 2009||Marvell International Ltd.||Integrated memory controller|
|US7876630 *||Nov 6, 2007||Jan 25, 2011||Altera Corporation||Postamble timing for DDR memories|
|US7990783 *||Jan 11, 2011||Aug 2, 2011||Altera Corporation||Postamble timing for DDR memories|
|US8352696||Apr 15, 2008||Jan 8, 2013||Rambus Inc.||Integrated circuit with bi-modal data strobe|
|US8407510 *||Oct 11, 2006||Mar 26, 2013||Marvell Israel (Misl) Ltd.||DDR interface bus control|
|US8630131 *||Jul 30, 2012||Jan 14, 2014||Altera Corporation||Data strobe enable circuitry|
|US9001595 *||Jan 6, 2014||Apr 7, 2015||Altera Corporation||Data strobe enable circuitry|
|US20050071707 *||Sep 30, 2003||Mar 31, 2005||Hampel Craig E.||Integrated circuit with bi-modal data strobe|
|Cooperative Classification||G11C7/1078, G11C7/109, G11C7/1087, G11C7/1093|
|European Classification||G11C7/10W3, G11C7/10W5, G11C7/10W7, G11C7/10W|
|Jul 22, 2003||AS||Assignment|
|Jul 22, 2008||FPAY||Fee payment|
Year of fee payment: 4
|Jul 11, 2012||FPAY||Fee payment|
Year of fee payment: 8