US20050023644A1 - Stabilization in device characteristics of a bipolar transistor that is included in a semiconductor device with a CMOSFET - Google Patents
Stabilization in device characteristics of a bipolar transistor that is included in a semiconductor device with a CMOSFET Download PDFInfo
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- US20050023644A1 US20050023644A1 US10/929,621 US92962104A US2005023644A1 US 20050023644 A1 US20050023644 A1 US 20050023644A1 US 92962104 A US92962104 A US 92962104A US 2005023644 A1 US2005023644 A1 US 2005023644A1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Definitions
- the present invention relates to a semiconductor device including a CMOSFET and a bipolar transistor and to a method for manufacturing the semiconductor device.
- the bipolar transistor is formed by taking advantage of steps for forming a well region, source regions, and drain regions of the CMOSFET.
- Bi-CMOS IC With a manufacturing process for a semiconductor device called a Bi-CMOS IC, in which bipolar transistors and CMOSFETs are formed on the same substrate, there is a technology for forming, for example, base regions of the bipolar transistors using diffusion regions for forming wells for the CMOSFETs and for forming emitter regions using diffusion regions for forming the source and drain regions in order to reduce the number of process steps.
- a semiconductor device 1 shown in FIG. 24 a silicon-on-insulator (SOI) substrate is included., and a CMOSFET 4 and a bipolar transistor 5 are located over an insulating film 3 on a silicon substrate 2 .
- SOI silicon-on-insulator
- An SOI layer included in the SOI substrate includes a high impurity concentration n-type silicon layer 6 and a low impurity concentration n-type silicon layer 7 on the insulating film 3 , and the transistors 4 , 5 of the device 1 are isolated by trenches 8 and by LOCOS 9 in a surface of the device 1 .
- the CMOSFET 4 includes p channel-type and n channel-type MOSFETs 4 a , 4 b , in which an n-type well 10 and a p-type well 11 are included, respectively.
- Source and drain regions 12 , 13 are included in the n-type well 10 and the p-type well 11 , respectively.
- Each gate electrode 15 is located on a gate oxide film 14 .
- Contact holes are located in an insulating film 16 .
- Aluminum electrodes 17 are in electric-contact with the source and drain-regions 12 , 13 .
- An npn transistor 5 includes a low impurity concentration n-type silicon layer 7 as a collector region, in a surface of which a p-type base region 18 is located.
- An n-type emitter region 19 and a base contact region 20 are located in a surface of the p-type base region 18 .
- a collector contact region 21 is also located in the surface of the silicon layer 7 .
- the semiconductor device 1 is formed by the following process flow, which is shown in FIGS. 25A to 25 G.
- an SOI substrate 210 in which n-type single crystal silicon layers 6 , 7 are located on an insulating layer 3 , is prepared.
- trenches 8 are formed outside the areas where for transistors 4 , 5 are formed, as shown in FIG. 25B .
- wells 10 , 11 are formed using a known CMOSFET process.
- base region 18 is formed, as shown in FIG. 25C .
- LOCOS 9 are formed, and a gate oxide film 14 and gate electrodes 15 are formed, as shown in FIG. 25F .
- the source and drain regions 12 , 13 of MOSFETs 4 a , 4 b are formed, as shown FIG. 25F .
- an emitter region 19 , a base contact region 20 , and a collector contact region 21 are formed.
- an insulating film 16 and the aluminum electrodes 17 are formed to complete a Bi-CMOSFET semiconductor device 1 .
- the Bi-CMOSFET semiconductor device 1 has the following drawback with the characteristics of the npn transistor 5 .
- the base region 18 of the transistor 5 is simultaneously formed at the step for forming the p-type well 11 , so the surface impurity concentration of the base region 18 is generally relatively low. Therefore, the characteristics of the transistor 5 can shift due to a slight shift in the amount of charges at the interface between the p-type base region 18 and the insulating film 16 , which is made of SiO 2 , under a certain biasing condition for driving the transistor 5 .
- the interface is shown with small x-marks in FIG. 24 . As a result, the characteristics of the transistor 5 become unstable, and operating errors are caused in some circuit designs.
- a first object of the present invention is to provide a semiconductor device that is relatively stable in the device characteristics, which are affected by the impurity concentration at a surface of a base region, even when a bipolar transistor and a CMOSFET is simultaneously formed in a device using a CMOSFET process.
- a second object is to provide a method of manufacturing the semiconductor device.
- a CMOSFET and a bipolar transistor are formed into a single unit on a substrate.
- the steps for forming a well region, source regions, and drain regions of the CMOSFETs are also used for forming the bipolar transistors, and one of the steps is used for introducing impurities of the same conductivity type in a surface of a base region of the bipolar transistor in order to form a high impurity concentration area in the surface.
- the surface of the base region is exposed by ultraviolet rays in order to reduce the amount of charges at the interface between the base region and an insulating film located on the surface of the base region.
- a hydrogen barrier film is formed such that the hydrogen barrier film covers the surface of the base region.
- FIG. 1 is a partial cross-sectional view of a semiconductor device according to a first embodiment of the present invention
- FIG. 2 is a graph showing the simulation results obtained for the Gummel characteristics of an npn transistor having a surface impurity concentration of 2 ⁇ 10 16 cm ⁇ 3 in a base region of the transistor in both cases with and without positive fixed charges at an interface between a base region and an insulating film located on the base region;
- FIG. 3 is a graph showing the simulation results for the direct current amplification (h FE ) characteristics of an npn transistor with respect to impurity concentration at the surface of a base region of the transistor in both cases with and without the positive fixed charges;
- FIG. 4 is a graph showing the simulation results for the direct current amplification (h FE ) characteristics of an npn transistor with respect to the distance d between a high impurity concentration region and an emitter region of the transistor in both cases with and without charges;
- FIG. 5 is a graph showing the actually measured results for the direct current amplification (h FE ) characteristics of an npn transistor that has the same structure as used for the simulation of FIG. 4 ;
- FIG. 6 is a graph showing the correlation between the reverse bias breakdown voltage and distance between a high impurity concentration region and an emitter region of an npn transistor
- FIG. 7 is a graph showing the correlation between the changes in output voltage and time with various distances between a high impurity concentration region and an emitter region of an npn transistor;
- FIG. 8A is a partial cross-sectional view of a first variation of a semiconductor device according to a second embodiment
- FIG. 8B is a plan view of a bipolar transistor in the first variation
- FIG. 8C is a partial cross-sectional view of a second variation of the semiconductor device according to the second embodiment
- FIG. 8D is a plan view of a bipolar transistor in the second variation
- FIGS. 9A to 9 P are cross-sectional views showing the structure of a semiconductor device according to a third embodiment in the manufacturing process of the device.
- FIG. 10 is a cross-sectional view of a bipolar transistor of a semiconductor device according to a fourth embodiment
- FIG. 11 is a partial cross-sectional view of a semiconductor device according to a fifth embodiment.
- FIG. 12 is a partial cross-sectional view of a semiconductor device according to a sixth embodiment.
- FIG. 13 is a graph showing the correlation between the direct current amplification factor and the collector current without any ultraviolet radiation
- FIG. 14 is a graph showing the correlation between the direct current amplification factor and the collector current with ultraviolet radiation
- FIG. 15 is a partial cross-sectional view of a semiconductor device according to a seventh embodiment.
- FIG. 16A is a partial cross-sectional view of a semiconductor device according to an eighth embodiment and FIG. 16B is a plan view of a bipolar transistor in the device according to the seventh embodiment;
- FIG. 17 is a cross-sectional view of a bipolar transistor in a semiconductor device according to a ninth embodiment.
- FIG. 18A is a cross-sectional view of a bipolar transistor in a semiconductor device according to a tenth embodiment and FIG. 18B is a plan view of the bipolar transistor according to the tenth embodiment;
- FIG. 19A is a cross-sectional view of a bipolar transistor in a semiconductor device according to an eleventh embodiment and FIG. 19B is a plan view of the bipolar transistor according to the eleventh embodiment;
- FIG. 20 is a cross-sectional view of a bipolar transistor in a semiconductor device according to a twelfth embodiment
- FIG. 21 is a circuit diagram according to a thirteenth embodiment
- FIG. 22 is another circuit diagram according to the thirteenth embodiment.
- FIG. 23 is another circuit diagram according to the thirteenth embodiment.
- FIG. 24 is a cross-sectional view of a proposed semiconductor device.
- FIGS. 25A to 25 G are cross-sectional views showing the structure of the device in FIG. 24 in the manufacturing process of the device.
- a Bi-CMOS semiconductor device 31 includes a CMOSFET 34 and a bipolar transistor 35 .
- the CMOSFET 34 and the transistor 35 are located on an insulating film 33 , which is located on a silicon substrate 32 .
- the Bi-CMOS semiconductor device 31 is formed from an SOI substrate, which has an SOI layer including a high impurity concentration n-type silicon layer 36 and a low impurity concentration n-type silicon layer 37 , impurity concentration of which is, for example, approximately 1 ⁇ 10 15 cm ⁇ 3 .
- the CMOSFET 34 and the transistor 35 include the silicon layers 36 and 37 .
- the CMOSFET 34 and the bipolar transistor 35 are surrounded and isolated by the trenches 38 , respectively. Furthermore, the CMOSFET 34 and the bipolar transistor 35 are isolated by local-oxidation-of-silicon (LOCOS) areas 39 at the surface of the device 31 .
- LOC local-oxidation-of-silicon
- the CMOSFET 34 includes an n channel MOSFET 34 a and a p channel MOSFET 34 b .
- a p-type well 40 which has an impurity concentration of, for example, approximately 4 ⁇ 10 16 cm ⁇ 3 , and an n-type well 41 are located in the low impurity concentration n-type layer 37 .
- N-type source and drain regions 42 are located in the p-type well 40 .
- P-type source and drain regions 43 are located in the n-type well 41 .
- Gate electrodes 45 are made of polycrystalline silicon. Each gate electrode 45 is located on a gate insulating film 44 , which is located above each channel between the source region and the drain region 42 , 43 . The surface of the CMOSFET 34 is covered by an insulating film 46 , and aluminum electrodes 47 are in electric contact with the source and drain regions 42 , 43 through contact holes in the insulating film 46 .
- a p-type base region 48 which has an impurity concentration of, for example, approximately 4 ⁇ 10 16 cm ⁇ 3 , is located in a surface of the low impurity concentration n-type layer 37 .
- a high impurity concentration n-type emitter region 49 which has an impurity concentration of, for example, approximately 1 ⁇ 10 20 cm ⁇ 3 , is located in a surface of the p-type base region 48 .
- a high impurity concentration p-type base region 50 which has an impurity concentration of, for example, approximately 1 ⁇ 10 20 cm ⁇ 3 , is located in the surface of the p-type base region 48 .
- the high impurity concentration p-type base region 50 is extends from an end of the LOCOS 39 to a position having a distance d from an end of the emitter region 49 .
- a high impurity concentration n-type collector contact region 51 is located in a surface of the low impurity concentration n-type layer 37 .
- the surface of the bipolar transistor 35 is also covered by an insulating film 46 , and aluminum electrodes 47 are in electric contact with the emitter region 49 , the base region 50 , and the collector contact region 51 through contact holes in the insulating film 46 .
- the base region 48 of the bipolar transistor 35 is simultaneously formed when the p-type well 41 of the CMOSFET 34 is formed. Furthermore, the emitter region 49 and the collector contact region 51 are simultaneously formed when the n-type source and drain regions 42 are formed.
- the high impurity concentration p-type base region 50 is simultaneously formed when the p-type source and drain regions 43 are formed.
- the impurity concentration of the p-type well 40 is lower than the concentration required for the base of a bipolar transistor.
- the impurity concentration is, for example, approximately 4 ⁇ 10 16 cm ⁇ 3 . Therefore, it is essentially undesired that the base region 48 is formed at the step of forming the p-type well 40 in terms of device characteristics.
- the surface area of the base region 48 is mostly covered by the emitter region 49 and the high impurity concentration p-type base region 50 , and the base region 48 is in contact with the insulating film 46 at the space of as short as 1 to 2 ⁇ m between the emitter region 49 and the base region 50 . Therefore, the instability in operating characteristics of the bipolar transistor 35 , which is caused by a relatively low impurity concentration at the surface of the base region 48 , is improved, and the operating characteristics becomes relatively stable. The reason is as follows.
- the impurity concentration at the surface of the base region 18 can be as low as 1 ⁇ 10 18 cm ⁇ 3 or less for the sake of the design of the CMOSFET 4 when simultaneously forming the base region 18 of the bipolar transistor 5 and the p-type well region 11 of the CMOSFET 4 .
- the operating characteristics stray from desired values, because an n-type inversion layer can be formed at the surface of the base region 18 when the bipolar transistor 5 is driven under certain biasing conditions, or when an amount of the positive fixed charges increases at the Si—SiO 2 interface, which is located between the base contact region 20 and the emitter region 19 , in the manufacturing process of the device 1 .
- the inventor of the present invention conducted the following simulations to study the above problem.
- the base current Ib increases when the number of recombination sites increases due to a higher density of defects such as a crystal defect and a dangling bond in the emitter-base depletion layer and the corresponding recombination current increases.
- the collector current Ic changes with a change in the transistor structure such as impurity concentrations, depths, and sizes of the base region and the emitter region.
- the simulation results show that the base current Ib substantially does not change under the effect of the positive fixed charges while the collector current Ic increases.
- the Gummel characteristics in FIG. 2 show that the transistor structure changes under the effect of the positive fixed charges when the impurity concentration is too low at the surface of the base region.
- the above problems encountered with the proposed device of FIG. 24 can be addressed by raising the impurity concentration at the surface of the base region.
- the first embodiment is based on the above simulation results, so the bipolar transistor 35 includes the high impurity concentration p-type base region 50 for raising the impurity concentration at the surface of the base region 48 .
- the distance d between the emitter region 49 and the high impurity concentration p-type base region 50 is 1 to 2 ⁇ m. Therefore, the impurity concentration is relatively high across the substantially entire surface of the base region 48 .
- the position for forming the high impurity concentration p-type base region 50 will be described in detail.
- h FE is relatively stable, with or without the charges, when the distance d is 1 to 2 ⁇ m.
- the h FE values go down rapidly when the distance d is shorter than 1 ⁇ m. Furthermore, as shown in FIG.
- the reverse bias breakdown voltage Vz (V) between the emitter region and the base region changes with the distance d, and the breakdown voltage goes down rapidly when the distance d is shorter than 1 ⁇ m. Therefore, the lower limit for the distance d should be 1 ⁇ m.
- the lower limit for the distance d should be 1 ⁇ m.
- substantially no changes in the output voltage are observed and the output voltage becomes stable when the distance d is shorter than 2 ⁇ m. From the results shown in FIGS. 4 to 7 , it is concluded that an optimal range for the distance d should be 1 to 2 ⁇ m.
- the distance d between the high impurity concentration p-type base region 50 and the emitter region 49 is set at 1 to 2 ⁇ m, so the shifts in the device characteristics are improved while sustaining the direct current amplification h FE and the breakdown voltage Vz.
- Bi-CMOS semiconductor devices 52 of FIGS. 8A to 8 D are different in structure of the high impurity concentration p-type base region from the Bi-CMOS semiconductor device 31 of FIG. 1 .
- a high impurity concentration p-type base region 54 is formed to surround an emitter region 49 in a bipolar transistor 53 of the Bi-CMOS device 52 , as shown in FIG. 8B , in which aluminum electrodes 47 are not illustrated.
- a bipolar transistor 53 includes a high impurity concentration p-type base contact region 54 a , on which an aluminum electrode 47 is formed, and a high impurity concentration p-type base region 54 b that surrounds an emitter region 49 , as shown in FIG. 8D , in which aluminum electrodes 47 are not illustrated.
- the size of the surface, at which the base region 48 is in contact with the insulating film 46 is smaller than in the Bi-CMOS semiconductor device 31 of FIG. 1 , so the changes in device characteristics, which is caused by an inversion at the surface, is further reduced and stabilized in the Bi-CMOS semiconductor devices 52 of FIGS. 8A to 8 D.
- a Bi-CMOS semiconductor device 55 differs from the Bi-CMOS semiconductor devices 52 of FIGS. 8A to 8 D in that a self alignment mask pattern 56 is included in order to precisely control the distance d between a high impurity concentration p-type base region 54 and an emitter region 49 .
- An additional process step is not required for forming the self alignment mask pattern 56 .
- the self alignment mask pattern 56 which is made of a polycrystalline silicon film, is located over the surface of a base region 48 between the high impurity concentration p-type base region 54 and the emitter region 49 in addition to the structures of the Bi-CMOS semiconductor devices 52 of FIGS. 8A to 8 D.
- a passivation film 57 for protecting the device surface including aluminum electrodes 47 is illustrated.
- an SOI substrate 58 shown in FIG. 9A is prepared.
- a silicon substrate 32 is several hundred microns in thickness.
- a high impurity concentration n-type silicon layer 36 and a low impurity concentration n-type silicon layer 37 are located on an insulating film 33 made of a silicon oxide film, which is located on the substrate 32 .
- trenches 38 for device isolation are formed in the SOI substrate 58 , as shown in FIG. 9B .
- the trenches 38 are formed by forming grooves, depositing an insulating film on the sidewalls defining the grooves, and filling the grooves with polycrystalline silicon for planarization.
- an ion implanted area 59 corresponding to an n-type well region 41 , is formed by ion implanting an n-type impuritiy, as shown in FIG. 9C .
- an ion implanted area 60 corresponding to a p-type well region 40 , is formed by ion implanting a p-type impurity, as shown in FIG. 9D .
- an ion implanted area 61 is also formed.
- the p-type well region 40 , the n-type well region 41 , and the p-type base region 48 are formed from the ion implanted areas 59 through 61 by driving in the impurities at a diffusion step, as shown in FIG. 9E .
- LOCOS 39 are formed at predetermined locations on the substrate surface for device isolation at the surface, as shown in FIG. 9F .
- a gate oxide film 44 is formed on the surface of the substrate of FIG. 9F , and gate electrodes 45 are formed from a polycrystalline silicon film, as shown in FIG. 9G .
- a self alignment mask pattern 56 is also formed from the polycrystalline silicon film on the surface of the bipolar transistor 53 .
- the mask pattern 56 has a width corresponding to the distance d between an emitter region 49 and a high impurity concentration p-type base region 50 of the bipolar transistor 53 .
- a photo resist 62 is patterned to form p-type source and drain regions 43 in the n-type well region 41 and a high impurity concentration p-type base region 54 in the p-type base region 48 , as shown in FIG. 9H .
- the photo resist 62 is formed to be slightly offset from the edges of the mask pattern 56 . As a result, the positions of the edges of the high impurity concentration p-type base region 54 can be aligned with a higher precision than an alignment precision achieved by the photo resist 62 .
- p-type impurities are introduced by ion implanting into the openings in the photo resist 62 to form the p-type source and drain regions 43 and the high impurity concentration p-type base region 54 , as shown in FIG. 9I .
- the photo resist 62 is stripped off, as shown in FIG. 9J , and a photo resist 63 is patterned for forming n-type source and drain regions 42 , the high impurity concentration n-type emitter region 49 , and a collector contact region 51 , as shown in FIG. 9K .
- the edges of the photo resist 63 are slightly offset from the edges of the mask pattern 56 .
- n-type impurities are introduced by ion implanting to form the n-type source and drain regions 42 , the high impurity concentration n-type emitter region 49 , and the collector contact region 51 , as shown in FIG. 9L .
- the photo resist 63 is stripped off, as shown in FIG. 9M , and an insulating film 46 is formed with a BPSG film, as shown in FIG. 9N .
- Contact holes are opened by photolithography and etching, and aluminum electrodes 47 are formed, as shown in FIG. 90 .
- a passivation film 57 is formed, and openings are made at the electrode pads to complete the wafer process, as shown in FIG. 9P .
- the distance d between the emitter region 49 and the high impurity concentration p-type base region 54 can be controlled precisely by using the self alignment mask pattern 56 to achieve a high degree of process control. Furthermore, the production cost is lowered by simultaneously forming the gate electrodes 45 of the CMOSFET 34 and the self alignment mask pattern 56 from the same polycrystalline silicon film because no additional process steps are required.
- a bipolar transistor 65 in a Bi-CMOS device 64 has an emitter support area 66 as a self alignment mask pattern.
- the Bi-CMOS device 64 includes a CMOS 34 having the same structure as the CMOS 34 in FIG. 1 .
- an emitter region 49 is formed before p-type source and drain regions 43 of the CMOS 34 are formed, and the emitter support area 66 , which is electrically connected to the emitter region 49 , is formed after a gate insulating film 44 is formed.
- the emitter support area 66 is formed using a polycrystalline silicon film at the same time as gate electrodes 45 of the CMOS 34 are formed, and an electric contact is established with the emitter support area 66 through a contact hole opened in the gate insulating film 44 in an area corresponding to the emitter region 49 .
- One end of the emitter support area 66 extends out of the emitter region 49 by a predetermined distance d1.
- the emitter support area 66 is used as a self alignment mask pattern.
- the distance d between the high impurity concentration p-type base region 50 and the emitter region 49 is slightly smaller than d1. Therefore, a desired distance d is achieved with a high precision by taking into account how much smaller the distance d will be than the predetermined distance d1 of the emitter support area 66 and compensating the extension d1 in advance.
- a Bi-CMOS semiconductor device 67 differs from the Bi-CMOS semiconductor device 31 of FIG. 1 in that a double diffused CMOSFET (DCMOSFET) 69 is included in addition to a bipolar transistor 68 and a CMOS 34 as a single unit in the Bi-CMOS 67 .
- a step for forming the DCMOSFET 69 is used for forming a high impurity concentration p-type base region 70 of the bipolar transistor 68 .
- a drain region 71 of the DCMOSFET 69 and an n-type well region 41 of the CMOSFET 34 are simultaneously formed. Then, when a p-type region 72 , which makes up a channel and has a higher level of impurity concentration than the p-type well 40 , is formed, the high impurity concentration p-type base region 70 is simultaneously formed in a base region 48 of the bipolar transistor 68 .
- a gate oxide film 44 and a gate electrode 73 of the DCMOSFET 69 are formed, and a p-type channel contact region 74 , an n-type source region 75 , and a drain contact region 76 are formed in the DCMOSFET 69 .
- an insulating film 46 and aluminum electrodes 47 are formed.
- One of the aluminum electrodes 47 that is formed to span over the p-type channel contact region 74 and the n-type source region 75 is a source electrode.
- Another one of the aluminum electrodes 47 that is formed on the drain contact region 76 is a drain electrode.
- the gate electrode 73 is electrically connected to the outside through a gate electrode metal, which is not illustrated.
- the high impurity concentration p-type base region 70 is formed in the bipolar transistor 68 without adding extra steps.
- the interface between the high impurity concentration p-type base region 70 and the insulating film 46 are so stable that relatively good device characteristics of the bipolar transistor 68 are acquired in the Bi-CMOS 67 .
- ultraviolet rays are exposed to a Bi-CMOSFET semiconductor device having the same structure as the Bi-CMOSFET semiconductor device 31 of FIG. 1 to remove hydrogen atoms from the interface, which is a Si—SiO 2 interface, between a high impurity concentration p-type base region 50 and an insulating film 46 and from the interface between a p-type base region 48 and the insulating film 46 .
- Positive fixed charges which is denoted by “X” marks in FIG. 12 , are generated at the interface. Changes in the amount of the positive fixed charges can be attributed to shifts of hydrogen atoms, which are bonded to silicon with dangling bonds at the interface, under certain biasing conditions used for driving the bipolar transistor 35 , or due to the manufacturing process of the Bi-CMOSFET semiconductor device.
- the passivation film 57 is exposed to ultraviolet rays to remove the hydrogen atoms located at the interface by adding energy to the hydrogen atoms.
- the passivation film 57 needs to transmit ultraviolet rays to expose the Si—SiO 2 interface to the ultraviolet rays and provide enough energy with the hydrogen atoms.
- the bipolar transistor 35 becomes more stable in the device characteristics.
- Ten samples that had not been exposed to ultraviolet rays showed changes in device characteristics between the initial conditions and after 300 hours of operation, as shown in FIG. 13 .
- three samples that had been exposed to ultraviolet rays showed substantially no changes in the device characteristics between the initial conditions and after 300 hours of operation, as shown in FIG. 14 .
- the benefit of the UV irradiation can be applied to the Bi-CMOSFET semiconductor device 1 of FIG. 24 , which has a wider spacing between the high impurity concentration p-type base region 20 and the emitter region 19 .
- a Bi-CMOSFET semiconductor device 77 differs from the Bi-CMOSFET semiconductor device of FIG. 12 in that an EPROM 78 is included in the Bi-CMOS device 77 .
- the EPROM 78 has a structure for erasing contents of the memory under an ultraviolet radiation, and, for this reason, a film that is highly transparent to ultraviolet rays is used as a passivation film 57 , just as in the Bi-CMOSFET semiconductor device of FIG. 12 .
- the EPROM 78 has a standard EPROM structure.
- an n-type well region 79 which is similar to an n-type well region 41 , is located in a low impurity concentration n-type silicon layer 37 , and p-type source and drain regions 80 are located in the n-type well region 79 .
- a floating gate 81 is located above a gate insulating film 44 , and a common gate 82 is located on the floating gate 81 with another insulating film in-between.
- the Bi-CMOS 77 Each time the Bi-CMOS 77 is exposed to ultraviolet rays for erasing the memory content in the EPROM 78 , hydrogen atoms at the interface between a base region 48 and an insulating film 46 in a bipolar transistor 35 are removed. Therefore, the bipolar transistor 35 of the Bi-CMOS 77 has more stable device characteristics than the bipolar transistor 35 of the Bi-CMOSFET semiconductor device 31 in FIG. 1 .
- a Bi-CMOSFET semiconductor device 83 differs from the Bi-CMOSFET semiconductor device 31 in FIG. 1 , which includes the high impurity concentration p-type base region 50 having a distance of 1 to 2 ⁇ m from the emitter region 49 , in that a polycrystalline silicon film 85 is located in the bipolar transistor 84 as a hydrogen barrier layer.
- the Bi-CMOSFET semiconductor device 83 the polycrystalline silicon film 85 is included in order to prevent the hydrogen atoms existing in a passivation film 57 , which is not shown in FIGS. 16A and 16B , from traveling to the interface between a base region 48 and an insulating film 44 of FIG. 16A and from changing the characteristics of a bipolar transistor 84 .
- the bipolar transistor 84 includes an emitter region 49 and a base contact region 50 a in the base region 48 .
- the polycrystalline silicon film 85 which is the hydrogen barrier film, is located above the interface between the base region 48 and the insulating film 44 of FIG. 16A in such a way that the polycrystalline silicon film 85 surrounds the emitter region 49 as viewed in FIG. 16B .
- the polycrystalline silicon film 85 is simultaneously formed at the step of forming gate electrodes 45 of a CMOSFET 34 of FIG. 16A . Therefore, the Bi-CMOSFET semiconductor device 83 of FIG. 16A can be manufactured using the manufacturing process shown by FIGS. 25A to 25 G, which are the ones for the proposed semiconductor device 1 of FIG. 24 , without any additional steps.
- a Bi-CMOSFET semiconductor device 96 differs from the Bi-CMOSFET semiconductor device 83 of FIG. 16A in that a bipolar transistor 86 includes an emitter electrode 87 , which is made of a polycrystalline silicon film, to function as a hydrogen barrier film.
- the Bi-CMOS device 96 includes a CMOSFET 34 having the same structure as the CMOSFET 34 in FIG. 16A .
- the bipolar transistor 84 of FIG. 16 a the polycrystalline silicon film 85 is floating.
- the emitter electrode 87 which is in electric contact with the emitter region 49 , has the same function as the polycrystalline silicon film 85 .
- the emitter electrode 87 is simultaneously formed in the process for forming the CMOSFET 34 , which is not shown. An emitter contact hole is formed in a gate insulating film 44 . Then, the emitter electrode 87 is formed from a polycrystalline silicon film, which is also used for forming gate electrodes 45 . The emitter electrode 87 is patterned in such a way that an edge of the emitter electrode 87 extends toward and near the edge of a base contact area 50 a . As a result, the emitter electrode 87 is located above the interface between the base region 48 and the insulating film 44 of FIG. 16A such that the interface is substantially completely covered by the emitter electrode 87 .
- the hydrogen atoms which can otherwise bond to silicon at the interface with dangling bonds and undesirably affect the characteristics of the bipolar transistor 86 , are not allowed to travel from an insulating film 46 or a passivation film 57 , which is not shown in FIG. 17 , so the bipolar transistor 86 has relatively stable device characteristics.
- a Bi-CMOSFET semiconductor device 97 differs from the Bi-CMOSFET semiconductor device 83 of FIG. 16A in that a bipolar transistor 88 includes an aluminum electrode 47 a as a base electrode and as a hydrogen barrier film.
- the Bi-CMOS device 97 includes a CMOSFET 34 having the same structure as the CMOSFET 34 in FIG. 16A .
- the aluminum electrode 47 a extends above the interface between a base region 48 and an insulating film 46 of FIG.
- the bipolar transistor 88 has relatively stable device characteristics.
- a Bi-CMOSFET semiconductor device 98 differs from the Bi-CMOSFET semiconductor device 97 of FIGS. 18A and 18B in that a bipolar transistor 89 includes an aluminum electrode 47 b as an emitter electrode and as a hydrogen barrier film.
- the Bi-CMOS device 97 includes a CMOSFET 34 having the same structure as the CMOSFET 34 in FIG. 16A .
- the aluminum electrode 47 b extends above the interface between a base region 48 and an insulating film 46 of FIG.
- the bipolar transistor 88 has relatively stable device characteristics in the same manner as the Bi-CMOSFET semiconductor device 97 of FIG. 18A .
- a Bi-CMOSFET semiconductor device 99 differs from the Bi-CMOSFET semiconductor device 83 of FIG. 16A in that a bipolar transistor 90 includes a silicon nitride film 91 as a hydrogen barrier film.
- the Bi-CMOS device 97 includes a CMOSFET 34 having the same structure as the CMOSFET 34 in FIG. 16A .
- the silicon nitride film 91 is deposited to cover the substantially entire bipolar transistor 90 after a gate oxide film 44 is formed. Then, an insulating film 46 , aluminum electrodes 47 , and a passivation film 57 , which is formed on the aluminum electrode 47 although not shown in FIG. 20 . Therefore, the bipolar transistor 20 has relatively stable device characteristics.
- each application circuit 92 , 93 , 95 includes a pair of npn transistors, which are bipolar transistors Tr 1 a and Tr 2 a , Tr 1 b and Tr 2 b , Tr 1 c and Tr 2 c .
- the bipolar transistors in the Bi-CMOS devices according to the first through twelfth embodiments are used as the pair of transistors Tr 1 a and Tr 2 a , Tr 1 b and Tr 2 b , Tr 1 c and Tr 2 c to ensure the performance parity between the pair in each circuits 92 , 93 , 95 and to achieve high performance.
- each circuit 92 , 93 , 95 the amount of shifts in transistor characteristics of the pair during operation differs from each other because each bipolar transistor is exposed to different biasing conditions during operation. Therefore, the balance in performance between the pair tends to be lost. Thus, all of the circuits 92 , 93 , 95 require that the bipolar transistors of the pair offer stable characteristics in spite of varying biasing conditions.
- the first application circuit 92 of FIG. 24 is designed to provide an output current Iout in response to an input current Iin, and a current mirror circuit in the input stage of the first application circuit 92 includes the pair of bipolar transistors Tr 1 a , Tr 2 a , which have transistor characteristics identical with each other.
- the voltage Vce1 between the collector and the emitter of the transistor Tr 1 a , the collector and the base of which are shorted, is equivalent to the forward bias voltage Vf between the base and the emitter of a bipolar transistor Tr 3 .
- the voltage Vce2 between the collector and the emitter of the transistor Tr 2 a on the output side is equal to a balance between a supply voltage Vcc and the voltage Vf between the base and the emitter of the transistor Tr 3 .
- the voltages Vce1 and Vce2 are generally not equal to each other, and so are biasing conditions between the transistors Tr 1 a , Tr 2 a .
- the shifts in device characteristics of the transistors Tr 1 a , Tr 2 a which are used as a pair, becomes different from each other during operation and the performance parity between the transistors Tr 1 a , Tr 2 a to break down, if the bipolar transistor 5 in the proposed Bi-CMOSFET semiconductor device 1 of FIG. 24 is used for the pair of transistors Tr 1 a , Tr 2 a .
- stable circuit operation can be maintained in the circuit 92 of FIG. 21 by using the bipolar transistors in the Bi-CMOS devices according to the first through twelfth embodiments for the pair of transistors Tr 1 a , Tr 2 a.
- the second application circuit 93 of FIG. 25 is a band gap circuit, which is used for outputting a reference voltage of, for example, 1.3 V.
- currents of two different magnitudes are respectively provided for transistors Tr 1 b , Tr 2 b in a band gap circuit 94 of the second application circuit 93 .
- the voltage drop due to a resistance R 3 which is connected to the emitter of the transistor Tr 1 b and has an electric resistance of R3 ohms, leads to the following relationship between voltage Vbe1 and voltage Vbe2, which are respectively the voltage between the base and the emitter of the transistor Tr 1 b and the voltage between the base and the emitter of the transistor Tr 2 b:
- Vbe 2 ⁇ Vbe 1 R 3 ⁇ i,
- the transistors Tr 1 b , Tr 2 b which are used in a pair, are driven under different conditions.
- stable circuit operation can be maintained in the circuit 93 of FIG. 22 by using the bipolar transistors in the Bi-CMOS devices according to the first through twelfth embodiments for the pair of transistors Tr 1 b , Tr 2 b.
- the third application circuit 95 of FIG. 26 is also a band gap circuit, which is used for outputting a reference voltage Vref using a band gap circuit.
- transistor Tr 1 c , Tr 2 c which are used in a pair to make up the band gap circuit, operate under the following conditions, and a collector voltage and a base voltage of the transistor Tr 2 c are inputted into input terminals to an op amp Op1:
- the transistors Trlc, Tr 2 c are driven under different conditions.
- stable circuit operation can be maintained in the circuit 95 of FIG. 23 by using the bipolar transistors in the Bi-CMOS devices according to the first through twelfth embodiments for the pair of transistors Tr 1 c , Tr 2 c.
- the present invention is not limited to the Bi-CMOS devices of the first through twelfth and can also apply to the following variations.
- Each method used in the Bi-CMOS devices of the first through twelfth of the embodiments can be used alone or in combinations. That is to say, the first group of methods used in the first through fifth embodiments, in which the high impurity concentration p-type base region 50 is used, the second group of methods used in the sixth and the seventh embodiments, in which ultraviolet rays are exposed to the Bi-CMOS devices, and the third group of methods used in the eighth through the twelfth embodiments, in which the hydrogen barrier film is used, may be combined with each other in various arrangements.
- the transistors are isolated from each other by the trenches 38 and the insulating layer 33 in the Bi-CMOS devices of the first through twelfth embodiments, the transistors may be isolated by PN junctions.
- the polycrystalline silicon film 85 which is the hydrogen barrier film, is formed to surround the emitter region 49 in the Bi-CMOS device of FIG. 16A . However, if the emitter region 49 is formed to be in contact with the adjacent LOCOS 39 at one side of the emitter region 49 , the polycrystalline silicon film may surround the emitter region 49 on the remaining three sides.
- both the base electrode 47 a and the emitter electrode 47 b may extend out.
Abstract
In the manufacturing process of a Bi-CMOS semiconductor device, which includes a CMOSFET and a bipolar transistor, the steps for forming a well region, source regions, and drain regions of the CMOSFET are also used for forming the bipolar transistor. One of the steps is used for introducing impurities of the same conductivity type in a surface of a base region of the bipolar transistor in order to form a high impurity concentration region in the surface. The high impurity concentration region is formed such that the distance between an emitter region of the bipolar transistor and the high impurity concentration region becomes 1 to 2 μm. The shift in device characteristics of the bipolar transistor is improved by the high impurity concentration region even if the impurity concentration is relatively low at the surface of the base region of the bipolar transistor.
Description
- This application is based on and incorporates herein by reference Japanese Patent Application No. 2001-341906 filed on Nov. 7, 2001.
- The present invention relates to a semiconductor device including a CMOSFET and a bipolar transistor and to a method for manufacturing the semiconductor device. In the method, the bipolar transistor is formed by taking advantage of steps for forming a well region, source regions, and drain regions of the CMOSFET.
- With a manufacturing process for a semiconductor device called a Bi-CMOS IC, in which bipolar transistors and CMOSFETs are formed on the same substrate, there is a technology for forming, for example, base regions of the bipolar transistors using diffusion regions for forming wells for the CMOSFETs and for forming emitter regions using diffusion regions for forming the source and drain regions in order to reduce the number of process steps. In a
semiconductor device 1 shown inFIG. 24 , a silicon-on-insulator (SOI) substrate is included., and aCMOSFET 4 and abipolar transistor 5 are located over aninsulating film 3 on asilicon substrate 2. - An SOI layer included in the SOI substrate includes a high impurity concentration n-
type silicon layer 6 and a low impurity concentration n-type silicon layer 7 on theinsulating film 3, and thetransistors device 1 are isolated bytrenches 8 and by LOCOS 9 in a surface of thedevice 1. The CMOSFET 4 includes p channel-type and n channel-type MOSFETs type well 10 and a p-type well 11 are included, respectively. Source anddrain regions type well 10 and the p-type well 11, respectively. Eachgate electrode 15 is located on a gate oxide film 14. Contact holes are located in aninsulating film 16.Aluminum electrodes 17 are in electric-contact with the source and drain-regions - An
npn transistor 5 includes a low impurity concentration n-type silicon layer 7 as a collector region, in a surface of which a p-type base region 18 is located. An n-type emitter region 19 and abase contact region 20 are located in a surface of the p-type base region 18. Acollector contact region 21 is also located in the surface of thesilicon layer 7. - The
semiconductor device 1 is formed by the following process flow, which is shown inFIGS. 25A to 25G. As shown inFIG. 25A , anSOI substrate 210, in which n-type singlecrystal silicon layers insulating layer 3, is prepared. Then,trenches 8 are formed outside the areas where fortransistors FIG. 25B . Then,wells base region 18 is formed, as shown inFIG. 25C . Next, as shown inFIG. 25D ,LOCOS 9 are formed, and a gate oxide film 14 andgate electrodes 15 are formed, as shown inFIG. 25F . - Using the
gate electrodes 15 as a mask, the source anddrain regions MOSFETs FIG. 25F . Simultaneously, anemitter region 19, abase contact region 20, and acollector contact region 21 are formed. Finally, aninsulating film 16 and thealuminum electrodes 17 are formed to complete a Bi-CMOSFETsemiconductor device 1. - Because the
npn transistor 5 is formed using a CMOSFET manufacturing process, the Bi-CMOSFETsemiconductor device 1 has the following drawback with the characteristics of thenpn transistor 5. Thebase region 18 of thetransistor 5 is simultaneously formed at the step for forming the p-type well 11, so the surface impurity concentration of thebase region 18 is generally relatively low. Therefore, the characteristics of thetransistor 5 can shift due to a slight shift in the amount of charges at the interface between the p-type base region 18 and theinsulating film 16, which is made of SiO2, under a certain biasing condition for driving thetransistor 5. The interface is shown with small x-marks inFIG. 24 . As a result, the characteristics of thetransistor 5 become unstable, and operating errors are caused in some circuit designs. - The present invention has been made in view of the above aspects. A first object of the present invention is to provide a semiconductor device that is relatively stable in the device characteristics, which are affected by the impurity concentration at a surface of a base region, even when a bipolar transistor and a CMOSFET is simultaneously formed in a device using a CMOSFET process. A second object is to provide a method of manufacturing the semiconductor device.
- In the present invention, a CMOSFET and a bipolar transistor are formed into a single unit on a substrate. The steps for forming a well region, source regions, and drain regions of the CMOSFETs are also used for forming the bipolar transistors, and one of the steps is used for introducing impurities of the same conductivity type in a surface of a base region of the bipolar transistor in order to form a high impurity concentration area in the surface.
- Alternatively, the surface of the base region is exposed by ultraviolet rays in order to reduce the amount of charges at the interface between the base region and an insulating film located on the surface of the base region.
- Alternatively, after an insulating film is formed at the surface of the base region of the bipolar transistor, a hydrogen barrier film is formed such that the hydrogen barrier film covers the surface of the base region.
- The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:
-
FIG. 1 is a partial cross-sectional view of a semiconductor device according to a first embodiment of the present invention; -
FIG. 2 is a graph showing the simulation results obtained for the Gummel characteristics of an npn transistor having a surface impurity concentration of 2×1016 cm−3 in a base region of the transistor in both cases with and without positive fixed charges at an interface between a base region and an insulating film located on the base region; -
FIG. 3 is a graph showing the simulation results for the direct current amplification (hFE) characteristics of an npn transistor with respect to impurity concentration at the surface of a base region of the transistor in both cases with and without the positive fixed charges; -
FIG. 4 is a graph showing the simulation results for the direct current amplification (hFE) characteristics of an npn transistor with respect to the distance d between a high impurity concentration region and an emitter region of the transistor in both cases with and without charges; -
FIG. 5 is a graph showing the actually measured results for the direct current amplification (hFE) characteristics of an npn transistor that has the same structure as used for the simulation ofFIG. 4 ; -
FIG. 6 is a graph showing the correlation between the reverse bias breakdown voltage and distance between a high impurity concentration region and an emitter region of an npn transistor; -
FIG. 7 is a graph showing the correlation between the changes in output voltage and time with various distances between a high impurity concentration region and an emitter region of an npn transistor; -
FIG. 8A is a partial cross-sectional view of a first variation of a semiconductor device according to a second embodiment,FIG. 8B is a plan view of a bipolar transistor in the first variation,FIG. 8C is a partial cross-sectional view of a second variation of the semiconductor device according to the second embodiment,FIG. 8D is a plan view of a bipolar transistor in the second variation; -
FIGS. 9A to 9P are cross-sectional views showing the structure of a semiconductor device according to a third embodiment in the manufacturing process of the device; -
FIG. 10 is a cross-sectional view of a bipolar transistor of a semiconductor device according to a fourth embodiment; -
FIG. 11 is a partial cross-sectional view of a semiconductor device according to a fifth embodiment; -
FIG. 12 is a partial cross-sectional view of a semiconductor device according to a sixth embodiment; -
FIG. 13 is a graph showing the correlation between the direct current amplification factor and the collector current without any ultraviolet radiation; -
FIG. 14 is a graph showing the correlation between the direct current amplification factor and the collector current with ultraviolet radiation; -
FIG. 15 is a partial cross-sectional view of a semiconductor device according to a seventh embodiment; -
FIG. 16A is a partial cross-sectional view of a semiconductor device according to an eighth embodiment andFIG. 16B is a plan view of a bipolar transistor in the device according to the seventh embodiment; -
FIG. 17 is a cross-sectional view of a bipolar transistor in a semiconductor device according to a ninth embodiment; -
FIG. 18A is a cross-sectional view of a bipolar transistor in a semiconductor device according to a tenth embodiment andFIG. 18B is a plan view of the bipolar transistor according to the tenth embodiment; -
FIG. 19A is a cross-sectional view of a bipolar transistor in a semiconductor device according to an eleventh embodiment andFIG. 19B is a plan view of the bipolar transistor according to the eleventh embodiment; -
FIG. 20 is a cross-sectional view of a bipolar transistor in a semiconductor device according to a twelfth embodiment; -
FIG. 21 is a circuit diagram according to a thirteenth embodiment; -
FIG. 22 is another circuit diagram according to the thirteenth embodiment; -
FIG. 23 is another circuit diagram according to the thirteenth embodiment; -
FIG. 24 is a cross-sectional view of a proposed semiconductor device; and -
FIGS. 25A to 25G are cross-sectional views showing the structure of the device inFIG. 24 in the manufacturing process of the device. - The present invention will be described in detail with reference to various embodiments.
- First Embodiment
- As shown in
FIG. 1 , aBi-CMOS semiconductor device 31 includes aCMOSFET 34 and abipolar transistor 35. TheCMOSFET 34 and thetransistor 35 are located on an insulatingfilm 33, which is located on asilicon substrate 32. - The
Bi-CMOS semiconductor device 31 is formed from an SOI substrate, which has an SOI layer including a high impurity concentration n-type silicon layer 36 and a low impurity concentration n-type silicon layer 37, impurity concentration of which is, for example, approximately 1×1015 cm−3. TheCMOSFET 34 and thetransistor 35 include the silicon layers 36 and 37. TheCMOSFET 34 and thebipolar transistor 35 are surrounded and isolated by thetrenches 38, respectively. Furthermore, theCMOSFET 34 and thebipolar transistor 35 are isolated by local-oxidation-of-silicon (LOCOS)areas 39 at the surface of thedevice 31. TheCMOSFET 34 includes ann channel MOSFET 34 a anda p channel MOSFET 34 b. A p-type well 40, which has an impurity concentration of, for example, approximately 4×1016 cm−3, and an n-type well 41 are located in the low impurity concentration n-type layer 37. N-type source and drainregions 42 are located in the p-type well 40. P-type source and drainregions 43 are located in the n-type well 41. -
Gate electrodes 45 are made of polycrystalline silicon. Eachgate electrode 45 is located on agate insulating film 44, which is located above each channel between the source region and thedrain region CMOSFET 34 is covered by an insulatingfilm 46, andaluminum electrodes 47 are in electric contact with the source and drainregions film 46. - In the
bipolar transistor 35, a p-type base region 48, which has an impurity concentration of, for example, approximately 4×1016 cm−3, is located in a surface of the low impurity concentration n-type layer 37. A high impurity concentration n-type emitter region 49, which has an impurity concentration of, for example, approximately 1×1020 cm−3, is located in a surface of the p-type base region 48. In addition, a high impurity concentration p-type base region 50, which has an impurity concentration of, for example, approximately 1×1020 cm−3, is located in the surface of the p-type base region 48. The high impurity concentration p-type base region 50 is extends from an end of theLOCOS 39 to a position having a distance d from an end of theemitter region 49. A high impurity concentration n-typecollector contact region 51 is located in a surface of the low impurity concentration n-type layer 37. The surface of thebipolar transistor 35 is also covered by an insulatingfilm 46, andaluminum electrodes 47 are in electric contact with theemitter region 49, thebase region 50, and thecollector contact region 51 through contact holes in the insulatingfilm 46. - In the
Bi-CMOS semiconductor device 31, thebase region 48 of thebipolar transistor 35 is simultaneously formed when the p-type well 41 of theCMOSFET 34 is formed. Furthermore, theemitter region 49 and thecollector contact region 51 are simultaneously formed when the n-type source and drainregions 42 are formed. The high impurity concentration p-type base region 50 is simultaneously formed when the p-type source and drainregions 43 are formed. - In the
Bi-CMOS semiconductor device 31, the impurity concentration of the p-type well 40 is lower than the concentration required for the base of a bipolar transistor. The impurity concentration is, for example, approximately 4×1016 cm−3. Therefore, it is essentially undesired that thebase region 48 is formed at the step of forming the p-type well 40 in terms of device characteristics. However, the surface area of thebase region 48 is mostly covered by theemitter region 49 and the high impurity concentration p-type base region 50, and thebase region 48 is in contact with the insulatingfilm 46 at the space of as short as 1 to 2 μm between theemitter region 49 and thebase region 50. Therefore, the instability in operating characteristics of thebipolar transistor 35, which is caused by a relatively low impurity concentration at the surface of thebase region 48, is improved, and the operating characteristics becomes relatively stable. The reason is as follows. - In the
Bi-CMOSFET semiconductor device 1 ofFIG. 24 , the impurity concentration at the surface of thebase region 18 can be as low as 1×1018 cm−3 or less for the sake of the design of theCMOSFET 4 when simultaneously forming thebase region 18 of thebipolar transistor 5 and the p-type well region 11 of theCMOSFET 4. In that case, the operating characteristics stray from desired values, because an n-type inversion layer can be formed at the surface of thebase region 18 when thebipolar transistor 5 is driven under certain biasing conditions, or when an amount of the positive fixed charges increases at the Si—SiO2 interface, which is located between thebase contact region 20 and theemitter region 19, in the manufacturing process of thedevice 1. - The inventor of the present invention conducted the following simulations to study the above problem. As shown in
FIG. 2 , the collector currents increase due to the positive fixed charges. The direct current gain hFE is expressed in the equation, hFE=Ic/Ib, where Ib is a base current, and Ic is a collector current. In general, the base current Ib increases when the number of recombination sites increases due to a higher density of defects such as a crystal defect and a dangling bond in the emitter-base depletion layer and the corresponding recombination current increases. On the other hand, the collector current Ic changes with a change in the transistor structure such as impurity concentrations, depths, and sizes of the base region and the emitter region. The simulation results show that the base current Ib substantially does not change under the effect of the positive fixed charges while the collector current Ic increases. In other words, The Gummel characteristics inFIG. 2 show that the transistor structure changes under the effect of the positive fixed charges when the impurity concentration is too low at the surface of the base region. - Furthermore, as shown in
FIG. 3 , the above problems encountered with the proposed device ofFIG. 24 can be addressed by raising the impurity concentration at the surface of the base region. The first embodiment is based on the above simulation results, so thebipolar transistor 35 includes the high impurity concentration p-type base region 50 for raising the impurity concentration at the surface of thebase region 48. - In the
Bi-CMOS semiconductor device 31 ofFIG. 1 , the distance d between theemitter region 49 and the high impurity concentration p-type base region 50 is 1 to 2 μm. Therefore, the impurity concentration is relatively high across the substantially entire surface of thebase region 48. The position for forming the high impurity concentration p-type base region 50 will be described in detail. As shown inFIG. 4 , hFE is relatively stable, with or without the charges, when the distance d is 1 to 2 μm. As shown inFIG. 5 , the hFE values go down rapidly when the distance d is shorter than 1 μm. Furthermore, as shown inFIG. 6 , the reverse bias breakdown voltage Vz (V) between the emitter region and the base region changes with the distance d, and the breakdown voltage goes down rapidly when the distance d is shorter than 1 μm. Therefore, the lower limit for the distance d should be 1 μm. As shown inFIG. 7 , substantially no changes in the output voltage are observed and the output voltage becomes stable when the distance d is shorter than 2 μm. From the results shown in FIGS. 4 to 7, it is concluded that an optimal range for the distance d should be 1 to 2 μm. - In the
Bi-CMOS semiconductor device 31 ofFIG. 1 , shifts in the characteristics of thebipolar transistor 35, which is caused by otherwise a low impurity concentration at the surface of thebase region 48, is improved by forming the high impurity concentration p-type base region 50 at the surface of thebase region 48. Moreover, the production cost is lowered because the high impurity concentration p-type base region 50 is simultaneously formed when the p-type source and drainregions 43 are formed in the n-type well region 41 of theCMOSFET 34. Furthermore, the distance d between the high impurity concentration p-type base region 50 and theemitter region 49 is set at 1 to 2 μm, so the shifts in the device characteristics are improved while sustaining the direct current amplification hFE and the breakdown voltage Vz. - Second Embodiment
-
Bi-CMOS semiconductor devices 52 ofFIGS. 8A to 8D are different in structure of the high impurity concentration p-type base region from theBi-CMOS semiconductor device 31 ofFIG. 1 . In theBi-CMOS semiconductor device 52 ofFIGS. 8A and 8B , a high impurity concentration p-type base region 54 is formed to surround anemitter region 49 in abipolar transistor 53 of theBi-CMOS device 52, as shown inFIG. 8B , in whichaluminum electrodes 47 are not illustrated. In theBi-CMOS semiconductor device 52 ofFIGS. 8 c and 8 d, abipolar transistor 53 includes a high impurity concentration p-typebase contact region 54 a, on which analuminum electrode 47 is formed, and a high impurity concentration p-type base region 54 b that surrounds anemitter region 49, as shown inFIG. 8D , in whichaluminum electrodes 47 are not illustrated. - In the
Bi-CMOS semiconductor devices 52 ofFIGS. 8A to 8D, the size of the surface, at which thebase region 48 is in contact with the insulatingfilm 46 is smaller than in theBi-CMOS semiconductor device 31 ofFIG. 1 , so the changes in device characteristics, which is caused by an inversion at the surface, is further reduced and stabilized in theBi-CMOS semiconductor devices 52 ofFIGS. 8A to 8D. - Third Embodiment
- As shown in
FIG. 9P , aBi-CMOS semiconductor device 55 differs from theBi-CMOS semiconductor devices 52 ofFIGS. 8A to 8D in that a selfalignment mask pattern 56 is included in order to precisely control the distance d between a high impurity concentration p-type base region 54 and anemitter region 49. An additional process step is not required for forming the selfalignment mask pattern 56. - As shown in
FIG. 9P , the selfalignment mask pattern 56, which is made of a polycrystalline silicon film, is located over the surface of abase region 48 between the high impurity concentration p-type base region 54 and theemitter region 49 in addition to the structures of theBi-CMOS semiconductor devices 52 ofFIGS. 8A to 8D. InFIG. 9P , apassivation film 57 for protecting the device surface includingaluminum electrodes 47 is illustrated. - The manufacturing steps for forming the
Bi-CMOS semiconductor device 55 will be described. Firstly, anSOI substrate 58 shown inFIG. 9A is prepared. Asilicon substrate 32 is several hundred microns in thickness. A high impurity concentration n-type silicon layer 36 and a low impurity concentration n-type silicon layer 37 are located on an insulatingfilm 33 made of a silicon oxide film, which is located on thesubstrate 32. Then,trenches 38 for device isolation are formed in theSOI substrate 58, as shown inFIG. 9B . Thetrenches 38 are formed by forming grooves, depositing an insulating film on the sidewalls defining the grooves, and filling the grooves with polycrystalline silicon for planarization. - Next, an ion implanted
area 59, corresponding to an n-type well region 41, is formed by ion implanting an n-type impuritiy, as shown inFIG. 9C . Similarly, an ion implantedarea 60, corresponding to a p-type well region 40, is formed by ion implanting a p-type impurity, as shown inFIG. 9D . At the step for forming the p-type well region 40, an ion implantedarea 61, corresponding to a p-type base region 48 of abipolar transistor 53, is also formed. - Next, the p-
type well region 40, the n-type well region 41, and the p-type base region 48 are formed from the ion implantedareas 59 through 61 by driving in the impurities at a diffusion step, as shown inFIG. 9E . LOCOS 39 are formed at predetermined locations on the substrate surface for device isolation at the surface, as shown inFIG. 9F . Next, agate oxide film 44 is formed on the surface of the substrate ofFIG. 9F , andgate electrodes 45 are formed from a polycrystalline silicon film, as shown inFIG. 9G . - At the same time, a self
alignment mask pattern 56 is also formed from the polycrystalline silicon film on the surface of thebipolar transistor 53. Themask pattern 56 has a width corresponding to the distance d between anemitter region 49 and a high impurity concentration p-type base region 50 of thebipolar transistor 53. - Next, a photo resist 62 is patterned to form p-type source and drain
regions 43 in the n-type well region 41 and a high impurity concentration p-type base region 54 in the p-type base region 48, as shown inFIG. 9H . The photo resist 62 is formed to be slightly offset from the edges of themask pattern 56. As a result, the positions of the edges of the high impurity concentration p-type base region 54 can be aligned with a higher precision than an alignment precision achieved by the photo resist 62. Next, p-type impurities are introduced by ion implanting into the openings in the photo resist 62 to form the p-type source and drainregions 43 and the high impurity concentration p-type base region 54, as shown inFIG. 9I . Then, the photo resist 62 is stripped off, as shown inFIG. 9J , and a photo resist 63 is patterned for forming n-type source and drainregions 42, the high impurity concentration n-type emitter region 49, and acollector contact region 51, as shown inFIG. 9K . The edges of the photo resist 63 are slightly offset from the edges of themask pattern 56. Then, n-type impurities are introduced by ion implanting to form the n-type source and drainregions 42, the high impurity concentration n-type emitter region 49, and thecollector contact region 51, as shown inFIG. 9L . - Then, the photo resist 63 is stripped off, as shown in
FIG. 9M , and an insulatingfilm 46 is formed with a BPSG film, as shown inFIG. 9N . Contact holes are opened by photolithography and etching, andaluminum electrodes 47 are formed, as shown inFIG. 90 . Finally, apassivation film 57 is formed, and openings are made at the electrode pads to complete the wafer process, as shown inFIG. 9P . - The distance d between the
emitter region 49 and the high impurity concentration p-type base region 54 can be controlled precisely by using the selfalignment mask pattern 56 to achieve a high degree of process control. Furthermore, the production cost is lowered by simultaneously forming thegate electrodes 45 of theCMOSFET 34 and the selfalignment mask pattern 56 from the same polycrystalline silicon film because no additional process steps are required. - Fourth Embodiment
- As shown in
FIG. 10 , abipolar transistor 65 in aBi-CMOS device 64 has anemitter support area 66 as a self alignment mask pattern. Although not shown, theBi-CMOS device 64 includes aCMOS 34 having the same structure as theCMOS 34 inFIG. 1 . - In the
bipolar transistor 65, anemitter region 49 is formed before p-type source and drainregions 43 of theCMOS 34 are formed, and theemitter support area 66, which is electrically connected to theemitter region 49, is formed after agate insulating film 44 is formed. Theemitter support area 66 is formed using a polycrystalline silicon film at the same time asgate electrodes 45 of theCMOS 34 are formed, and an electric contact is established with theemitter support area 66 through a contact hole opened in thegate insulating film 44 in an area corresponding to theemitter region 49. One end of theemitter support area 66 extends out of theemitter region 49 by a predetermined distance d1. - Next, when forming the high impurity concentration p-
type base region 50 by introducing impurities, theemitter support area 66 is used as a self alignment mask pattern. The distance d between the high impurity concentration p-type base region 50 and theemitter region 49 is slightly smaller than d1. Therefore, a desired distance d is achieved with a high precision by taking into account how much smaller the distance d will be than the predetermined distance d1 of theemitter support area 66 and compensating the extension d1 in advance. - Fifth Embodiment
- As shown in
FIG. 11 , aBi-CMOS semiconductor device 67 differs from theBi-CMOS semiconductor device 31 ofFIG. 1 in that a double diffused CMOSFET (DCMOSFET) 69 is included in addition to abipolar transistor 68 and aCMOS 34 as a single unit in the Bi-CMOS 67. A step for forming theDCMOSFET 69 is used for forming a high impurity concentration p-type base region 70 of thebipolar transistor 68. - In the manufacturing process of the Bi-CMOS 67, a
drain region 71 of theDCMOSFET 69 and an n-type well region 41 of theCMOSFET 34 are simultaneously formed. Then, when a p-type region 72, which makes up a channel and has a higher level of impurity concentration than the p-type well 40, is formed, the high impurity concentration p-type base region 70 is simultaneously formed in abase region 48 of thebipolar transistor 68. Next, agate oxide film 44 and agate electrode 73 of theDCMOSFET 69 are formed, and a p-typechannel contact region 74, an n-type source region 75, and adrain contact region 76 are formed in theDCMOSFET 69. Subsequently, an insulatingfilm 46 andaluminum electrodes 47 are formed. One of thealuminum electrodes 47 that is formed to span over the p-typechannel contact region 74 and the n-type source region 75 is a source electrode. Another one of thealuminum electrodes 47 that is formed on thedrain contact region 76 is a drain electrode. Thegate electrode 73 is electrically connected to the outside through a gate electrode metal, which is not illustrated. - In the manufacturing process of the Bi-CMOS 67, the high impurity concentration p-
type base region 70 is formed in thebipolar transistor 68 without adding extra steps. The interface between the high impurity concentration p-type base region 70 and the insulatingfilm 46 are so stable that relatively good device characteristics of thebipolar transistor 68 are acquired in the Bi-CMOS 67. - Sixth Embodiment
- As shown in
FIG. 12 , in the method according to the sixth embodiment, ultraviolet rays are exposed to a Bi-CMOSFET semiconductor device having the same structure as theBi-CMOSFET semiconductor device 31 ofFIG. 1 to remove hydrogen atoms from the interface, which is a Si—SiO2 interface, between a high impurity concentration p-type base region 50 and an insulatingfilm 46 and from the interface between a p-type base region 48 and the insulatingfilm 46. - Positive fixed charges, which is denoted by “X” marks in
FIG. 12 , are generated at the interface. Changes in the amount of the positive fixed charges can be attributed to shifts of hydrogen atoms, which are bonded to silicon with dangling bonds at the interface, under certain biasing conditions used for driving thebipolar transistor 35, or due to the manufacturing process of the Bi-CMOSFET semiconductor device. - It is known that when an insulating film containing a large amount of hydrogen atoms such as a silicon nitride film formed by a plasma CVD method is used as a
passivation film 57, hydrogen atoms diffuse to the interface during a thermal treatment step. Therefore, device characteristics of thebipolar transistor 35 are further stabilized by providing theBi-CMOSFET semiconductor device 1 ofFIG. 24 with a treatment step for reversing the adverse effects of such hydrogen atoms. - As shown in
FIG. 12 , after thepassivation film 57 is formed and annealed, thepassivation film 57 is exposed to ultraviolet rays to remove the hydrogen atoms located at the interface by adding energy to the hydrogen atoms. Thepassivation film 57 needs to transmit ultraviolet rays to expose the Si—SiO2 interface to the ultraviolet rays and provide enough energy with the hydrogen atoms. - By removing the hydrogen atoms from the Si—SiO2 interface with ultraviolet rays after the formation and annealing of the
passivation film 57, thebipolar transistor 35 becomes more stable in the device characteristics. Ten samples that had not been exposed to ultraviolet rays showed changes in device characteristics between the initial conditions and after 300 hours of operation, as shown inFIG. 13 . On the other hand, three samples that had been exposed to ultraviolet rays showed substantially no changes in the device characteristics between the initial conditions and after 300 hours of operation, as shown inFIG. 14 . - Although ultraviolet rays are exposed to the Bi-CMOSFET semiconductor device having the same structure as the
Bi-CMOSFET semiconductor device 31 ofFIG. 1 in the method ofFIG. 12 , the benefit of the UV irradiation can be applied to theBi-CMOSFET semiconductor device 1 ofFIG. 24 , which has a wider spacing between the high impurity concentration p-type base region 20 and theemitter region 19. - Seventh Embodiment
- As shown in
FIG. 15 , aBi-CMOSFET semiconductor device 77 differs from the Bi-CMOSFET semiconductor device ofFIG. 12 in that anEPROM 78 is included in theBi-CMOS device 77. TheEPROM 78 has a structure for erasing contents of the memory under an ultraviolet radiation, and, for this reason, a film that is highly transparent to ultraviolet rays is used as apassivation film 57, just as in the Bi-CMOSFET semiconductor device ofFIG. 12 . - The
EPROM 78 has a standard EPROM structure. In theEPROM 78, an n-type well region 79, which is similar to an n-type well region 41, is located in a low impurity concentration n-type silicon layer 37, and p-type source and drainregions 80 are located in the n-type well region 79. A floatinggate 81 is located above agate insulating film 44, and acommon gate 82 is located on the floatinggate 81 with another insulating film in-between. - Each time the Bi-CMOS 77 is exposed to ultraviolet rays for erasing the memory content in the
EPROM 78, hydrogen atoms at the interface between abase region 48 and an insulatingfilm 46 in abipolar transistor 35 are removed. Therefore, thebipolar transistor 35 of the Bi-CMOS 77 has more stable device characteristics than thebipolar transistor 35 of theBi-CMOSFET semiconductor device 31 inFIG. 1 . - Eighth Embodiment
- As shown in
FIGS. 16A and 16B , aBi-CMOSFET semiconductor device 83 differs from theBi-CMOSFET semiconductor device 31 inFIG. 1 , which includes the high impurity concentration p-type base region 50 having a distance of 1 to 2 μm from theemitter region 49, in that apolycrystalline silicon film 85 is located in thebipolar transistor 84 as a hydrogen barrier layer. - In the method of
FIG. 12 , ultraviolet rays were exposed to the Bi-CMOSFET semiconductor device ofFIG. 12 for removing the hydrogen atoms, which are bonded to silicon with dangling bonds and undesirably affect the characteristics of thebipolar transistor 35, from the Si—SiO2 interface. On the other hand, in theBi-CMOSFET semiconductor device 83, thepolycrystalline silicon film 85 is included in order to prevent the hydrogen atoms existing in apassivation film 57, which is not shown inFIGS. 16A and 16B , from traveling to the interface between abase region 48 and an insulatingfilm 44 ofFIG. 16A and from changing the characteristics of abipolar transistor 84. - The
bipolar transistor 84 includes anemitter region 49 and abase contact region 50 a in thebase region 48. However, thepolycrystalline silicon film 85, which is the hydrogen barrier film, is located above the interface between thebase region 48 and the insulatingfilm 44 ofFIG. 16A in such a way that thepolycrystalline silicon film 85 surrounds theemitter region 49 as viewed inFIG. 16B . Thepolycrystalline silicon film 85 is simultaneously formed at the step of forminggate electrodes 45 of a CMOSFET 34 ofFIG. 16A . Therefore, theBi-CMOSFET semiconductor device 83 ofFIG. 16A can be manufactured using the manufacturing process shown byFIGS. 25A to 25G, which are the ones for the proposedsemiconductor device 1 ofFIG. 24 , without any additional steps. - Ninth Embodiment
- As shown in
FIG. 17 , aBi-CMOSFET semiconductor device 96 differs from theBi-CMOSFET semiconductor device 83 ofFIG. 16A in that abipolar transistor 86 includes anemitter electrode 87, which is made of a polycrystalline silicon film, to function as a hydrogen barrier film. Although not shown, theBi-CMOS device 96 includes a CMOSFET 34 having the same structure as theCMOSFET 34 inFIG. 16A . In thebipolar transistor 84 ofFIG. 16 a, thepolycrystalline silicon film 85 is floating. In thebipolar transistor 86 ofFIG. 17 , on the other hand, theemitter electrode 87, which is in electric contact with theemitter region 49, has the same function as thepolycrystalline silicon film 85. - The
emitter electrode 87 is simultaneously formed in the process for forming theCMOSFET 34, which is not shown. An emitter contact hole is formed in agate insulating film 44. Then, theemitter electrode 87 is formed from a polycrystalline silicon film, which is also used for forminggate electrodes 45. Theemitter electrode 87 is patterned in such a way that an edge of theemitter electrode 87 extends toward and near the edge of abase contact area 50 a. As a result, theemitter electrode 87 is located above the interface between thebase region 48 and the insulatingfilm 44 ofFIG. 16A such that the interface is substantially completely covered by theemitter electrode 87. - Therefore, the hydrogen atoms, which can otherwise bond to silicon at the interface with dangling bonds and undesirably affect the characteristics of the
bipolar transistor 86, are not allowed to travel from an insulatingfilm 46 or apassivation film 57, which is not shown inFIG. 17 , so thebipolar transistor 86 has relatively stable device characteristics. - Tenth Embodiment
- As shown in
FIGS. 18A and 18B , aBi-CMOSFET semiconductor device 97 differs from theBi-CMOSFET semiconductor device 83 ofFIG. 16A in that abipolar transistor 88 includes analuminum electrode 47 a as a base electrode and as a hydrogen barrier film. Although not shown, theBi-CMOS device 97 includes a CMOSFET 34 having the same structure as theCMOSFET 34 inFIG. 16A . As shown inFIGS. 18A and 18A , thealuminum electrode 47 a extends above the interface between abase region 48 and an insulatingfilm 46 ofFIG. 18A such that the interface is substantially completely covered by thealuminum electrode 47 a to prevent hydrogen atoms from traveling to the interface from apassivation film 57, which is located on thealuminum electrode 47 a although not shown inFIG. 18A . Therefore, thebipolar transistor 88 has relatively stable device characteristics. - Eleventh Embodiment
- As shown in
FIGS. 19A and 19B , aBi-CMOSFET semiconductor device 98 differs from theBi-CMOSFET semiconductor device 97 ofFIGS. 18A and 18B in that abipolar transistor 89 includes analuminum electrode 47 b as an emitter electrode and as a hydrogen barrier film. Although not shown, theBi-CMOS device 97 includes a CMOSFET 34 having the same structure as theCMOSFET 34 inFIG. 16A . As shown inFIGS. 19A and 19B , thealuminum electrode 47 b extends above the interface between abase region 48 and an insulatingfilm 46 ofFIG. 19A such that the interface is substantially completely covered by thealuminum electrode 47 b to prevent hydrogen atoms from traveling to the interface from apassivation film 57, which is located on thealuminum electrode 47 b although not shown inFIG. 18A . Therefore, thebipolar transistor 88 has relatively stable device characteristics in the same manner as theBi-CMOSFET semiconductor device 97 ofFIG. 18A . - Twelfth Embodiment
- As shown in
FIG. 20 , aBi-CMOSFET semiconductor device 99 differs from theBi-CMOSFET semiconductor device 83 ofFIG. 16A in that abipolar transistor 90 includes asilicon nitride film 91 as a hydrogen barrier film. Although not shown, theBi-CMOS device 97 includes a CMOSFET 34 having the same structure as theCMOSFET 34 inFIG. 16A . Thesilicon nitride film 91 is deposited to cover the substantially entirebipolar transistor 90 after agate oxide film 44 is formed. Then, an insulatingfilm 46,aluminum electrodes 47, and apassivation film 57, which is formed on thealuminum electrode 47 although not shown inFIG. 20 . Therefore, thebipolar transistor 20 has relatively stable device characteristics. - Thirteenth Embodiment
- As shown in FIGS. 21 to 23, each
application circuit circuit circuits - In each
circuit circuits - The
first application circuit 92 ofFIG. 24 is designed to provide an output current Iout in response to an input current Iin, and a current mirror circuit in the input stage of thefirst application circuit 92 includes the pair of bipolar transistors Tr1 a, Tr2 a, which have transistor characteristics identical with each other. The voltage Vce1 between the collector and the emitter of the transistor Tr1 a, the collector and the base of which are shorted, is equivalent to the forward bias voltage Vf between the base and the emitter of a bipolar transistor Tr3. Furthermore, the voltage Vce2 between the collector and the emitter of the transistor Tr2 a on the output side is equal to a balance between a supply voltage Vcc and the voltage Vf between the base and the emitter of the transistor Tr3. - Therefore, the voltages Vce1 and Vce2 are generally not equal to each other, and so are biasing conditions between the transistors Tr1 a, Tr2 a. When driven under such conditions, the shifts in device characteristics of the transistors Tr1 a, Tr2 a, which are used as a pair, becomes different from each other during operation and the performance parity between the transistors Tr1 a, Tr2 a to break down, if the
bipolar transistor 5 in the proposedBi-CMOSFET semiconductor device 1 ofFIG. 24 is used for the pair of transistors Tr1 a, Tr2 a. On the other hand, stable circuit operation can be maintained in thecircuit 92 ofFIG. 21 by using the bipolar transistors in the Bi-CMOS devices according to the first through twelfth embodiments for the pair of transistors Tr1 a, Tr2 a. - The
second application circuit 93 ofFIG. 25 is a band gap circuit, which is used for outputting a reference voltage of, for example, 1.3 V. In theapplication circuit 93, currents of two different magnitudes are respectively provided for transistors Tr1 b, Tr2 b in aband gap circuit 94 of thesecond application circuit 93. The voltage drop due to a resistance R3, which is connected to the emitter of the transistor Tr1 b and has an electric resistance of R3 ohms, leads to the following relationship between voltage Vbe1 and voltage Vbe2, which are respectively the voltage between the base and the emitter of the transistor Tr1 b and the voltage between the base and the emitter of the transistor Tr2 b:
Vbe2−Vbe1=R3×i, -
- where i is a current that flows through the resistance R3.
- Therefore, the transistors Tr1 b, Tr2 b, which are used in a pair, are driven under different conditions. Thus, stable circuit operation can be maintained in the
circuit 93 ofFIG. 22 by using the bipolar transistors in the Bi-CMOS devices according to the first through twelfth embodiments for the pair of transistors Tr1 b, Tr2 b. - The
third application circuit 95 ofFIG. 26 is also a band gap circuit, which is used for outputting a reference voltage Vref using a band gap circuit. In theapplication circuit 95, transistor Tr1 c, Tr2 c, which are used in a pair to make up the band gap circuit, operate under the following conditions, and a collector voltage and a base voltage of the transistor Tr2 c are inputted into input terminals to an op amp Op1:
Vbe1=Vce1=Vce2+R3×i2, and
i1/i2=R2/R3. - Therefore, the transistors Trlc, Tr2 c are driven under different conditions. Thus, stable circuit operation can be maintained in the
circuit 95 ofFIG. 23 by using the bipolar transistors in the Bi-CMOS devices according to the first through twelfth embodiments for the pair of transistors Tr1 c, Tr2 c. - Other Embodiments
- The present invention is not limited to the Bi-CMOS devices of the first through twelfth and can also apply to the following variations.
- Each method used in the Bi-CMOS devices of the first through twelfth of the embodiments can be used alone or in combinations. That is to say, the first group of methods used in the first through fifth embodiments, in which the high impurity concentration p-
type base region 50 is used, the second group of methods used in the sixth and the seventh embodiments, in which ultraviolet rays are exposed to the Bi-CMOS devices, and the third group of methods used in the eighth through the twelfth embodiments, in which the hydrogen barrier film is used, may be combined with each other in various arrangements. - Although the transistors are isolated from each other by the
trenches 38 and the insulatinglayer 33 in the Bi-CMOS devices of the first through twelfth embodiments, the transistors may be isolated by PN junctions. - The
polycrystalline silicon film 85, which is the hydrogen barrier film, is formed to surround theemitter region 49 in the Bi-CMOS device ofFIG. 16A . However, if theemitter region 49 is formed to be in contact with theadjacent LOCOS 39 at one side of theemitter region 49, the polycrystalline silicon film may surround theemitter region 49 on the remaining three sides. - Although only one of the
aluminum electrodes 47, which are thebase electrode 47 a and theemitter electrode 47 b, extends out in the Bi-CMOS devices ofFIGS. 18A and 19A , both thebase electrode 47 a and theemitter electrode 47 b may extend out.
Claims (41)
1. A method for manufacturing a semiconductor device, which includes a CMOSFET and a bipolar transistor, wherein the bipolar transistor is formed on a substrate using steps of forming a well region of the CMOSFET and pairs of regions of the CMOSFET, each pair of which includes a source region and a drain region, on the substrate, and wherein a high impurity concentration region is formed by introducing a first impurity of the same conductivity type as a base region of the bipolar transistor in a surface of the base region.
2. The method in claim 1 , wherein the base region is formed using the step of forming the well region, wherein an emitter region of the bipolar transistor is formed by introducing a second impurity at the step of forming one of the pairs of regions, wherein the high impurity concentration region is formed using the step of forming another one of the pairs of regions.
3. The method in claim 2 , wherein a self alignment mask pattern of the bipolar transistor is formed using a step of forming a gate electrode of the CMOSFET such that the self alignment mask pattern is located above a surface of the base region between the emitter region and the high impurity concentration region, and wherein the first and second impurities are introduced using the self alignment mask pattern as a mask material.
4. The method in claim 1 , wherein the base region is formed using the step of forming the well region, wherein an emitter region of the bipolar transistor is formed by introducing a second impurity, wherein an insulating film is formed on a surface of the bipolar transistor, wherein an emitter support area is formed using a step of forming a gate electrode of the CMOSFET such that the emitter support area is in electric contact with the emitter region and extends out of the emitter region on the insulating film by a predetermined distance, and wherein the first impurity is introduced using the emitter support area as a mask material.
5. The method in claim 1 , wherein an emitter region of the bipolar transistor is formed by introducing a second impurity, and wherein the high impurity concentration region and the emitter region are formed such that a distance between the high impurity concentration region and the emitter region is 2 μm or shorter.
6. The method in claim 5 , wherein the high impurity concentration region is formed such that the distance is 1 μm or longer.
7. The method in claim 1 , wherein the semiconductor device further includes a DCMOSFET, wherein the base region is formed using the step of forming the well region, wherein the high impurity concentration region is formed using a step of forming a region for channel of the DCMOSFET, and wherein an emitter region of the bipolar transistor is formed by introducing a second impurity in a surface of the high impurity concentration region at the step of forming one of the pairs of regions.
8. The method in claim 1 , wherein the high impurity concentration region is formed to surround an emitter region of the bipolar transistor.
9. The method in claim 1 , wherein the surface of the base region is exposed to ultraviolet rays to reduce the amount of charges existing at an interface between the base region and an insulating film, which is located on the surface of the base region.
10-12. (Cancelled)
13. A method for manufacturing a semiconductor device, which includes a CMOSFET and a bipolar transistor, wherein the bipolar transistor is formed on a substrate using steps of forming a well region of the CMOSFET and pairs of regions of the CMOSFET, each pair of which includes a source region and a drain region, on the substrate, wherein a base region of the bipolar transistor is formed using the step of forming the well region, wherein a high impurity concentration region is formed by introducing a first impurity of the same conductivity type as the base region in a surface of the base region using the step of forming one of the pairs of regions, wherein an emitter region of the bipolar transistor is formed by introducing a second impurity at the step of forming another one of the pairs of regions, and wherein the high impurity concentration region and the emitter region are formed such that a distance between the high impurity concentration region and the emitter region is 2 μm or shorter.
14. A method for manufacturing a semiconductor device, which includes a CMOSFET and a bipolar transistor, wherein the bipolar transistor is formed on a substrate using steps of forming a well region of the CMOSFET and pairs of regions of the CMOSFET, each pair of which includes a source region and a drain region, on the substrate, and wherein a surface of a base region of the bipolar transistor is exposed to ultraviolet rays to reduce the amount of charges existing at an interface between the base region and an insulating film, which is located on the surface of the base region.
15. The method in claim 14 , wherein the semiconductor device further includes an EPROM, and wherein a passivation film, which is transparent to ultraviolet rays, is formed on the CMOSFET, the bipolar transistor, and the EPROM before the step of exposing.
16-17. (Cancelled).
18. The method in claim 14 , wherein an SOI substrate is used for the substrate.
19. A method for manufacturing a semiconductor device, which includes a CMOSFET and a bipolar transistor, wherein the bipolar transistor is formed on a substrate using steps of forming a well region of the CMOSFET and pairs of regions of the CMOSFET, each pair of which includes a source region and a drain region, on the substrate, and wherein an insulating film is formed on a surface of a base region of the bipolar transistor, and wherein a hydrogen barrier film is formed on the insulating film to cover the surface of the base region.
20-21. (Cancelled)
22. The method in claim 19 , wherein the base region is formed using the step of forming the well region, wherein an emitter region of the bipolar transistor is formed by introducing a second impurity, wherein an emitter support area is formed as the hydrogen barrier film using a step of forming a gate electrode of the CMOSFET such that the emitter support area is in electric contact with the emitter region and extends out of the emitter region by a predetermined distance.
23. The method in claim 19 , wherein the hydrogen barrier film is formed using a portion of metal electrode of the bipolar transistor.
24. The method in claim 23 , wherein the metal electrode is a base electrode.
25. The method in claim 23 , wherein the metal electrode is an emitter electrode.
26. The method in claim 19 , wherein the hydrogen barrier film is formed from a silicon nitride film.
27. (Cancelled)
28. A semiconductor device comprising a CMOSFET and a bipolar transistor, wherein the CMOSFET and the bipolar transistor are located on the same substrate, wherein a high impurity concentration region, which includes a impurity of the same conductivity type as a base region of the bipolar transistor with higher concentration than the base region, is located in a surface of the base region.
29. The semiconductor device in claim 28 , wherein the high impurity concentration region has substantially the same impurity concentration as a pair of regions that includes a source region and a drain region of the CMOSFET.
30. The semiconductor device in claim 29 further comprising a self alignment mask pattern that is used to adjust the distance between an emitter region of the bipolar transistor and the high impurity concentration region to a predetermined distance in a manufacturing process of the semiconductor device.
31. The semiconductor device in claim 28 , wherein the bipolar transistor includes an insulating film, wherein the insulating film is located on a surface of the base region, wherein the emitter support area is in electric contact with an emitter region of the bipolar transistor and extends on the insulating film by a predetermined dimension, and wherein the emitter support area is used as a mask material for forming the high impurity concentration region in a manufacturing process of the semiconductor device.
32-33. (Cancelled)
34. The semiconductor device in claim 28 , wherein the semiconductor device further comprises a DMOSFET, and wherein the high impurity concentration region has substantially the same impurity concentration as a region for channel of the DCMOSFET.
35. The semiconductor device in claim 28 , wherein the high impurity concentration region is located to surround an emitter region of the bipolar transistor.
36. The semiconductor device in claim 28 , wherein a hydrogen barrier film is located on a surface of the base region with an insulating film in-between.
37. The method in claim 36 , wherein the hydrogen barrier film includes one film selected from the group that consists of a polycrystalline silicon film, an aluminum film, and a silicon nitride film.
38. The semiconductor device in claim 28 , wherein the substrate is an SOI substrate.
39. A semiconductor device comprising a CMOSFET and a bipolar transistor, wherein the CMOSFET and the bipolar transistor are located on the same substrate, wherein a hydrogen barrier film is located on a surface of the base region with an insulating film in-between.
40-41. (Cancelled)
42. The semiconductor in claim 39 , wherein the bipolar transistor includes an emitter support area, wherein the emitter support area is in electric contact with an emitter region of the bipolar transistor and extends on the insulating film by a predetermined dimension to function as the hydrogen barrier film.
43. The semiconductor in claim 39 , wherein the hydrogen barrier film is a portion of a metal electrode of the bipolar transistor.
44. The semiconductor device in claim 43 , wherein the metal electrode is a base electrode.
45. The semiconductor device of claim 43 , wherein the metal electrode is an emitter electrode.
46. The semiconductor device in claim 39 , wherein the hydrogen barrier film is a silicon nitride film.
47. (Cancelled)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US10/929,621 US20050023644A1 (en) | 2001-11-07 | 2004-08-31 | Stabilization in device characteristics of a bipolar transistor that is included in a semiconductor device with a CMOSFET |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2001341906A JP4003438B2 (en) | 2001-11-07 | 2001-11-07 | Semiconductor device manufacturing method and semiconductor device |
JP2001-341906 | 2001-11-07 | ||
US10/289,220 US6803634B2 (en) | 2001-11-07 | 2002-11-07 | Stabilization in device characteristics of a bipolar transistor that is included in a semiconductor device with a CMOSFET |
US10/929,621 US20050023644A1 (en) | 2001-11-07 | 2004-08-31 | Stabilization in device characteristics of a bipolar transistor that is included in a semiconductor device with a CMOSFET |
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US10/929,621 Abandoned US20050023644A1 (en) | 2001-11-07 | 2004-08-31 | Stabilization in device characteristics of a bipolar transistor that is included in a semiconductor device with a CMOSFET |
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JP5755939B2 (en) * | 2011-05-24 | 2015-07-29 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Semiconductor device and manufacturing method thereof |
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US9466687B2 (en) | 2010-10-20 | 2016-10-11 | Freescale Semiconductor, Inc. | Methods for producing bipolar transistors with improved stability |
Also Published As
Publication number | Publication date |
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JP4003438B2 (en) | 2007-11-07 |
US20030085414A1 (en) | 2003-05-08 |
US6803634B2 (en) | 2004-10-12 |
JP2003142613A (en) | 2003-05-16 |
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