US 20050040811 A1
In order to form a modular interface between a DUT board, which is housing devices under tests (DUT), to cables connected to a test head, a board spacer is provided that has an array of connectors. Each cable is connected to a respective connector, and the DUT board contains a corresponding array of connection points which are less than or equal to the number of connectors in the arrays on the board spacer. In this way, a common board spacer can be used to connect the cables to DUT boards housing different types of DUTs since the location of the connection points on the board spacer is known and kept constant. This interface allows a high speed and high fidelity connection between the test head and the devices on the DUTs for frequencies in excess of 50 MHz.
1. An interface to perform high-parallelism testing of memory devices, comprising:
a first board holding one of the memory devices and having a receptacle connected to the one memory device; and
a plug connected to respective cables and to the receptacle to create a communication pathway,
wherein combinations of said first boards and said plugs allow high-parallelism testing of the memory devices.
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9. A method of connecting a memory device on a DUT board to cables for high-parallelism testing of memory devices, comprising:
unplugging first DUT boards from plugs, where each first DUT board has a first receptacle that is connected to a first memory device and each plug is connected to respective cables; and
plugging second DUT boards into the plugs, where each second DUT board has a second receptacle that is connected to a second memory device so as to form communication pathways between the cables and the second memory device,
wherein the combined second DUT boards and plugs allows high-parallelism testing of the second memory devices.
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This application is a divisional of U.S. patent application Ser. No. 10/326,392, filed Dec. 23, 2002 in the United States Patent and Trademark Office, which is a divisional of U.S. patent application Ser. No. 09/808,009, filed Mar. 15, 2001 in the United States Patent and Trademark Office, the disclosures of which is incorporated herein by reference.
1. Field of the Invention
This invention relates generally to automatic test equipment used to test integrated circuit elements, and more particularly to interface hardware used in automatic test equipment to connect devices under test to a test head in order to perform the testing.
2. Description of the Related Art
Automatic test equipment (i.e., a tester) is generally used to test semiconductor devices and integrated circuit elements, such as memory or logic for manufacturing defects. A general representation of a tester is shown in
As shown in
For a conventional tester 1, when a new type of DUT 60 is to be tested, the new DUT 60 is brought to the tester 1 via handler 5 and connected to a test socket (not shown), completing the electrical connection between the test head 20 and the new DUT 60. The test is then performed. After completion of the test, the DUT 60 is then removed from the test socket via handler 5, and a new DUT 60 of the same type is installed into the test socket using the handler 5.
If a new type of DUT 60 is to be tested, the old DUT board 80 must be replaced and a new DUT board 80 inserted in its place. The new DUT board 80 will have different connection needs reflecting the new type of DUT 60. As such, either a new interface assembly must be used, or the cables 70 must be resoldered at different solder points 82. In either case, the cables 70 are custom fitted to different DUT boards 80 for each new type of DUT 60 to be tested. Further, where the cables 70 are resoldered, each change in DUT 60 type requires that the interface assembly, including the board spacer 40, be partially or wholly disassembled, the cables 70 be soldered onto respective solder points 82 of the new DUT board 80, and the interface be reassembled. On the other hand, where the entire interface assembly is replaced, large numbers of interface assemblies must be stored for each type of DUT 60 to be tested.
This use of solder connections is problematic since it is time consuming to attach the cables 70 to the solder points 82 of the DUT boards 80. This problem is exacerbated as both the density and/or number of DUTs 60 increases. For instance, modern testers can accommodate up to 128 DUTs 60 per test head 20, with changes in the types of DUTs 60 being made multiple times per week, or even per day. As such, the requirement that the interface be disassembled and reassembled, and the custom soldering to connect the cables 70 to the different types of DUT boards 80 can require significant time and expense to perform for each change in the type of DUT 60 to be tested, and also significantly increases the amount of time required to test the DUT 60s.
As shown in
However, this solution also is problematic as the number and density of DUTs 60 being tested increases. As the density of DUTs 60 being tested increases, smaller and smaller pogos 100 must be used in order to fit into the space provided under the DUT board 80. As the pogos 100 get smaller, they become more delicate and difficult to work with. Further, as pogos 100 get smaller, their stroke (i.e., the distance that the tip of the pin 100 can travel vertically in order to bias against pad 90) decreases, which means that the DUT board 80 and the pogo boards 110 must be made highly planar to ensure a connection at all pads 90. This increases the production cost for the pogo boards 110 and the DUT boards 80. In addition, pogos 100 are themselves expensive to use. As such, pogos 100 do not present an ideal alternative to solder connection as the density and/or number of DUTs 60 increases.
Where the DUT 60 is a logic element 65, it is known to perform lower parallelism testing using plugs 160 as shown in
However, this configuration is known for use in lower-parallelism testing of logic elements 65, and requires the use of eight or more plugs 160 per logic board 150. Such a configuration is unsuitable for high-density, high-parallelism testing of DUTs, especially where the DUT is a smaller device such as a memory device. In order to test these devices, the DUT boards are smaller, which prevents the use of numerous plugs 160. Further, the handlers 5 that move the memory devices, such as the Advantest M65XX and M67XX series handlers, use spacing frames having a pitch that does not allow the use of a large number of plugs 160 in order to test these devices. Thus, for high-parallelism testing of memory devices (i.e., simultaneous testing of 32 or more devices), conventional plug arrangements were not possible.
It is an object of the invention to provide a connection system between devices under test and a test head that provides a secure modular connection to the devices under test for high data rates without causing degradation in signal quality.
It is a further object of the invention to provide a high density, scalable connection system between devices under test and a test head.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Accordingly, to achieve these and other objects, an embodiment of the present invention uses an interface between a device under test (DUT) and cables, including a first board having an array of first connectors, each first connector connected to a respective cable, and a second board holding the DUT and having second connectors, each second connector being connected to the DUT and to a respective first connector, and where the number of second connectors is less than the number of first connectors.
According to another embodiment of the invention, the first connectors and second connectors comprise pairs of header connectors and shielded-controlled impedance connectors.
According to a further embodiment of the invention, the first connectors and the second connectors comprise pairs of pads allowing a board-to-board connection between the first board and the second board.
According to another embodiment of the present invention, an interface to perform high-parallelism testing of memory devices comprises a first board holding one of the memory devices and having a receptacle connected to the one memory device, and a plug connected to respective cables and to the receptacle to create a communication pathway, wherein combinations of the first boards and the plugs allow high-parallelism testing of the memory devices.
According to a still further embodiment of the present invention, a method of connecting a DUT on a DUT board to cables for testing comprises unplugging a first DUT board having a first number of connectors from respective cables held in an array on a board spacer, and plugging a second DUT board having a second number of connectors different from the first number of connectors into the cables.
According to yet another embodiment of the present invention, a method of connecting a DUT on a DUT board to cables for testing comprises removing a first DUT board having first pads connected to a first DUT from a board spacer having board pads connected to the cables, where respective pairs of first pads and board pads formed a board-to-board connection creating first communication pathways for signals between the cables and the first DUT, and placing a second DUT board having second pads connected to a second DUT onto the board spacer to form a board-to-board connection creating a second communication pathways for signals between the cables and the second DUT.
According to still another embodiment of the present invention, a method of connecting a memory device on a DUT board to cables for high-parallelism testing of memory devices that comprises unplugging a first DUT board having a first receptacle from a plug connected to respective cables, and plugging a second DUT board having a second receptacle into the plug to form a communication pathway between the memory device and the cables, wherein combinations of the second DUT boards and the plugs allow high-parallelism testing of the memory devices.
These and other objects and advantages of the invention will become apparent and more readily appreciated from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings of which:
Reference will now be made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.
For an embodiment of the present invention shown in
In order to form a communication pathway between SCI connectors 220 and respective DUTs 60, sets of headers 210 are arrayed on DUT board 280. Each header 210 contains header connectors 215, which are pairs of pins, each pair having a signal pin and a ground pin. A connector 220 from a respective cable 70 connects to one header connector 215. As shown in
Generally, the board spacer 230 has fully populated arrays 240, meaning that each array hole 245 in the array 240 has a respective SCI connector 220. In contrast, as shown in
As shown, the SCI connector 220 is a 2 mm connector having a signal and a ground line. Such 2 mm connectors 220 can be WL Gore 2 mm EYEOPENER cable connectors, or SCI connectors from 3M, which are 1×2 2 mm controlled impedance connectors. Similarly, the header 210 is a surface mount technology 2 mm header, which allows 60-70 header connectors 215 to be used on each DUT board 280.
Of course, it is understood that it is also possible to use connectors 220 having other distances between signal and ground lines for the same connector 220, and/or between signal lines and ground lines of adjacent connectors 220 (i.e., other pitches). For instance, it is possible to use connectors 220 which have a 1.27 mm pitch or a 0.1″ pitch.
Further, while the shown header 210 is surface mounted to the DUT board 280, it is understood that the through hole connection can be used. It is further understood, but not shown, that the headers 210 and SCI connectors 220 could be reversed such that the header 210 is located in the array 240 and the SCI connector 220 is surface mounted to the DUT board 280. However configured, the interface according to the preferred embodiments of the present invention is able to support high speed and high fidelity signals at frequencies above 50 MHz.
Another embodiment of the present invention is shown in
Generally, the plug 320 is attached to the receptacle 310 using screws, pull pins, a series of cams, or similar attachment mechanisms. However, it is also possible, but not shown, to construct a board spacer to support and hold the plugs 320 in an array.
As shown in
The PCB 323 includes internal wires 326 that form communication pathways to respective cables 70. The cables 70 are connected to the respective wires 326 by conventional methods such as soldering. The cables 70 are supported using strain relief member 328, which is attached to housing 324 that also protects the assembly.
The receptacle 310 also has internal connection points (not shown), where the internal connection points are connected to receptacle wires 315 leading to the DUT 60. The internal connection points and associated wires 315 may be equal to or less than the number of wires 326/cables 70 for a respective plug 320, depending on how many of the cables 70 are required to test a specific type of DUT 60. In this way, the same plugs 320 can be used for various DUT boards 380 holding various types of DUTs 60, with the difference in connections being provided by selectively connecting to the wires 326 in the respective plugs 320.
Further, using this configuration, the number of plugs 320 can be reduced such that one or two plugs 320 are used per DUT board 380. Such a result is especially desirable where the DUT 60 is a memory device, and where space limitations have heretofore prevented the use of plug-receptacle connections. For instance, such an interface would be useful with a M65XX and M67XX Advantest handler which are capable of delivering thirty-two (32) devices per space frame (sixty-four (64) devices AD style), but which has pitch limitations preventing the use of conventional plug configurations.
For still another embodiment of the present invention as shown in
By way of example, in order to test a different type of DUT 60 using the interface according to the embodiment of the present invention shown in
As such, according to the preferred embodiments of the present invention, a common board spacer or connection scheme can be used which allows DUT boards housing different types of DUTs to be interchanged in a tester without having to rewire and reconnect cables to respective DUTs on the DUT board. Instead, they allow the use of predetermined connection points arrayed on a board spacer or in a plug to form the connection to the cables.
Although a few preferred embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in this embodiment without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.