US 20050048696 A1
A microbeam interconnection method is provided to connect integrated circuit bond pads to substrate contacts. Conductive leads (microbeams) are releasably formed, by a process such as electroplating or vacuum deposition, over a release layer deposited on a ceramic, glass or similar carrier. The microbeam material adheres only very weakly to the release layer. After the inner ends of the microbeams have been bonded to IC bond pads, such as by flip chip bump bonding, and the integrated circuit has been fully tested, the IC is lifted away from the carrier, causing the microbeams to peel away from the release layer. After straightening the microbeams against a flat surface, the outer ends of the microbeams may then be bonded to contacts on an MCM or other substrate. The method permits full electrical testing at speed and high speed bonding. The method significantly reduces mechanical stresses in interconnect bonds and thereby improves integrated circuit reliability.
36. A method of forming interconnects between integrated circuit bond pads and microbeam conductors comprising:
providing a carrier having a release layer located thereon;
bonding at least one conductive microbeam to the release layer;
bonding the conductive microbeam to a bond pad of an integrated circuit; and
at least partially etching away the release layer to thereby aid in releasing the microbeam from the carrier.
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48. A method of forming interconnects between integrated circuit bond pads and substrate contacts comprising:
providing a carrier having a plurality of conductors located on a first region of the carrier and a release layer located on a second region of the carrier; and
bonding a plurality of conductive microbeams to the release layer, wherein each of the microbeams is in electrical communication with at least one of the conductors.
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The present invention relates to interconnections between integrated circuits and substrates and, more particularly, to a microbeam assembly method which allows for electrical testing of an integrated circuit at speed and subsequent interconnection of the integrated circuit to a substrate.
An essential step in the fabrication of microelectronic hardware is the step of providing electrical connections from the electronic devices to the interconnection board or substrate. As microelectronic devices such as integrated circuits become more highly integrated and more complex there is also great need for a method to fully functional test the device at speed before assembly into the circuit. Otherwise, large amounts of time are required to locate failed devices on a complex substrate containing several high lead count devices. For physically large devices the interconnection method must also be able to compensate for significant thermal expansion mismatches between the integrated circuit die and the interconnection substrate or board material. A number of unique approaches have been developed to solve some of these problems, such as TAB (tape automated bonding), beam lead bonding, and flipchip bonding.
As a point of reference, the most common approach to the interconnection of semiconductor devices involves mounting the device in a package and bonding fine wire (usually 1 mil gold or aluminum wire) from metallized pads on the device to the interior leads of the package using ultrasonic or thermocompression bonding methods. The package leads extend through the package wall and are subsequently connected to other circuitry, such as by a soldering process. In a variation on this approach, multiple copper leads (which are typically gold plated) are supplied on a polyimide tape so that the lead bonding and electrical testing processes can be highly automated. This automated lead bonding scheme is generally referred to by those skilled in the art as TAB.
Several techniques have been developed for making a mechanically-sound electrical contact between the chip bond pad and an electrical lead in lead bonding applications. In one technique, the contacts are formed by wire bonding. With wire bonding, thin wires are attached via thermocompression or thermosonic bonding to a lead and a respective bond pad on the chip.
Another standard technique forms the electrical contacts through solder bumps formed on the chip bond pads. The leads are first positioned over the solder bumps on the chip. A thermode is heated to a temperature which is above the melting point of the solder and brought into contact with the leads. Sufficient force is used to insure that the leads intimately contact the solder bumps during solder reflow.
TAB and other lead bonding approaches generally produce leads that extend beyond the chip footprint (such as by 40 mils), which may be a problem in applications requiring tight spacing. In addition, the high bonding forces required to bond a copper TAB lead may damage the chip or substrate and the removal of defective TAB bonded chips from a substrate is often difficult to accomplish without damaging the substrate. Moreover, TAB leads may require stress relief to alleviate thermal expansion mismatches with the chip and substrate.
Another popular interconnect technology is the so-called “flip chip” technology first developed by IBM.
Yet another known interconnect technology is the beam lead process first developed by IBM. Beam lead technology is a semiconductor device fabrication and interconnection process whereby devices are fabricated on the semiconductor wafer with extra space (typically 8 to 12 mils) between devices. A set of interdigitated beam leads is then plated up to connect the active elements with gold conductors that can later be used to interconnect the devices to the next level circuitry. The individual devices are separated by etching the semiconductor from the back side of the wafer in the area above the plated beams so that the separated devices have individual beams extending beyond the device perimeter. The short, high conductive leads provided by the beam lead process are ideal for small high-speed diodes and transistors for microwave device applications, but the process is not useful for large lead count devices, does not permit functional testing at speed, and wastes significant wafer area to accommodate the beams.
Notwithstanding the variety of conventional lead bonding techniques available in the art, the electronics industry therefore still desires a more reliable lead bonding technology which does not require solder flux and which permits close spacing of the resulting integrated circuits. This desire for more reliable lead bonding technology seems to be becoming more important as the space available for lead bonding shrinks and as reliability requirements for resulting integrated circuits increase. Moreover, as devices become more complex and include more leads, automated testing at speed becomes more important to ensure that only known-good devices are processed further.
According to one advantageous embodiment, the present invention provides a method of connecting an integrated circuit to a substrate comprising the steps of attaching the integrated circuit to conductive microbeams releasably formed on a carrier, lifting the integrated circuit from the carrier so as to separate the microbeams from the carrier, mounting the integrated circuit to a substrate, and connecting microbeams to respective substrate contacts. By utilizing microbeams according to the present invention, the integrated circuit can therefore be reliably connected to respective substrate contacts without requiring solder flux. In addition, the connection method of the present invention permits close spacing of the resulting integrated circuit by reducing the space required for lead bonding. Thus, the connection method of the present invention addresses each of the deficiencies of the prior art.
In an alternate advantageous embodiment of the present invention, a method is provided of forming integrated circuit bond pad leads comprising the steps of releasably forming conductive microbeams on a carrier, bonding integrated circuit bond pads to respective microbeams, and lifting the integrated circuit from the carrier so as to separate the microbeams from the carrier while the microbeams remain bonded to respective bond pads. The integrated circuit, complete with the microbeams bonded to respective bond pads, can then be mounted to a substrate or the like in order to appropriately connect the integrated circuit bond pad leads with respective substrate contacts via the microbeams.
According to another aspect of the present invention, a microbeam assembly is provided that is adapted to form interconnects between integrated circuit bond pads and substrate contacts. According to one advantageous embodiment of the invention, the microbeam assembly includes a carrier and a plurality of conductive microbeams releasably bonded to the carrier, wherein the conductive microbeams are sized and spaced to mate with the bond pads of an integrated circuit.
The method and apparatus of the present invention provide an integrated circuit packaging system that reduces interconnect bond mechanical stress and thereby improves reliability without requiring solder flux. As noted above, the integrated circuit packaging system of the present invention also permits close spacing among resulting integrated circuits by reducing the spacing required for lead bonding in comparison to conventional lead bonding techniques.
The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth here; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
One advantageous embodiment of the microbeam assembly according to the present invention is depicted in
While the release layer 50 may be formed of tungsten, the release layer 50 may also be formed of a very thin oxidized metal layer or of a thin layer of polyimide or parylene. In addition, other metallic or non-metallic materials, such as spin-on oxide or spin-on glass coatings, may be used to form the release layer 50 so long as the release layer will adhere to the microbeams 52 very weakly without contaminating the underside of the microbeams 52 (so as to thereby avoid bonding difficulties that may result from microbeam surface contamination).
The polyimide material used to form the release layer 50 may be a liquid organic polyimide such as Pyralin PI-2570 from Dupont. The polyimide may be applied to the carrier 48 by a spin-on process as is commonly used for photoresist coatings in the semiconductor industry. Alternatively, the polyimide may be applied by such drop dispensing, spraying, or roller coating processes as are known in the art.
Alternatively, the microbeams 52 may be formed on a lift-off polyimide material soluble in a release solvent. In this approach, the release layer 50 is dissolved after formation of the microbeams 52, thereby releasing the microbeams. Alternatively, the polyimide release layer may be removed from under the microbeams 52 by plasma etching of the polyimide with oxygen or with a reactive gas such as CF4 as is known in the art.
The carrier 48, according to one embodiment of the present invention, is a substantially rigid carrier, such as a glass or ceramic carrier, upon which the fan-out conductors 46, release layer 50, and microbeams 52 may be formed.
After the release layer 50 has been formed on the carrier 48, the microbeams 52 are formed on top of the release layer, such as by electroplating. The conductive microbeams 52 are preferably sized and spaced to mate with the bond pads of an integrated circuit. The microbeams may be formed of gold, copper, alloys thereof, or other suitable conductive materials or alloys as is known in the art. For example, in one preferred embodiment the microbeams 52 comprise one-half ounce copper conductors. In one advantageous embodiment, the microbeams are between 0.4 mils and 0.7 mils thick, although the microbeams can have other thicknesses without departing from the spirit and scope of the present invention.
As will be discussed below, bumps, such as gold or solder bumps, and solder dams or other features can be formed on the microbeams or the devices in wafer form as needed. These features may be chosen for the particular bonding system employed for interconnection between the integrated circuit, the microbeams, and the substrate to which the integrated circuit will eventually be mounted and connected. These features may be formed by any feature formation processes as are known in the art. A variety of advantageous configurations of the IC bond pad, the microbeam, and the structure of the bond between the two are discussed below.
In order to fabricate a microbeam assembly according to one embodiment, a mask or other artwork is prepared so that fan-out conductors 46 can be formed on the carrier to deliver test signals to and from the microbeams 52 in a fanned out configuration to and from test points on the perimeter of the carrier. All of the fan-out conductors 46 are preferably shorted together at the outer edge of the carrier 48, beyond the test pads, so that the fan-out conductors 46 can be simultaneously electroplated as is known in the art. Subsequent carrier sawing operations will separate those portions of the fan-out conductors that are shorted together, thereby electrically isolating all of the fan-out conductors 46 for subsequent integrated circuit electrical testing.
Before or after formation of the fan-out conductors 46, a release layer 50 is deposited around the fan-out conductors on the remainder of the carrier. A second mask or other artwork is then prepared to allow selective electroplating of microbeams 52 on top of the release layer 50. The microbeams 52 are preferably 2 to 4 mils wide and preferably extend beyond the eventual device perimeter by 12 to 18 mils. The outer end of each microbeam preferably extends to the outer edge of the release layer. As such, each microbeam makes electrical contact with a respective fan-out conductor.
The next processing step is illustrated in
The next step in the process is depicted by
As the integrated circuit 30 continues to be separated from the carrier 48, the microbeam 52 is fully released from the release layer 50 and the attachment to the fan-out conductors 46 at the end of the microbeams is severed, as is shown in
As illustrated in
A plan view of a carrier according to the present invention is illustrated in
In any event, the method and apparatus of the present invention provides an integrated circuit assembly system that allows for full electrical testing at speed and high throughput bonding that reduces interconnect bond mechanical stress and thereby improves reliability without requiring solder flux. The integrated circuit packaging system of the present invention also permits close spacing among resulting integrated circuits by reducing the spacing required for lead bonding in comparison to conventional lead bonding techniques.
Many modifications and other embodiments of the invention will come to mind to one skilled in the art to which this invention pertains having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.