US 20050054177 A1
A trench-gated MOSFET includes adjacent mesas formed on opposite sides of a trench. A body region in the first mesa extends downward below the level of the trenches and laterally across the bottom of the trenches. The body region in the second mesa extends part of the way down the mesa, leaving a portion of the drain abutting the trench. The body region in the second mesa includes a channel region adjacent a wall of the trench. The area where the drain abuts the trench is thus relatively restricted and the drain-gate capacitance of the device is reduced. Moreover, the drain-gate capacitance is made independent of the depth and width of the trenches, allowing greater freedom in the design of the MOSFET.
1. A method of fabricating a MOSFET comprising:
providing a semiconductor chip doped with impurity of a first conductivity type;
forming a first mask over the chip, the mask having openings which define the locations of first, second and third trenches, respectively;
etching the chip through the openings in the first mask to form the first, second and third trenches, thereby forming a first mesa between the first and second trenches and a second mesa between the second and third trenches;
forming an insulating layer on the walls of the trenches;
introducing a conductive gate material into the trenches;
forming a second mask covering the first mesa but having an opening over the second mesa;
introducing a first dopant of the first conductivity type through the opening in the second mask into the second mesa;
introducing a second dopant through the opening in the second mask into the second mesa, the second dopant being of a second conductivity type opposite to the first conductivity type and being introduced at a first energy level;
removing the second mask;
forming a third mask covering the second mesa but having an opening over the first mesa;
introducing a third dopant through the opening in the third mask into the first mesa, the third dopant being of the second conductivity type and being introduced with at a second energy level, the second energy level being greater than the first energy level; and
subjecting the chip to heat such that and the first, second and third dopants diffuse, the third dopant diffusing under the second trench, a junction between the first and second dopants forming a body-drain junction of the MOSFET.
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forming a fourth mask having an opening over the first mesa;
implanting a fourth dopant of the first conductivity type at a third energy level through the opening in the fourth mask to form a first source region in the first mesa; and
forming a fifth mask having an opening over the second mesa; and
implanting a fifth dopant of the first conductivity type at a fourth energy level through the opening in the fifth mask to form a second source region in the second mesa, the third energy level being different from the fourth energy level.
12. A trench MOSFET comprising:
a semiconductor chip doped with impurity of a first conductivity type, the chip having first, second and third trenches formed at a surface of the chip, the first and second trenches defining a first mesa, the second and third trenches defining a second mesa;
a first source region of the first conductivity type in the first mesa, the first source region being adjacent the surface of the chip;
a second body region of a second conductivity type opposite to the first conductivity type in the first mesa, the second body region forming a first junction with the first source region, the second body region extending below the first and second trenches such that the second body region is adjacent the bottoms of the first and second trenches;
a third source region of the first conductivity type in the second mesa, the third source region being adjacent the surface of the chip;
a fourth body region of the second conductivity type in the second mesa, the fourth body region forming a second junction with the third source region, the fourth body region comprising a first channel region adjacent a wall of the second trench; and
a fifth drain region of the first conductivity type in the second mesa, the fifth drain region forming a third junction with the fourth body region.
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This invention relates to metal-oxide-silicon field-effect transistors (MOSFETs) and in particular to MOSFETs in which the gate electrode is located in a trench.
Trench-gated MOSFETs have achieved wide acceptance because of their superior on-resistance characteristics. Because the current flow is primarily in a vertical direction, through a channel located adjacent a side wall of the trench, it is possible to obtain a higher cell packing density than is the case with MOSFETs having a significant horizontal current flow. This allows a greater flow of current per unit of area of the semiconductor chip. Thus the on-resistance characteristics of trench-gated MOSFETs are generally superior to those of, for example, planar double-diffused MOSFETs.
One problem, however, that has occurred with trench MOSFETs relates to the capacitance that exists between the gate and the drain. This problem is illustrated in
The presence of a sizeable gate-drain capacitance limits the speed at which MOSFET 10 can be operated. This effect has become more problematical as the device size has decreased and the speed (frequency) has become greater.
One possible solution to this problem is illustrated in
Thus a definite need exists for a technique for reducing the gate-drain capacitance of a MOSFET without sacrificing on-resistance.
A trench MOSFET according to this invention includes a semiconductors chip and number of gate trenches formed in the chip which define intervening mesas. One of the mesas includes a body region and a source region. The body region includes a channel region adjacent a wall of the trench. A second mesa, located on an opposite side of the trench from the first mesa, includes a source region and a body region which extends downward below the trenches and laterally underneath the trenches. A drain region of the MOSFET borders the trench only in a region of the first mesa below the body region. Thus the drain-gate capacitance is greatly reduced and is rendered independent of the depth and width of the trenches.
The invention also includes methods of fabricating such a MOSFET. One illustrative method includes implanting a body dopant into the first mesa at a relatively low energy and implanting the body dopant into the second mesa at a relatively high energy such that the body dopant extends to a deeper level in the second mesa. The chip is annealed to drive in the body dopant, and the body dopant in the second mesa extends downward to the point where it reaches a level below the trenches and spreads laterally under the trenches. In one embodiment the body dopant in the second mesa extends across the entire bottom of the trenches and in effect “wraps around” the lower corners of the trenches.
There are numerous other methods that can be used to fabricate a MOSFET in accordance with this invention.
Adjacent the top surface 110 are N+ source regions 120 in mesa 112 and N+ source regions 122 in mesa 114. Forming junctions with N+ source regions 122 is a P+ body region 124 which in turn forms a junction with an N+ drain region 126 in mesa 114. Drain region 126 is in contact with the N− background doping of chip 102, which also forms a part of the drain of MOSFET 100. Within P+ body region 124 are channel regions 128 and 130, which adjoin the walls of trenches 106 and 108, respectively, and which can be inverted by the potential of polysilicon 116 to allow a current to flow between N+ source regions 122 and N+ drain region 126 through channel regions 128 and 130.
A metal layer 129 is formed on top surface 110 to make ohmic contact with N+ source regions 122. A P+ body contact region 125 establishes ohmic contact between metal layer 129 and P+ body region 124. A layer 127 of borophosphosilicate glass (BPSG) is formed over trenches 104, 106 and 108 to isolate the polysilicon 116 gate material from metal layer 129.
In mesa 112, a P+ body region 132 forms junctions with N+ source regions 120. Unlike P+ body region 124, P+ body region 132 extends downward from the junctions with N+ source regions 120 and to a region below the trenches 104 and 106. In this embodiment, P+ body region 132 forms a junction with N+ drain region 126 in mesa 114. Trench 106 has lower corners 134 and 136 at the intersection of the walls and bottom of trench 106 and P+ body region 132 “wraps around” corners 134 and 136. Like mesa 114, mesa 112 contains a P+ body contact region 131, which provides an ohmic contact between P+ body region 132 and metal layer 129.
When MOSFET 100 is in operation, a current flows in mesa 114 between N+ source regions 122 and N+ drain region 126 through channel regions 128 and 130, depending on the voltage applied to the polysilicon gate electrodes. In mesa 112, a current flows in a path that extends downward from N+ source regions 120, around the bottoms of trenches 104 and 106 to N+ drain regions 126. The current flows in MOSFET 100 are shown in
Insofar as trenches 106 and 108 are concerned, the drain-gate capacitance of MOSFET 100 arises entirely from the area where N+ drain region 126 abuts trenches 106 and 108. As will be evident, this is a much smaller area than the area designated 26 in
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The resulting device is the MOSFET 100 shown in
MOSFET 250, shown in
The fabrication of yet another embodiment is shown in
Referring again to MOSFET 250 shown in
It will be understood that the length of the channels can be adjusted in a similar manner in embodiments such as the one shown in
While specific embodiments of this invention have been described above, it will be apparent to those of skill in the art that numerous other embodiments may be constructed in accordance with the broad principles of this invention.