US 20050062630 A1 Abstract A tree-structured dynamic encoder generates an N-bit encoder output word in response to each encoder input word of a sequence of encoder input words, such that the number of encoder output word bits of value 1 equals a value of the encoder input word and such that positions bits of value 1 within the N-bit encoder output word for each give value of encoder word varies with time. Some or all of the switching blocks produce more than two block output words in response to each block input word. The dynamic encoder includes a tree of switching blocks, each dynamically encoding a block input word into more than one block output words, each having fewer bits than the block input word. A sum of values of the output words of each switching block always equals a value of that block's input word. A switching block of the highest layer of the tree receives each successive encoder input word as its block input word, and each switching block of each layer of the tree other than a lowest layer supplies each of its at least two block output words as a block input word to a separate switching block of a next lower layer of the tree. Each switching block of the lowest layer of the tree generates single-bit block output words, each forming a separate bit of the N-bit encoder output word.
Claims(33) 1. A dynamic encoder for generating an n-bit encoder output word in response to each encoder input word of a sequence of encoder input words, where each encoder input word may represent any of N+1 different levels, where N is an integer greater than 4, the dynamic encoder comprising:
a plurality of switching blocks organized into a tree comprising at least a highest layer and a lowest layer of switching blocks,
wherein each switching block receives a block input word and converts it into R block output words, each of the R block output words having fewer bits than the block input word, such that a sum of values of the R block output words equals a value of the block input word, and such that when the value of the block input word is other than a multiple of R, a value of each one of its R block output words is other than solely a function of the value of the block input word,
wherein the highest layer of the tree includes a switching block receiving each successive encoder input word of the sequence as its block input word,
wherein each switching block of each layer of the tree other than the lowest layer supplies each of its R block output words as a block input word to a separate switching block of a next lower layer of the tree,
wherein each block output word of each switching block of the lowest layer of the tree consists of a single bit and forms a separate bit of the N-bit encoder output word,
wherein for at least one of the plurality of switching blocks R>2.
2. The dynamic encoder in accordance with 3. The dynamic encoder in accordance with 4. The dynamic encoder in accordance with 5. The dynamic encoder in accordance with 6. The dynamic encoder in accordance with 7. The dynamic encoder in accordance with claim
wherein N is a power of two other than a power of four, and wherein for every switching block of every layer of the tree other than the highest layer of the tree R=4. 8. The dynamic encoder in accordance with a scrambling encoder for generating R 2′ scrambling encoder output bits in response to r least significant bits of the at least one switching block's block input word, wherein r>0, wherein a sum of values of scrambling encoder output bits is equal to a value represented by the r least significant bits of the at least one switching block's block input word; and R first summers, each corresponding to a separate one of the scrambling encoder output bits, each for generating a separate one of the at least one switching block's block R block output words as a sum of values of its corresponding scrambling encoder output bit and a 2 k+1−r moat significant bits of the at least one switching block's block input word. 9. The dynamic encoder in accordance with a first circuit for producing data d[n]=MOD(z[n],R); a second circuit for producing data q[n]=FLOOR(z[n]/R); a scrambling encoder for generating R scrambling encoder output bits in response to data d[n], wherein a sum of values of scrambling encoder output bits is equal to a value represented by d[n]; and R first summers, each corresponding to a separate one of the scrambling encoder output bits, each for generating a separate one of the at least one switching block's block R block output words as a sum of values of its corresponding scrambling encoder output bit and q[n]. 10. The dynamic encoder in accordance with 11. The dynamic encoder in accordance with 12. The dynamic encoder in accordance with a ranking circuit for monitoring the scrambling encoder output bits and for generating a plurality of ranking circuit output words as functions of past values of the scrambling encoder output bits, wherein each ranking circuit output word corresponds to a separate scrambling encoder output bit and wherein all ranking circuit output words have different values; and a plurality of comparison circuits, each corresponding to a separate one of the ranking data words, each for generating a corresponding one of the scrambling encoder output bit of a value determined as a result of a comparison between its corresponding one of the ranking data words and a value of the r least significant bits of the at least one switching block's input data word. 13. The dynamic encoder in accordance with a plurality of second summers for generating a plurality of summer output words, each second summer corresponding to a separate one of the scrambling encoder output bits other than a first scrambling encoder output bit and generating a summer output word representing a difference in values of its corresponding encoder output bit and the first scrambling encoder output bit, a plurality of digital filters for separately filtering the separate summer output words to produce a plurality of filter output words; and at least one comparator for generating the ranking circuit output words as functions of filter output words. 14. The dynamic encoder in accordance with 15. The dynamic encoder in accordance with 16. A method for generating an N-bit encoder output word in response to each encoder input word of a sequence of encoder input words, wherein each encoder input word may represent any one of N+1 levels, where N is an integer greater than 4,
a. converting each encoder input word into a set of M generated words, each consisting of fewer bits than the encoder input word, wherein a sum of values of the M generated words equals a value of the encoder input word, and wherein M>1; and b. converting each previously generated word into a separate set of R generated words each consisting of fewer bits than the previously generated word, wherein combined values of the R generated words equals a value of the previously generated word, wherein values of the R generated words are other than sole functions of the previously generated word; and c. iteratively executing step b until all generated words comprise only a single bit, wherein during each execution of step b, R>1, and wherein for at least one execution of step b, R>2. 17. The method in accordance with 18. The method in accordance with 19. The method in accordance with 20. The method in accordance with b1. generating R=2 ^{r }scrambling encoder output bits in response to r least significant bits of each previously generated word, wherein a sum of values of the scrambling encoder output bits equals a value represented by the r least significant bits of the previously generated output word, where r>0; and b2. generating each word of the set of R generated words as a sum of a corresponding one of the scrambling encoder output bits and a 2 k+1-r most significant bits of the previously generated word. 21. The method in accordance with 22. The method in accordance with 23. The method in accordance with b11. monitoring the scrambling encoder output bits and generating a plurality of ranking data words as functions of past values of the scrambling encoder output bits, wherein each ranking circuit output word corresponds to a separate scrambling encoder output bit and wherein all ranking data words have different values; and b12. generating each one of the scrambling encoder output bits of a value determined as a result of a comparison between values of a corresponding one of the ranking data words and the r least significant bits of the previously generated output word. 24. The method in accordance with b111. for each scrambling encoder output bit other than a first scrambling encoder output bit, generating a difference word sequence representing a difference in a sequence of values of the encoder output bit and a sequence of values of the first scrambling encoder output bit, b112. digitally filtering a corresponding one of the difference words to sequence produce a separate filter output word sequence; and b113. generating the ranking data words as functions of words of the filter output word sequences. 25. The method in accordance with 26. The method in accordance with 27. A digital-to-analog converter (DAC) for generating an N+1 level analog DAC output signal in response to each DAC input word of a sequence of DAC input words, wherein each DAC input word may represent any of N+1 different levels, where N is an integer greater than 4, the DAC comprising:
a plurality of switching blocks organized into a tree comprising at least a highest layer and a lowest layer of switching blocks,
wherein each switching block receives a block input word and converts it into R block output words, each of the R block output words having fewer bits than the block input word, such that a sum of values of the R block output words equals a value of the block input word, and such that when the value of the block input word is other than a multiple of R, a value of each one of its R block output words is other than solely a function of the value of the block input word,
wherein the highest layer of the tree includes a switching block receiving each successive DAC input word of the sequence as its block input word,
wherein each switching block of each layer of the tree other than the lowest layer supplies each of its R block output words as a block input word to a separate switching block of a next lower layer of the tree,
wherein each block output word of each switching block of the lowest layer of the tree consists of a single bit,
wherein for at least one of the plurality of switching blocks R>2;
a plurality of 1-bit DACs for converting the signal bit output words of switching blocks of the lowest layer of the tree into a plurality of analog signals; and a summer for summing the plurality of analog signals to produce the analog DAC output signal. 28. The DAC in accordance with a scrambling encoder for generating R=2′ scrambling encoder output bits in response to r least significant bits of the at least one switching block's block input word, wherein r>0, wherein a sum of values of scrambling encoder output bits is equal to a value represented by the r least significant bits of the at least one switching block's block input word; and R first summers, each corresponding to a separate one of the scrambling encoder output bits, each for generating a separate one of the at least one switching block's block R block output words as a sum of values of its corresponding scrambling encoder output bit and a 2 k+1 r most significant bits of the at least one switching block's block input word. 29. The DAC in accordance with a ranking circuit for monitoring the scrambling encoder output bits and for generating a plurality of ranking circuit output words as functions of past values of the scrambling encoder output bits, wherein each ranking circuit output word corresponds to a separate scrambling encoder output bit and wherein all ranking circuit output words have different values; and a plurality of first comparators, each corresponding to a separate one of the ranking data words, each for generating a corresponding one of the scrambling encoder output bit of a value determined as a result of a comparison between its corresponding one of the ranking data words and a value of the r least significant bits of the at least one switching block's input data word. 30. The DAC in accordance with a plurality of second summers for generating a plurality of summer output words, each second summer corresponding to a separate one of the scrambling encoder output bits other than a first scrambling encoder output bit and generating a summer output word representing a difference in values of its corresponding encoder output bit and the first scrambling encoder output bit, a plurality of digital filter for separately filtering the separate summer output words to produce a plurality of filter output words; and at least one second comparator for generating the ranking circuit output words as functions of filter output words. 31. The DAC in accordance with 32. The DAC in accordance with 33. The DAC in accordance with a first circuit for producing data d[n]=MOD(z[n],R); a second circuit for producing data q[n]=FLOOR(z[n]R); a scrambling encoder for generating R scrambling encoder output bits in response to values of data d[n], wherein a sum of values of scrambling encoder output bits is equal to a value represented by data d[n]; and R first summers, each corresponding to a separate one of the scrambling encoder output bits, each for generating a separate one of the at least one switching block's block R block output words as a sum of values of its corresponding scrambling encoder output bit and q[n]. Description 1. Field of the Invention The present invention relates in general to multiple-bit digital-to-analog encoders (DACS) and in particular, to a spectral shaping dynamic encoder for a DAC. 2. Description of Related Art Delta-Sigma ADC Architecture Assume ADC Delta-sigma modulator Spectral Shaping The feedback provided by DAC Multiple-bit (M>1) DACs are not inherently linear, yet a higher resolution delta-sigma data converters can employ multiple-bit DACs by using “mismatch-shaping” to resolve problems associated with their nonlinear behavior. The nonlinearity of a multiple-bit DAC arises from mismatches in its internal components, and while a “mismatch-shaping” DAC exhibits nonlinear behavior, it shapes the error component frequencies of its output signal resulting from component mismatches so that they reside outside a frequency band of interest. Thus, when DAC A “non-dynamic digital” encoder will always map each value of x[n] to the same value of its output word {x An ideal dynamic digital encoder Each switching block S Each switching block S -
- 1. setting the first output higher than the second in response to an odd input data value when it last set the second output higher in response to an odd input value, and
- 2. setting the second output higher than the first in response to an odd input data value when it last set the first output higher in response to an odd input value.
For example, when a switching block S_{i,j }receives an input sequence [5, 2, 4, 3], its output sequence may be [{3,2}, {1,1}, {2,2} and {1,2}]. Note that for the first odd input (5), switching block S_{i,j }produces output set {3,2} such that its first output exceeds its second output by 1. To compensate for this imbalance when the second odd input (3) arrives, switching block S_{i,j }makes its output set {1,2} so that the second output exceeds the first output by 1, thereby compensating for the previous allocation imbalance.FIGS. 5 and 6 show how encoder**32**ofFIG. 4 might set bits of output word {x**1**[n+**1**] . . . x**8**[n+**1**]} when successive words x[1] and x[n+1] both equal 5. Note that both output bit sets inFIGS. 5 and 6 have five “1” bits, but they do not occur in the same bit positions.
When the value of N is large, encoder A tree-structured dynamic encoder in accordance with the invention generates an N-bit encoder output word in response to each word of a sequence of binary encoder input words, wherein the number of encoder output word bits of value 1 equals a value of the encoder input word. Positions of bits of value 1 within each encoder output word vary to provide mismatch-shaping when the encoder bits are pseudorandomly selected. The dynamic encoder includes a tree of switching blocks, each for dynamically encoding a block input word into a set of output words, each having fewer bits than the block input word. A sum of values of the output words of each switching block equals a value of that switching block's input word. A switching block of the highest layer of the tree receives each successive encoder input word as its block input word, and each switching block of each layer of the tree other than its lowest layer supplies each of its output words as a block input word to a separate switching block of a next lower layer of the tree. Each switching block of the lowest layer of the tree generates single-bit block output words, each forming a separate bit of the N-bit encoder output word. In accordance with the invention, at least one of the switching blocks produces more than two output words. For example, when N is a power of four, each switching block is suitably a “radix-4” switching block produces four output words in response to each input word. Such an encoder requires only log The claims appended to this specification particularly point out and distinctly claim the subject matter of the invention. However those skilled in the art will best understand both the organization and method of operation of what the applicant(s) consider to be the best mode(s) of practicing the invention, together with further advantages and objects of the invention, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements. The invention relates to a mismatch-shaping, dynamic encoder suitable for use in a multiple-bit digital-to-analog converter (DAC). While the drawings and the specification below describe exemplary embodiments of best modes of practicing the invention, those of skill in the art will appreciate that other modes of practicing the invention are possible. The claims appended to this specification therefore define the true scope of the invention. As discussed above in connection with Dynamic Encoder Architecture A tree-structured dynamic encoder in accordance with the invention employs switching blocks producing more than two output words to reduce the number of levels of switching blocks, thereby increasing the maximum operating frequency of the encoder. For example When N is a power of 2, but not a power of 4, an encoder in accordance with the invention requires only log Switching Block Architecture A tree-structured dynamic encoder in accordance with the invention employs at least one radix-R switching block having one input word and producing R output words, where the sum of values of the block output words equals a value of the block input word and where R>2. When the integer value V of the block input word is of value 0 or is a multiple of R, all its output words suitably are of value, V/R. But when a switching block's input word value V is other than 0 or a multiple of R, values of its R output words may differ by as much as 1 from each other, with the integer value of each output word being slightly larger or smaller than the non-integer value of V/R. For example each radix-4 switching block S The manner in which scrambling encoder
IIR Filtering Scrambling Encoder Scrambling encoder The scrambling encoder architecture of
Summers As an alternative to using a fixed, predefined comparing priority for resolving ties as illustrated in Table 2, ranking circuit The transfer function F(z) of filters In an alternative embodiment of the invention, scrambling encoder
Each state corresponds to a separate bit of the set {d 1[n] . . . d4[n]} that was most recently set to 1. The next value of bit set {d1[n] . . . d4[n]} and the next state that the state machine enters depends on the incoming value of r[n] and the current state. This simple DWA scheme tends to equalize the average frequency of signals {d1[n] . . . d4[n]} regardless of the nature of input sequence d[n], but a more complicated a state machine program can increase randomization of bit positions within output bit set {d1[n] . . . d4[n]} to improve spectral shaping. Dithering can also help increase randomization of “1” bit positions within the output bit set when the state machines' current state is at least partly a function of a random number.
Radix-2 Switching Block Architecture Radix-R Switch The radix-4 switching block architecture of A tree-structured dynamic encoder in accordance with the invention can include radix-R switching blocks having more than one value of R to achieve a desired number of output bits. For example The foregoing specification and the drawings depict exemplary embodiments of the best mode(s) of practicing the invention, and elements or steps of the depicted best mode(s) exemplify the elements or steps of the invention as recited in the appended claims. The claims below are therefore intended to apply to any mode of practicing the invention comprising the combination of elements or steps as described in any one of the claims, including elements or steps that are functional equivalents of the example elements or steps of the exemplary embodiment(s) of the invention depicted in the specification and drawings. Classifications
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