US20050083091A1 - Adjustment of a clock duty cycle - Google Patents
Adjustment of a clock duty cycle Download PDFInfo
- Publication number
- US20050083091A1 US20050083091A1 US10/984,250 US98425004A US2005083091A1 US 20050083091 A1 US20050083091 A1 US 20050083091A1 US 98425004 A US98425004 A US 98425004A US 2005083091 A1 US2005083091 A1 US 2005083091A1
- Authority
- US
- United States
- Prior art keywords
- signal
- duty cycle
- clock signals
- producing
- uncorrected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
- H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
Definitions
- the present disclosure relates to adjustment of a clock duty cycle.
- Clock signals may be used in electronic circuits to provide timing information.
- An important aspect of a clock signal in many applications is the clock duty cycle, which may be defined as the ratio of the time the clock pulse is at a high level to the clock period. For example, a clock signal that is at the high level for one-half of the clock period and the low level for one half the clock period has a 50% duty cycle.
- a 50% duty cycle is desirable for many applications.
- both the rising and falling edges of the clock signal may be used to increase the total number of operations.
- Such systems may require a 50% duty cycle to help prevent or reduce jitter and other timing related distortions.
- the duty cycle may be critical to proper performance of the system.
- the duty cycle of the clock signal may become distorted or degraded, for example, as a result of semiconductor process errors. Other conditions also may cause the duty cycle to deviate from the desired value.
- Duty cycle correction circuits may be used to correct or adjust such distortions.
- FIG. 1 is a diagram of a circuit for adjusting the duty cycle of differential clock signals.
- FIGS. 2 ( a ) through 2 ( d ) are examples of timing diagrams for FIG. 1 .
- FIG. 3 illustrates further details of the circuit of FIG. 1 according to one implementation.
- FIG. 4 illustrates details of a charge pump that may be used in the circuit of FIG. 1 according to one particular implementation.
- FIG. 5 is a diagram of a circuit for adjusting the duty cycle of a single-ended clock signal.
- Circuits for adjusting the duty cycle of a clock(s) signal include a negative feedback loop for applying an offset signal to the uncorrected clock signal(s).
- the offset signal which corresponds to a duty cycle error of the corrected clock signal(s), adjusts the slicing level of the uncorrected clock signal(s) to cause the duty cycle error to converge toward a predetermined value, for example, zero.
- the techniques may be used to adjust the duty cycle error of differential clock signals as well as single-ended clock signals.
- the feedback loop may include a charge pump and an integrator to receive an output from the charge pump.
- a net charge in the integrator may correspond to the duty cycle error.
- a driver may be provided to amplify and clamp the values of the clock signals after applying a DC offset signal to the uncorrected clock signal(s).
- the circuits may be used to correct a signal having an arbitrary duty cycle to a signal having the same frequency with a 50% duty cycle.
- Use of an integrator in the feedback loop may allow the gain to be sufficiently large to minimize or reduce the duty cycle error.
- a circuit 20 may be used to adjust the differential duty cycle for a pair of clock signals (CN, CP).
- the circuit 20 may be used to correct the differential duty cycle and cause it to converge toward 50%.
- the circuit uses a negative feedback configuration that adds a DC offset signal (V OS ) to the uncorrected clock signals (CN, CP).
- V OS DC offset signal
- the DC offset voltage (V OS ) may be added to the input clock signals using summers 22 , 24 , to produce corrected clock signals, CN′ and CP′, respectively.
- the corrected clock signals (CN′, CP′) are applied as inputs to a driver 26 which forms part of the feedback loop.
- the output signals (OUTN, OUTP) from the driver 26 represent the clock signals with the corrected differential duty cycle.
- the driver may provide a high gain and may clamp the maximum amplitude of the output clock signals at a fixed value to prevent amplitude variation.
- the feedback loop also includes a differential charge pump 28 and integrator 30 which together produce an error voltage proportional to the duty cycle error.
- the output clock signals from the driver 26 are applied, respectively, to input terminals (UP, DN) of the charge pump.
- the charge pump sources a current I UP from one output (I) and sinks substantially the same amount of current into the second output ⁇ overscore (I) ⁇ .
- the charge pump sources a current I DN from the output ⁇ overscore (I) ⁇ and sinks substantially the same amount of current into the output I.
- the outputs of the charge pump are indicative of the instantaneous time difference between the high and low states of the clock signals. For example, if the duty cycle of the clock signals were exactly 50%, the average net output of the charge pump would be about zero.
- the current signals from the output terminals (I and ⁇ overscore (I) ⁇ ) of the charge pump are applied as input signals to the integrator 30 .
- the integrator may include capacitors (not shown in FIG. 1 ) which are charged and discharged depending on the output currents from the charge pump 28 .
- the net charge on the capacitors is proportional to the integrated value of the deviation of the clock signals from a predetermined duty cycle, for example, a 50% duty cycle.
- the DC offset voltage (V OS ) corresponds to the net charge and represents the duty cycle error of the differential clock signal (CP′ ⁇ CN′). For example, if the differential duty cycle were exactly 50%, then the DC offset voltage (V OS ) would be about zero volts.
- FIG. 2 ( a ) illustrate an example of a timing diagram in which it is assumed that the input clock signals have a duty cycle that deviates from 50%. In that case, the duty cycle of the differential clock signal (CP ⁇ CN) also will deviate from 50%.
- the feedback loop causes the offset voltage V OS to be applied to the input clock signals, effectively shifting the zero crossing (i.e., slicing level) of the clock signals, as illustrated in FIG. 2 ( b ).
- each of the modified clock signals (CP′, CP′) has approximately a 50% duty cycle
- the duty cycle of the differential clock signal (CP′ ⁇ CP′) may still deviate from 50% as a result of the amplitude variations in the modified clock signals.
- the driver 26 amplifies and clamps the modified clock signals to produce the output clock signals (OUTP, OUTN), as illustrated in FIG. 2 ( c ).
- the output clock signals have approximately a 50% duty cycle.
- the differential clock signal, OUTP ⁇ OUTN also has approximately a 50% duty cycle.
- the driver includes a pair of single-ended drivers, such as complementary metal oxide semiconductor (CMOS) inverters 32 , 34 .
- CMOS complementary metal oxide semiconductor
- the input clock signals (CP, CN) may be AC-coupled through the respective capacitors C C to the CMOS inverters which drive external loads shown as a pair of capacitors C L .
- the input to each inverter is the sum of the offset voltage (V OS ) and the corresponding uncorrected clock signal.
- the driver 26 may be implemented as a differential amplifier.
- the charge pump 28 may operate at the input clock rate.
- One specific implementation of the charge pump is illustrated in FIG. 4 and includes a p-type MOS current source, an n-type MOS current sink, and CMOS switches to direct the currents. Other types of charge pumps may be used as well.
- the integrator 30 may be implemented as a passive integrator including one or more capacitors.
- the feedback loop may include an active integrator.
- the active integrator 30 includes a differential operational amplifier 38 and feedback capacitors C p , C n .
- the output clock signals (OUTP, OUTN) drive the charge pump 28 , which charges and discharges the capacitors C p , C n .
- the active integrator keeps the potentials of the output terminals of the charge pump substantially equal to one another.
- the charge pump output currents may, therefore, be independent of the duty cycle error, as well as the offset voltage (V OS ), thereby relaxing requirements on the charge pump.
- the integrator outputs are fed back through a pair of resistors R F to control the DC voltage across the AC-coupling capacitors C C .
- the values of the feedback capacitors C p and C n in the integrator should be large enough to provide sufficient phase margin.
- the input offset voltage (V offset ) of the operational amplifier 38 may cause a small duty cycle error in the output.
- a negative feedback loop may be used to adjust the duty cycle of the single-ended clock signal CP and to cause it to converge toward 50%.
- the amplified clock output signal (OUT) from the driver 26 serves as the input to the UP terminal of the charge pump 28 .
- the clock output signal (OUT) also may serve as the input to an inverter 40 whose output is provided to the DN terminal of the charge pump.
- the output current from the terminal (I) of the charge pump serves as the input to the integrator 30 .
- the DC offset voltage at the output of the integrator represents the DC component of the clock signal (CP′) which, in turn, corresponds to the duty cycle error. Feeding the DC offset voltage back to the summer 24 causes the duty cycle to converge toward 50%.
- the foregoing techniques may be used for clock signals at high or low frequencies, but may be particularly advantageous for frequencies of 1.25 gigahertz (GHz) and higher.
- the techniques may be useful, for example, in high-speed digital transmitters in which the output data is clocked by a double-edge-triggered (DET) flip-flop.
- the techniques may be used in other systems as well.
Abstract
Circuits for adjusting the duty cycle of a clock(s) signal include a negative feedback loop for applying an offset signal to the uncorrected clock signal(s). The offset signal, which corresponds to a duty cycle error of the corrected clock signal(s), adjusts the slicing level of the uncorrected clock signal(s) to cause the duty cycle error to converge toward a predetermined value, for example, zero. The techniques may be used to adjust the duty cycle error of differential clock signals as well as single-ended clock signals.
Description
- The present disclosure relates to adjustment of a clock duty cycle.
- Clock signals may be used in electronic circuits to provide timing information. An important aspect of a clock signal in many applications is the clock duty cycle, which may be defined as the ratio of the time the clock pulse is at a high level to the clock period. For example, a clock signal that is at the high level for one-half of the clock period and the low level for one half the clock period has a 50% duty cycle.
- A 50% duty cycle is desirable for many applications. For example, in clock-driven digital systems requiring high speed operation, both the rising and falling edges of the clock signal may be used to increase the total number of operations. Such systems may require a 50% duty cycle to help prevent or reduce jitter and other timing related distortions. In such systems, the duty cycle may be critical to proper performance of the system. Unfortunately, the duty cycle of the clock signal may become distorted or degraded, for example, as a result of semiconductor process errors. Other conditions also may cause the duty cycle to deviate from the desired value. Duty cycle correction circuits may be used to correct or adjust such distortions.
-
FIG. 1 is a diagram of a circuit for adjusting the duty cycle of differential clock signals. - FIGS. 2(a) through 2(d) are examples of timing diagrams for
FIG. 1 . -
FIG. 3 illustrates further details of the circuit ofFIG. 1 according to one implementation. -
FIG. 4 illustrates details of a charge pump that may be used in the circuit ofFIG. 1 according to one particular implementation. -
FIG. 5 is a diagram of a circuit for adjusting the duty cycle of a single-ended clock signal. - Circuits for adjusting the duty cycle of a clock(s) signal include a negative feedback loop for applying an offset signal to the uncorrected clock signal(s). The offset signal, which corresponds to a duty cycle error of the corrected clock signal(s), adjusts the slicing level of the uncorrected clock signal(s) to cause the duty cycle error to converge toward a predetermined value, for example, zero. The techniques may be used to adjust the duty cycle error of differential clock signals as well as single-ended clock signals.
- In various implementations, the feedback loop may include a charge pump and an integrator to receive an output from the charge pump. A net charge in the integrator may correspond to the duty cycle error. A driver may be provided to amplify and clamp the values of the clock signals after applying a DC offset signal to the uncorrected clock signal(s).
- Various implementations may include one or more of the following advantages. For example, the circuits may be used to correct a signal having an arbitrary duty cycle to a signal having the same frequency with a 50% duty cycle. Use of an integrator in the feedback loop may allow the gain to be sufficiently large to minimize or reduce the duty cycle error.
- Other features and advantages will be readily apparent from the following detailed description, the accompanying drawings and the claims.
- As shown in
FIG. 1 , acircuit 20 may be used to adjust the differential duty cycle for a pair of clock signals (CN, CP). In particular, thecircuit 20 may be used to correct the differential duty cycle and cause it to converge toward 50%. - The circuit uses a negative feedback configuration that adds a DC offset signal (VOS) to the uncorrected clock signals (CN, CP). The DC offset voltage (VOS) may be added to the input clock
signals using summers - The corrected clock signals (CN′, CP′) are applied as inputs to a
driver 26 which forms part of the feedback loop. The output signals (OUTN, OUTP) from thedriver 26 represent the clock signals with the corrected differential duty cycle. The driver may provide a high gain and may clamp the maximum amplitude of the output clock signals at a fixed value to prevent amplitude variation. - The feedback loop also includes a
differential charge pump 28 andintegrator 30 which together produce an error voltage proportional to the duty cycle error. The output clock signals from thedriver 26 are applied, respectively, to input terminals (UP, DN) of the charge pump. When the signal at the terminal UP is a high level signal and the signal at the terminal DN is a low level signal, the charge pump sources a current IUP from one output (I) and sinks substantially the same amount of current into the second output {overscore (I)}. Conversely, when the signal at the terminal input UP is a low level signal and the signal at the terminal DN is a high level signal, the currents flow in the opposite direction—in other words, the charge pump sources a current IDN from the output {overscore (I)} and sinks substantially the same amount of current into the output I. The outputs of the charge pump are indicative of the instantaneous time difference between the high and low states of the clock signals. For example, if the duty cycle of the clock signals were exactly 50%, the average net output of the charge pump would be about zero. - The current signals from the output terminals (I and {overscore (I)}) of the charge pump are applied as input signals to the
integrator 30. The integrator may include capacitors (not shown inFIG. 1 ) which are charged and discharged depending on the output currents from thecharge pump 28. The net charge on the capacitors is proportional to the integrated value of the deviation of the clock signals from a predetermined duty cycle, for example, a 50% duty cycle. The DC offset voltage (VOS) corresponds to the net charge and represents the duty cycle error of the differential clock signal (CP′−CN′). For example, if the differential duty cycle were exactly 50%, then the DC offset voltage (VOS) would be about zero volts. On the other hand, as the duty cycle deviates from 50%, the DC offset voltage will vary as well. Applying the DC offset voltage signal to the input clock signals CN, CP adjusts the zero crossing point, or slicing level, of the input clock signals so that the differential duty cycle converges toward 50%. -
FIG. 2 (a) illustrate an example of a timing diagram in which it is assumed that the input clock signals have a duty cycle that deviates from 50%. In that case, the duty cycle of the differential clock signal (CP−CN) also will deviate from 50%. The feedback loop causes the offset voltage VOS to be applied to the input clock signals, effectively shifting the zero crossing (i.e., slicing level) of the clock signals, as illustrated inFIG. 2 (b). Although each of the modified clock signals (CP′, CP′) has approximately a 50% duty cycle, the duty cycle of the differential clock signal (CP′−CP′) may still deviate from 50% as a result of the amplitude variations in the modified clock signals. Thedriver 26 amplifies and clamps the modified clock signals to produce the output clock signals (OUTP, OUTN), as illustrated inFIG. 2 (c). The output clock signals have approximately a 50% duty cycle. Furthermore, as shown byFIG. 2 (d), the differential clock signal, OUTP−OUTN, also has approximately a 50% duty cycle. - A particular implementation of the duty cycle correction circuit is shown in
FIG. 3 . In this implementation, the driver includes a pair of single-ended drivers, such as complementary metal oxide semiconductor (CMOS)inverters - In other embodiments, the
driver 26 may be implemented as a differential amplifier. - The
charge pump 28 may operate at the input clock rate. One specific implementation of the charge pump is illustrated inFIG. 4 and includes a p-type MOS current source, an n-type MOS current sink, and CMOS switches to direct the currents. Other types of charge pumps may be used as well. - The
integrator 30 may be implemented as a passive integrator including one or more capacitors. Alternatively, as shown inFIG. 3 , the feedback loop may include an active integrator. In the implementation ofFIG. 3 , theactive integrator 30 includes a differentialoperational amplifier 38 and feedback capacitors Cp, Cn. The output clock signals (OUTP, OUTN) drive thecharge pump 28, which charges and discharges the capacitors Cp, Cn. The active integrator keeps the potentials of the output terminals of the charge pump substantially equal to one another. The charge pump output currents may, therefore, be independent of the duty cycle error, as well as the offset voltage (VOS), thereby relaxing requirements on the charge pump. The integrator outputs are fed back through a pair of resistors RF to control the DC voltage across the AC-coupling capacitors CC. - To ensure stability of the duty cycle correction loop, the values of the feedback capacitors Cp and Cn in the integrator should be large enough to provide sufficient phase margin.
- In some applications, the input offset voltage (Voffset) of the
operational amplifier 38 may cause a small duty cycle error in the output. The error in the output is proportional to the input offset voltage and is inversely proportional to the slew rate (r) and period (T) of the input signal. For example, assuming that the rise and fall times are one fourth the period—r·(T/4)=VDD=1.2 volts—then an input offset voltage of 10 millivolts (mV) would result in an output duty cycle error or about only 0.4%. - Although the particular circuits described above are illustrated in the context of differential clock signals, the techniques may be used for adjusting the duty cycle of a single-ended clock signal as well. As shown in
FIG. 5 , a negative feedback loop may be used to adjust the duty cycle of the single-ended clock signal CP and to cause it to converge toward 50%. The amplified clock output signal (OUT) from thedriver 26 serves as the input to the UP terminal of thecharge pump 28. The clock output signal (OUT) also may serve as the input to aninverter 40 whose output is provided to the DN terminal of the charge pump. The output current from the terminal (I) of the charge pump serves as the input to theintegrator 30. The DC offset voltage at the output of the integrator represents the DC component of the clock signal (CP′) which, in turn, corresponds to the duty cycle error. Feeding the DC offset voltage back to thesummer 24 causes the duty cycle to converge toward 50%. - The foregoing techniques may be used for clock signals at high or low frequencies, but may be particularly advantageous for frequencies of 1.25 gigahertz (GHz) and higher. The techniques may be useful, for example, in high-speed digital transmitters in which the output data is clocked by a double-edge-triggered (DET) flip-flop. The techniques may be used in other systems as well.
- Other implementations are within the scope of the claims.
Claims (21)
1-18. (canceled)
19. A method comprising:
obtaining one or more corrected clock signals based on one or more uncorrected clock signals;
obtaining a DC offset signal corresponding to a duty cycle error of the one or more corrected clock signals; and
adjusting a slicing level for the one or more uncorrected clock signals based on the DC offset signal, wherein the adjusting includes adding the DC offset signal to the one or more uncorrected clock signals.
20. The method of claim 19 including repeating said obtaining one or more corrected clock signals, obtaining a DC offset signal and adjusting a slicing level,
wherein adjusting the slicing level causes the duty cycle error to converge toward a predetermined value.
21. The method of claim 20 wherein the duty cycle error converges toward zero.
22. The method of claim 21 wherein the duty cycle error is a differential duty cycle error for a pair of corrected clock signals.
23. A method comprising:
receiving an uncorrected clock signal as an input to a negative feedback loop;
producing an integrated charge signal that is proportional to a clock duty cycle error;
producing an offset voltage signal based on the integrated charge signal; and
adjusting a slicing level for the uncorrected clock signal based on the offset voltage,
wherein the adjusting includes adding the offset voltage signal to the uncorrected clock signal.
24. The method of claim 23 wherein adjusting the slicing level includes adding the offset voltage signal to the uncorrected clock signal.
25. The method of claim 24 including:
amplifying a signal representing a sum of the uncorrected clock signal and the offset signal;
clamping the amplified signal; and
producing a corrected clock signal based on the clamped signal.
26. The method of claim 25 wherein the integrated charge signal is proportional to a duty cycle error of the corrected clock signal.
27. The method of claim 25 including producing a corrected clock signal having a duty cycle that converges toward a predetermined value.
28. The method of claim 25 including producing a corrected clock signal having a duty cycle that converges toward about 50%.
29. The method of claim 25 including repeatedly producing an offset voltage signal based on the integrated charge signal and adjusting a slicing level for the uncorrected clock signal based on the offset voltage.
30. The method of claim 25 wherein producing an integrated charge signal includes producing a signal indicative of a time difference between high and low states of the clock signal,
wherein the integrated charge signal is proportional to an integrated value of a deviation of the clock signal from a predetermined duty cycle.
31. A method comprising:
receiving a plurality of uncorrected clock signals as input to a negative feedback loop;
producing a net integrated charge that is proportional to a duty cycle error;
producing an offset voltage signal based on the net integrated charge; and
adjusting a slicing level for the uncorrected clock signals based on the offset voltage,
wherein the adjusting includes adding the offset voltage signal to the uncorrected clock signals.
32. The method of claim 31 wherein adjusting the slicing level includes adding the offset voltage signal to the uncorrected clock signals.
33. The method of claim 32 including:
amplifying signals each of which represents, respectively, a sum of one of the uncorrected clock signals and the offset signal;
clamping the amplified signals; and
producing corrected clock signals based on the clamped signals.
34. The method of claim 33 wherein the net integrated charge signal is proportional to a differential duty cycle error of the corrected clock signals.
35. The method of claim 33 including producing corrected clock signals having a differential duty cycle that converges toward a predetermined value.
36. The method of claim 33 including producing corrected clock signals having a differential duty cycle that converges toward about 50%.
37. The method of claim 33 including repeatedly producing an offset voltage signal based on the net integrated charge and adjusting a slicing level for the uncorrected clock signals based on the offset voltage.
38. The method of claim 33 wherein producing an integrated charge signal includes producing a signal indicative of a time difference between high and low states of the clock signal, wherein the integrated charge signal is proportional to an integrated value of a deviation of the clock signal from a predetermined duty cycle.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/984,250 US20050083091A1 (en) | 2002-10-29 | 2004-11-09 | Adjustment of a clock duty cycle |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/282,398 US6833743B2 (en) | 2002-10-29 | 2002-10-29 | Adjustment of a clock duty cycle |
US10/984,250 US20050083091A1 (en) | 2002-10-29 | 2004-11-09 | Adjustment of a clock duty cycle |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/282,398 Continuation US6833743B2 (en) | 2002-10-29 | 2002-10-29 | Adjustment of a clock duty cycle |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050083091A1 true US20050083091A1 (en) | 2005-04-21 |
Family
ID=32107350
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/282,398 Expired - Fee Related US6833743B2 (en) | 2002-10-29 | 2002-10-29 | Adjustment of a clock duty cycle |
US10/984,250 Abandoned US20050083091A1 (en) | 2002-10-29 | 2004-11-09 | Adjustment of a clock duty cycle |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/282,398 Expired - Fee Related US6833743B2 (en) | 2002-10-29 | 2002-10-29 | Adjustment of a clock duty cycle |
Country Status (1)
Country | Link |
---|---|
US (2) | US6833743B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110050304A1 (en) * | 2009-08-28 | 2011-03-03 | Elpida Memory, Inc. | Semiconductor apparatus |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005038468A1 (en) * | 2003-09-22 | 2005-04-28 | Brother International Corporation | A method and apparatus for sensing applied forces |
US7265597B2 (en) * | 2004-12-22 | 2007-09-04 | Intel Corporation | Differential clock correction |
JP4781744B2 (en) * | 2005-08-05 | 2011-09-28 | ローム株式会社 | POWER SUPPLY DEVICE AND ELECTRIC DEVICE USING THE SAME |
KR100712537B1 (en) * | 2005-10-26 | 2007-04-30 | 삼성전자주식회사 | Clock generating circuit |
DE102006051284B4 (en) * | 2005-10-26 | 2011-06-16 | Samsung Electronics Co., Ltd., Suwon | Duty cycle correction circuit, integrated circuit, phase locked loop circuit, delay locked loop circuit, memory device and method for generating a clock signal |
TWI304293B (en) * | 2005-12-23 | 2008-12-11 | Ind Tech Res Inst | Duty cycle corrector circuit with widely operating range |
US20070229115A1 (en) * | 2006-01-25 | 2007-10-04 | International Business Machines Corporation | Method and apparatus for correcting duty cycle error in a clock distribution network |
US7642828B2 (en) * | 2006-06-07 | 2010-01-05 | Nec Electronics Corporation | Level conversion circuit with duty correction |
US20090189595A1 (en) * | 2006-06-30 | 2009-07-30 | Nxp B.V. | Circuit for detecting the duty cycle of clock signals |
KR100771887B1 (en) * | 2006-10-17 | 2007-11-01 | 삼성전자주식회사 | Duty detector and duty detection/correction circuit including the same |
US7495491B2 (en) * | 2007-02-28 | 2009-02-24 | Intel Corporation | Inverter based duty cycle correction apparatuses and systems |
JP2010127632A (en) * | 2008-11-25 | 2010-06-10 | Renesas Electronics Corp | Duty detection circuit, duty correction circuit, and duty detection method |
US7839195B1 (en) | 2009-06-03 | 2010-11-23 | Honeywell International Inc. | Automatic control of clock duty cycle |
CN102255499B (en) * | 2011-06-28 | 2015-12-09 | 上海华虹宏力半导体制造有限公司 | Voltagre regulator |
US9124266B1 (en) | 2012-08-31 | 2015-09-01 | Marvell Israel (M.I.S.L) Ltd. | Increasing switching speed of logic circuits |
US10205445B1 (en) | 2017-09-25 | 2019-02-12 | Synopsys, Inc. | Clock duty cycle correction circuit |
CN116527020B (en) * | 2023-07-03 | 2023-09-15 | 芯耀辉科技有限公司 | Duty cycle calibration circuit and method |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4644196A (en) * | 1985-01-28 | 1987-02-17 | Motorola, Inc. | Tri-state differential amplifier |
US4720686A (en) * | 1987-01-14 | 1988-01-19 | Motorola, Inc. | Circuit for converting a fully differential amplifier to a single-ended output amplifier |
US4724337A (en) * | 1985-03-29 | 1988-02-09 | Kabushiki Kaisha Toshiba | Automatic gain control detection circuit |
US4789799A (en) * | 1983-04-05 | 1988-12-06 | Tektronix, Inc. | Limiting circuit |
US4992757A (en) * | 1988-09-26 | 1991-02-12 | Nec Corp. | Differential amplifying circuit |
US5182476A (en) * | 1991-07-29 | 1993-01-26 | Motorola, Inc. | Offset cancellation circuit and method of reducing pulse pairing |
US5572158A (en) * | 1994-02-15 | 1996-11-05 | Rambus, Inc. | Amplifier with active duty cycle correction |
US6047031A (en) * | 1996-04-04 | 2000-04-04 | Mitel Semiconductor Limited | Error correction circuit |
US6369629B1 (en) * | 1997-11-19 | 2002-04-09 | Sharp Kabushiki Kaisha | Flip-flop circuit |
US6384652B1 (en) * | 2000-08-17 | 2002-05-07 | Vanguard International Semiconductor Corporation | Clock duty cycle correction circuit |
US6411145B1 (en) * | 2001-06-14 | 2002-06-25 | Lsi Logic Corporation | Feedback control of clock duty cycle |
US6426660B1 (en) * | 2001-08-30 | 2002-07-30 | International Business Machines Corporation | Duty-cycle correction circuit |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63290046A (en) | 1987-05-21 | 1988-11-28 | Pioneer Electronic Corp | Correction circuit for pulse width distortion |
JPH01307312A (en) | 1988-05-23 | 1989-12-12 | Advanced Micro Devicds Inc | Circuit for generating a series of pulses having predetermined and controlled impact coefficient |
DE4018615A1 (en) | 1989-06-09 | 1990-12-13 | Licentia Gmbh | Frequency converter for quadrature modulator or demodulator |
US6369626B1 (en) * | 1997-03-21 | 2002-04-09 | Rambus Inc. | Low pass filter for a delay locked loop circuit |
-
2002
- 2002-10-29 US US10/282,398 patent/US6833743B2/en not_active Expired - Fee Related
-
2004
- 2004-11-09 US US10/984,250 patent/US20050083091A1/en not_active Abandoned
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4789799A (en) * | 1983-04-05 | 1988-12-06 | Tektronix, Inc. | Limiting circuit |
US4644196A (en) * | 1985-01-28 | 1987-02-17 | Motorola, Inc. | Tri-state differential amplifier |
US4724337A (en) * | 1985-03-29 | 1988-02-09 | Kabushiki Kaisha Toshiba | Automatic gain control detection circuit |
US4720686A (en) * | 1987-01-14 | 1988-01-19 | Motorola, Inc. | Circuit for converting a fully differential amplifier to a single-ended output amplifier |
US4992757A (en) * | 1988-09-26 | 1991-02-12 | Nec Corp. | Differential amplifying circuit |
US5182476A (en) * | 1991-07-29 | 1993-01-26 | Motorola, Inc. | Offset cancellation circuit and method of reducing pulse pairing |
US5572158A (en) * | 1994-02-15 | 1996-11-05 | Rambus, Inc. | Amplifier with active duty cycle correction |
US6047031A (en) * | 1996-04-04 | 2000-04-04 | Mitel Semiconductor Limited | Error correction circuit |
US6369629B1 (en) * | 1997-11-19 | 2002-04-09 | Sharp Kabushiki Kaisha | Flip-flop circuit |
US6384652B1 (en) * | 2000-08-17 | 2002-05-07 | Vanguard International Semiconductor Corporation | Clock duty cycle correction circuit |
US6411145B1 (en) * | 2001-06-14 | 2002-06-25 | Lsi Logic Corporation | Feedback control of clock duty cycle |
US6426660B1 (en) * | 2001-08-30 | 2002-07-30 | International Business Machines Corporation | Duty-cycle correction circuit |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110050304A1 (en) * | 2009-08-28 | 2011-03-03 | Elpida Memory, Inc. | Semiconductor apparatus |
US8604835B2 (en) * | 2009-08-28 | 2013-12-10 | Elpida Memory, Inc. | Semiconductor apparatus |
US8896348B2 (en) | 2009-08-28 | 2014-11-25 | Ps4 Luxco S.A.R.L. | Semiconductor apparatus |
Also Published As
Publication number | Publication date |
---|---|
US20040080350A1 (en) | 2004-04-29 |
US6833743B2 (en) | 2004-12-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6833743B2 (en) | Adjustment of a clock duty cycle | |
US6617926B2 (en) | Tail current node equalization for a variable offset amplifier | |
US20020140477A1 (en) | Duty cycle correction circuit and apparatus and method employing same | |
EP2041866B1 (en) | Class d audio amplifier | |
US10205445B1 (en) | Clock duty cycle correction circuit | |
JP2007174669A (en) | Circuit and method for correcting duty cycle distortion of differential clock signal | |
US10110204B2 (en) | Low power buffer with gain boost | |
US20110291724A1 (en) | Duty cycle correction circuit | |
US7525358B1 (en) | Duty-cycle correction for clock receiver | |
US7821316B2 (en) | Multiphase clock generator with enhanced phase control | |
JP2001358544A (en) | Amplifier circuit | |
US20090091364A1 (en) | Semiconductor circuit | |
EP1444777A1 (en) | A power amplifier module with distortion compensation | |
US9503119B2 (en) | Common mode sampling mechanism for residue amplifier in switched current pipeline analog-to-digital converters | |
EP1536561B1 (en) | Current controlled oscillator | |
US7688125B2 (en) | Latched comparator and methods for using such | |
US6975100B2 (en) | Circuit arrangement for regulating the duty cycle of electrical signal | |
US6384620B1 (en) | Signal deciding apparatus | |
US11063567B2 (en) | Input circuit with wide range input voltage compatibility | |
US20090206900A1 (en) | Duty cycle correction circuit and method for correcting duty cycle | |
CN109962694B (en) | Duty cycle adjusting circuit | |
JP2010273058A (en) | Amplitude limit amplifying circuit | |
TWI816426B (en) | Audio system, class-d driver circuit and control method thereof | |
US6650184B2 (en) | High gain amplifier circuits and their applications | |
JP3980337B2 (en) | Track hold circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |