Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20050087134 A1
Publication typeApplication
Application numberUS 10/931,845
Publication dateApr 28, 2005
Filing dateAug 31, 2004
Priority dateMar 1, 2001
Also published asUS6852167, US7410668, US20020122885, US20050034662, US20070107661, US20070131169
Publication number10931845, 931845, US 2005/0087134 A1, US 2005/087134 A1, US 20050087134 A1, US 20050087134A1, US 2005087134 A1, US 2005087134A1, US-A1-20050087134, US-A1-2005087134, US2005/0087134A1, US2005/087134A1, US20050087134 A1, US20050087134A1, US2005087134 A1, US2005087134A1
InventorsKie Ahn
Original AssigneeMicron Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Methods, systems, and apparatus for uniform chemical-vapor depositions
US 20050087134 A1
Abstract
Integrated circuits, the key components in thousands of electronic and computer products, are generally built layer by layer on a silicon substrate. One common technique for forming layers is called chemical-vapor deposition (CVD.) Conventional CVD systems not only form layers that have non-uniform thickness, but also have large chambers that make the CVD process wasteful and slow. Accordingly, the inventor devised new CVD systems, methods, and apparatuses. One exemplary CVD system includes an outer chamber, a substrate holder, and a unique gas-distribution fixture. The fixture includes a gas-distribution surface having holes for dispensing a gas and a gas-confinement member that engages or cooperates with the substrate holder to form an inner chamber within the outer chamber. The inner chamber has a smaller volume than the outer chamber, which not only facilitates depositions of more uniform thickness, but also saves gas and speeds up the deposition process.
Images(5)
Previous page
Next page
Claims(24)
1. A chemical-vapor-deposition system comprising:
a first chamber for confining gases; and
a second chamber within the first chamber for at least partially containing a substrate during deposition.
2. The system of claim 1, wherein the first chamber is a right cylindrical chamber.
3. The system of claim 1, wherein the second chamber comprises a surface of a substrate-support structure.
4. The system of claim 3, wherein the second chamber further comprises a gas-distribution fixture for atomic-layer deposition, the fixture confronting the surface of the substrate-support structure and comprising:
a non-reactive plate including a plurality of holes; and
a wall surrounding at least a portion of the plate.
5. A chemical-vapor deposition system comprising:
first means for confining one or more gases;
second means for confining one or more gases, the first means at least partly contained within the first means; and
third means for confining one or more gases, the third means at least partly contained within the first means.
6. A gas-distribution fixture for atomic-layer deposition, the fixture comprising:
a non-reactive plate including a plurality of holes; and
a wall surrounding at least a portion of the plate;
7. The fixture of claim 6, wherein the wall consists essentially of a material that is different from that of the non-reactive plate.
8. The fixture of claim 6, wherein the non-reactive plate consists essentially of silicon and a silicon oxide.
9. The fixture of claim 6, wherein the wall has a uniform height measured from a surface of the non-reactive plate.
10. The fixture of claim 6, wherein the wall consists essentially of a material that is different from that of the second non-metallic plate.
11. The fixture of claim 6, wherein the wall consists essentially of a stainless steel.
12. The fixture of claim 6, wherein the non-reactive plate is formed in a method comprising:
forming one or more channels in a first plate;
forming two or more holes in a second plate;
forming a bond between the first and second plates.
13. A method of making at least a portion of a gas-distribution fixture for a chemical-vapor-deposition system, the method comprising:
forming one or more channels in a first plate;
forming two or more holes in a second plate;
forming a bond between the first and second plates.
14. The method of claim 13, wherein forming one or more channels in the first plate comprises:
masking the first plate to define a respective position of each of the channels; and
etching the masked first plate to form the channels.
15. The method of claim 13, wherein etching the masked first plate comprises wet etching the masked first plate.
16. The method of claim 13, wherein forming the one or more channels comprises forming two or more perpendicular channels.
17. The method of claim 13, wherein forming the one or more channels comprises forming two or more channels having a common width and depth.
18. The method of claim 13, wherein forming holes in the second plate comprises:
masking the second plate to define a respective size, shape, and position of each of the holes; and
etching the masked second plate to form the channels.
19. The method of claim 13 wherein etching the masked second plate comprises wet etching the masked first plate.
20. The method of claim 13, wherein forming the holes comprises forming two or more holes of approximately the same shape and size.
21. The method of claim 13, wherein forming the one or more channels comprises forming two or more channels having a common width and depth.
22. The method of claim 13:
wherein the first and second plates consist essentially of silicon; and
wherein forming the bond between the first and second plates comprises:
aligning the first and second plates such that the one or more channels are in fluid communication with the two or more holes; and
using a silicon-wafer bonding technique to effect the bond.
23. The method of claim 13, wherein forming the one or more channels in the first plate occurs after forming the two or more holes in the second plate;
24. A method of making at least a portion of a gas-distribution fixture for a chemical-vapor-deposition system, the method comprising:
forming one or more channels in a first plate;
forming two or more holes in a second plate;
aligning the first and second plates, with at least one of the holes aligned with one of the channels; and
bonding the first and second plates to each other.
Description
  • [0001]
    This application is a Divisional of U.S. application Ser. No. 09/797,324, filed Mar. 1, 2001 which is incorporated herein by reference.
  • TECHNICAL FIELD
  • [0002]
    This invention concerns methods of making integrated circuits, particularly layer-formation, such as chemical-vapor deposition.
  • BACKGROUND OF THE INVENTION
  • [0003]
    Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators generally build these circuits layer by layer, using techniques, such as deposition, doping, masking, and etching, to form thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, known as a wafer. The components are then wired, or interconnected, together to define a specific electric circuit, such as a computer memory.
  • [0004]
    One common technique for forming layers in an integrated circuit is called chemical vapor deposition. Chemical vapor deposition generally entails placing a substrate in a reaction chamber, heating the substrate to prescribed temperatures, and introducing one or more gases, known as precursor gases, into the chamber to begin a deposition cycle. The precursor gases enter the chamber through a gas-distribution fixture, such as a gas ring or a showerhead, one or more centimeters above the substrate, and descend toward the heated substrate. The gases react with each other and/or the heated substrate, blanketing its surface with a layer of material. An exhaust system then pumps gaseous by-products or leftovers from the reaction out of the chamber through a separate outlet to complete the deposition cycle.
  • [0005]
    Conventional chemical-vapor-deposition (CVD) systems suffer from at least two problems. First, conventional CVD systems generally form layers that include microscopic hills and valleys and thus have non-uniform thickness. In the past, fabricators have been able to overcome these hills and valleys through use of post-deposition planarization or other compensation techniques. However, escalating demands for greater circuit density, for thinner layers, and for larger substrates make it increasingly difficult, if not completely impractical, to overcome the non-uniform thickness of conventional CVD layers.
  • [0006]
    Second, some conventional CVD systems are also inefficient and time consuming. One significant factor affecting both CVD efficiency and duration is the size of conventional reaction chambers, which are generally made large to allow a loading mechanism to insert and extract the substrate. Large chambers generally require more gases to be introduced to achieve desired gas concentrations. However, much of this gas is not only unnecessary based on the amount of material deposited, but is typically treated as waste. Moreover, large chambers also take longer to fill up or pump out, prolonging deposition cycles and thus slowing fabrication of integrated circuits.
  • [0007]
    Accordingly, there is a need for better systems and methods of chemical-vapor deposition.
  • SUMMARY OF THE INVENTION
  • [0008]
    To address these and other problems, the present inventor devised new systems, methods, and apparatuses for chemical-vapor deposition. One exemplary chemical-vapor deposition system includes an outer chamber, a substrate holder, and a unique gas-distribution fixture. The fixture includes a gas-distribution surface having holes for dispensing a gas and a gas-confinement member that forms a wall around the holes. In operation, the gas-confinement member engages, or otherwise cooperates with the substrate holder to form an inner chamber within the outer chamber.
  • [0009]
    The inner chamber has a smaller volume than the outer chamber and thus consumes less gas during the deposition process than would the outer chamber used alone. Also, the smaller chamber volume allows the exhaust system to pump the chamber more quickly, thus increasing the rate of the CVD process. In addition, the exemplary showerhead is made of a material, like silicon, which can be easily passivated to reduce reaction with reactive gases, thus reducing chemical-vapor buildup in the showerhead. Also, the exemplary showerhead includes a configuration of holes that permits uniform gas flow.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0010]
    FIG. 1 is a side view of an exemplary deposition reactor according to the invention;
  • [0011]
    FIG. 2 is a top view of an exemplary gas-distribution fixture according to the invention;
  • [0012]
    FIG. 3 is a flowchart showing an exemplary method according to the invention; and
  • [0013]
    FIG. 4 is a diagram of an exemplary deposition system 400 incorporating a set of four deposition stations similar in structure and function to system 100 of FIG. 1.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0014]
    The following detailed description, which references and incorporates FIGS. 1-4, describes and illustrates specific embodiments of the invention. These embodiments, offered not to limit but only to exemplify and teach the invention, are shown and described in sufficient detail to enable those skilled in the art to make and use the invention. Thus, where appropriate to avoid obscuring the invention, the description may omit certain information known to those of skill in the art.
  • [0015]
    FIG. 1 shows an exemplary chemical-vapor-deposition system 100 which incorporates teachings of the present invention. In particular, system 100 includes a chamber 110, a wafer holder 120, a gas-distribution fixture 130, a gas supply system 140, and exhaust pump 150, and a exhaust pump 160.
  • [0016]
    More particularly, chamber 110 includes respective top and bottom plates 112 and 114 and a sidewall 116. In the exemplary embodiment, chamber 110 is a cylindrical structure formed of stainless steel or glass. However, other embodiments use different structures and materials. Bottom plate 114 includes an opening 114.1. Extending through opening 114.1 is a stem portion 122 of wafer holder 120.
  • [0017]
    Wafer holder 120 also includes a support platform 124, one or more heating elements 126, and one or more temperature sensors 128. Support platform 124 supports one or more substrates, wafers, or integrated-circuit assemblies 200. Substrate 200 has an exemplary width or diameter of about 30 centimeters and an exemplary thickness in the range of 850-1000 microns. (The term “substrate,” as used herein, encompasses a semiconductor wafer as well as structures having one or more insulative, conductive, or semiconductive layers and materials. Thus, for example, the term embraces silicon-on-insulator, silicon-on-sapphire, and other advanced structures.) Heating elements 126 and temperature sensors 128 are used for heating substrates 200 to a desired temperature. Holder 120 is coupled to a power supply and temperature control circuitry (both of which are not shown.) In the exemplary embodiment, wafer holder 120 is rotatable either manually or automatically and raises via manual or automatic lever mechanism (not shown). Above wafer holder 120 and substrate 200 is gas-distribution fixture 130.
  • [0018]
    Fixture 130 includes a gas-distribution member 132, a surface-projection (or gas-confinement) member 134, and a gas inlet 136. Gas inlet 132 couples to gas-supply, gas-distribution channels 134, and a gas inlet 136. In the exemplary embodiment, fixture 130 has two operating positions 138.1 and 138.2 relative support platform 124. Fixture 130 takes operating position 138.1, before and after depositions and operating position 138.2 during depositions.
  • [0019]
    Gas-distribution member 132 includes gas-distribution holes, or orifices, 132.1 and gas-distribution channels 132.2. Holes 132.1 define a gas-distribution surface 132.3. In the exemplary embodiment, holes 132.1 are substantially circular with a common diameter in the range of 15-20 microns; gas-distribution channels 132.2 have a common width in the range of 20-45 microns; and surface 132.3 is substantially planar and parallel to support platform 124 of wafer holder 120. However, other embodiments use other surface forms as well as shapes and sizes of holes and channels. The distribution and size of holes may also affect deposition thickness and thus might be used to assist thickness control. Holes 132.1 are coupled through gas-distribution channels 132.2 to gas inlet 136.
  • [0020]
    Surface-projection member 134 projects or extends from surface 132.3 toward support platform 124, defining a fixture cavity 134.1. The exemplary embodiment forms surface-projection member 134 from stainless steel as a uniform annular or circular wall or collar that projects perpendicularly from surface 132 to define a right-cylindrical cavity. However, other embodiments form member 134 to project at other angles relative surface 132.3. For example, some form the projection at an acute or obtuse angle, such as 45 or 135 degrees, and others form the projection to peripherally define an oval, ellipse, triangle, square, or any desirable regular or irregular polygon. Thus, the present invention encompasses a wide variety of projection shapes and configurations, indeed any projection shape that facilitates definition of an effective cavity or gas-confinement volume in cooperation with wafer holder 120 and/or substrate 200.
  • [0021]
    FIG. 2, a plan view, shows further details of the exemplary embodiment of gas-distribution fixture 130. In particular, the plan view shows not only exemplary circular peripheries of gas-distribution member 132 and surface-projection member 134, but also an exemplary distribution pattern for holes 132.1 and an exemplary orthogonal arrangement of gas-distribution channels 132.2. Other embodiments, however, use other hole distribution patterns and channel arrangements. For example, some embodiments include random or concentric hole patterns and various channel geometries, including concentric circles, rectangles, or other regular or irregular concentric polygons. Some embodiments may also dedicate various subsets of channels and corresponding holes to different gases.
  • [0022]
    Gas-distribution member 132 can be made in a number of ways. One exemplary method entails providing two wafers of materials, such as silicon or other passivatable, inert, or non-reactive material. One wafer is patterned and etched, for example, using conventional photolithographic or micro-electro-mechanical systems (MEMS) technology, to form a pattern holes, and the other wafer is patterned and etched to include a complementary or corresponding pattern of gas-distribution channels. (MEMS refers to the technologies of making structures and devices with micrometer dimensions.) Dry-etching techniques produce small openings and channels, while wet etching produces larger openings and channels. For further details, see, for example, M. Engelhardt, “Modern Application of Plasma Etching and Patterning in Silicon Process Technology,” Contrib. Plasma Physics, vol. 39, no. 5, pp. 473-478 (1999).
  • [0023]
    The two wafers are then bonded together with the holes and channels in appropriate alignment using known wafer-bonding techniques. See, for example, G. Krauter et al., “Room Temperature Silicon Wafer Bonding with Ultra-Thin Polymer Films,” Advanced Materials, vol. 9, no. 5, pp. 417-420 (1997); C. E. Hunt et al., “Direct Bonding of Micromachined Silicon Wafers for Laser Diode Heat Exchanger Applications,” J. Micromech. Microeng, vol. 1, pp. 152-156 (1991); Zucker, O. et al., “Applications of oxygen plasma processing to silicon direct bonding,” Sensors and Actuators, A. Physical, vol. 36, no. 3, pp. 227-231 (1993), which are all incorporated herein by reference. See also, copending and co-assigned U.S. patent application Ser. No. 09/189,276 (dockets 303.534US1 and 97-1468) entitled “Low Temperature Silicon Wafer Bond Process with Bulk Material Bond Strength,” which was filed Nov. 10, 1998 and which is also incorporated herein by reference. The resulting bonded structure is then passivated using thermal oxidation for example.
  • [0024]
    For an alternative fixture structure and manufacturing method that can be combined with those of the exemplary embodiment, see U.S. Pat. No. 5,595,606, entitled “Shower Head and Film Forming Apparatus Using Same, which is incorporated herein by reference. In particular, one embodiment based on this patent adds a projection or gas-confinement member to the reported showerhead structure.
  • [0025]
    FIG. 1 also shows that gas inlet 136 couples gas-distribution fixture 130 to gas-supply system 140. Gas-supply system 140 includes a gas line 142, gas sources 144 and 145, and mass-flow controllers 146 and 147. Gas line or conduit 142, which includes a flexible portion 142.1, passes through an opening 116.1 in chamber sidewall 116 to connect with gas inlet 136. Gas source 144 is coupled via mass-flow controller 146 to gas line 142, and gas source 147 is coupled via mass-flow controller 147 to gas line 142. The exemplary embodiment provides computer-controlled thermal or pressure-based mass-flow controllers; however, the invention is not limited to any particular number or type of mass-flow controller, nor to any particular number or set of gas sources.
  • [0026]
    System 100 also includes vacuum pumps 150 and 160. Vacuum pump 150 is coupled to gas-distribution fixture 130 via a mass-flow controller 152 and gas line 142. And, vacuum pump 160 is coupled to the interior of chamber 110 via a line 162 and an opening 114.2 in chamber bottom plate 114. In the exemplary embodiment, vacuum pump 160 has a greater capacity than vacuum pump 150.
  • [0027]
    In general operation, system 100 functions, via manual or automatic control, to move gas-distribution fixture 130 from operating position 138.1 to position 138.2, to introduce reactant gases through fixture 130 onto substrate 200, and to deposit desired matter through chemical-vapor deposition onto the substrate. After the desired matter is deposited, pump 150 evacuates gases through fixture 130.
  • [0028]
    More particularly, FIG. 3 shows a flowchart 300 which illustrates an exemplary method of operating system 100. Flowchart 300 includes process blocks 202-216.
  • [0029]
    The exemplary method begins at block 302 with insertion of substrate 300 onto wafer holder 120. Execution then proceeds to block 304.
  • [0030]
    Block 304 establishes desired temperature and pressure conditions within chamber 110. In the exemplary embodiment, this entails operating heating element 126 to heat substrate 200 to a desired temperature, and operating vacuum pump 160 to establish a desired pressure. Temperature and pressure are selected based on a number of factors, including composition of the substrate and reactant gases, as well as the desired reaction. After establishing these deposition conditions, execution continues at block 306.
  • [0031]
    In block 306, the system forms or closes an inner chamber around substrate 200, or more precisely a portion of substrate 200 targeted for deposition. In the exemplary embodiment, this entails using a lever or other actuation mechanism (not shown) to move gas-distribution fixture 130 from position 138.1 to position 138.2 or to move wafer holder 120 from position 138.2 to 138.1. In either case, this movement places gas-distribution surface 132.3 one-to-five millimeters from an upper most surface of substrate 200. In this exemplary position, a lower-most surface of surface-projection member 134 contacts the upper surface of support platform 124, with the inner chamber bounded by gas-distribution surface 132.3, surface-projection member 134, and the upper surface of support platform 124.
  • [0032]
    Other embodiments define in the inner chamber in other ways. For example, some embodiments include a surface-projection member on support platform 124 of wafer holder 120 to define a cavity analogous in structure and/or function to cavity 134.1. In these embodiments, the surface-projection member takes the form of a vertical or slanted or curved wall, that extends from support platform 124 and completely around substrate 200, and the gas-distribution fixture omits a surface-projection member. However, some embodiments include one or more surface-projection members on the gas-distribution fixture and the on the support platform, with the projection members on the fixture mating, engaging, or otherwise cooperating with those on the support platform to define a substantially or effectively closed chamber. In other words, the inner chamber need not be completely closed, but only sufficiently closed to facilitate a desired deposition.
  • [0033]
    After forming the inner chamber, the exemplary method continues at block 308. Block 308 entails introducing one or more reactant or precursor gases into the separate chamber. To this end, the exemplary embodiment operates one or more mass-flow controllers, such as controllers 146 and 147, to transfer gases in controlled quantities and temporal sequences from gas sources, such as sources 144 and 147, through gas line 142 and fixture 130 into the separate chamber.
  • [0034]
    Notably, the inner chamber is smaller in volume than chamber 100 and thus requires less gas and less fill time to achieve desired chemical concentrations (assuming all other factors equal.) More precisely, the exemplary embodiment provides an inner chamber with an empty volume in the range of 70 to 350 cubic centimeters, based on a 1-to-5 millimeter inner-chamber height and a fixture with a 30-centimeter diameter. Additionally, the number and arrangement of holes in the fixture as well as the placement of the holes close to the substrate, for example within five millimeters of the substrate, promote normal gas incidence and uniform distribution of gases over the targeted portion of substrate 200.
  • [0035]
    Block 310 entails allowing the gases to react with each other and/or the heated substrate to deposit a layer of material on targeted portions of the substrate. It is expected that the resulting layer will exhibit a highly uniform thickness across the entire substrate because of the more uniform gas distribution.
  • [0036]
    Next, as block 312 shows, the exemplary method entails evacuating gaseous waste or by-products produced during the deposition. To this end, the exemplary embodiment, activates vacuum pump 160 to pump gaseous waste from the inner chamber through gas-distribution fixture 130. In some embodiments, pumps 150 and 160 are operated concurrently to establish initial pressure conditions and to evacuate the inner and outer chambers after deposition.
  • [0037]
    In block 314, the system opens the separate chamber. In the exemplary embodiment, this entails automatically or manually moving gas-distribution fixture 130 to position 138.1. Other embodiments, however, move the wafer holder or both the fixture and the wafer holder. Still other embodiments may use multipart collar or gas-confinement members which are moved laterally relative the wafer holder or gas-distribution fixture to open and close an inner chamber.
  • [0038]
    In block 316, substrate 200 is unloaded from chamber 110. Some embodiments remove the substrate manually, and others remove it using an automated wafer transport system.
  • [0039]
    FIG. 4 shows a conceptual representation of another exemplary chemical-vapor-deposition system 400 incorporating teachings of the present invention. System 400 includes a rectangular outer chamber 410 which encloses four deposition stations 420, 422, 424, and 426, loaded with respective substrates 200, 202, 204, and 206. Although the figure omits numerous components for clarity, each deposition station is structurally and operationally analogous to system 100 in FIG. 1. In the exemplary embodiment, two or more of the stations are operated in parallel. Additionally, other embodiments of this multi-station system arrange the stations in a cross formation, with each station confronting a respective lateral face of the chamber. Still other embodiments use different outer chamber geometries, for example cylindrical or spherical.
  • CONCLUSION
  • [0040]
    In furtherance of the art, the inventor has presented new systems, methods, and apparatuses for chemical-vapor deposition. One exemplary system includes an outer chamber, a substrate holder, and a unique gas-distribution fixture. The fixture includes a gas-distribution surface having holes for dispensing a gas and a gas-confinement member that engages, or otherwise cooperates with the substrate holder to form an inner chamber within the outer chamber.
  • [0041]
    Notably, the inner chamber not only consumes less gas during deposition to reduce deposition waste and cost, but also facilitates rapid filling and evacuation to reduce deposition cycle times (with all other factors being equal.) The inner chamber also places the gas-distribution fixture within several millimeters of a substrate on the substrate holder, promoting normal gas incidence across the chamber and thus uniform deposition thickness.
  • [0042]
    The embodiments described above are intended only to illustrate and teach one or more ways of practicing or implementing the present invention, not to restrict its breadth or scope. The actual scope of the invention, which embraces all ways of practicing or implementing the invention, is defined only by the following claims and their equivalents.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4894801 *Jul 24, 1987Jan 16, 1990Hitachi, Ltd.Stacked MOS transistor flip-flop memory cell
US4902533 *Jun 19, 1987Feb 20, 1990Motorola, Inc.Method for selectively depositing tungsten on a substrate by using a spin-on metal oxide
US4987089 *Jul 23, 1990Jan 22, 1991Micron Technology, Inc.BiCMOS process and process for forming bipolar transistors on wafers also containing FETs
US4993358 *Jul 28, 1989Feb 19, 1991Watkins-Johnson CompanyChemical vapor deposition reactor and method of operation
US5080928 *Oct 5, 1990Jan 14, 1992Gte Laboratories IncorporatedMethod for making moisture insensitive zinc sulfide based luminescent materials
US5084606 *May 17, 1990Jan 28, 1992Caterpillar Inc.Encapsulated heating filament for glow plug
US5089084 *Dec 3, 1990Feb 18, 1992Micron Technology, Inc.Hydrofluoric acid etcher and cascade rinser
US5177028 *Oct 22, 1991Jan 5, 1993Micron Technology, Inc.Trench isolation method having a double polysilicon gate formed on mesas
US5391911 *Apr 22, 1994Feb 21, 1995International Business Machines CorporationReach-through isolation silicon-on-insulator device
US5392245 *Aug 13, 1993Feb 21, 1995Micron Technology, Inc.Redundancy elements using thin film transistors (TFTs)
US5393704 *Dec 13, 1993Feb 28, 1995United Microelectronics CorporationSelf-aligned trenched contact (satc) process
US5483094 *Sep 26, 1994Jan 9, 1996Motorola, Inc.Electrically programmable read-only memory cell
US5483487 *Apr 24, 1995Jan 9, 1996Taiwan Semiconductor Manufacturing Comp. Ltd.Electrically programmable memory device with improved dual floating gates
US5492853 *Mar 11, 1994Feb 20, 1996Micron Semiconductor, Inc.Method of forming a contact using a trench and an insulation layer during the formation of a semiconductor device
US5495441 *May 18, 1994Feb 27, 1996United Microelectronics CorporationSplit-gate flash memory cell
US5593912 *Oct 6, 1994Jan 14, 1997International Business Machines CorporationSOI trench DRAM cell for 256 MB DRAM and beyond
US5595606 *Apr 18, 1996Jan 21, 1997Tokyo Electron LimitedShower head and film forming apparatus using the same
US5710057 *Jul 12, 1996Jan 20, 1998Kenney; Donald M.SOI fabrication method
US6013553 *Jul 15, 1998Jan 11, 2000Texas Instruments IncorporatedZirconium and/or hafnium oxynitride gate dielectric
US6020024 *Aug 4, 1997Feb 1, 2000Motorola, Inc.Method for forming high dielectric constant metal oxides
US6025627 *May 29, 1998Feb 15, 2000Micron Technology, Inc.Alternate method and structure for improved floating gate tunneling devices
US6027960 *Oct 23, 1996Feb 22, 2000Semiconductor Energy Laboratory Co., Ltd.Laser annealing method and laser annealing device
US6027961 *Jun 30, 1998Feb 22, 2000Motorola, Inc.CMOS semiconductor devices and method of formation
US6171900 *Apr 15, 1999Jan 9, 2001Taiwan Semiconductor Manufacturing CompanyCVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET
US6174809 *Dec 15, 1998Jan 16, 2001Samsung Electronics, Co., Ltd.Method for forming metal layer using atomic layer deposition
US6184146 *Jun 20, 2000Feb 6, 2001Micron Technology, Inc.Plasma producing tools, dual-source plasma etchers, dual-source plasma etching methods, and method of forming planar coil dual-source plasma etchers
US6187484 *Aug 31, 1999Feb 13, 2001Micron Technology, Inc.Irradiation mask
US6194262 *Mar 29, 2000Feb 27, 2001Micron Technology, Inc.Method for coupling to semiconductor device in an integrated circuit having edge-defined, sub-lithographic conductors
US6342445 *May 15, 2000Jan 29, 2002Micron Technology, Inc.Method for fabricating an SrRuO3 film
US6348386 *Apr 16, 2001Feb 19, 2002Motorola, Inc.Method for making a hafnium-based insulating film
US6506666 *Dec 6, 2001Jan 14, 2003Micron Technology, Inc.Method of fabricating an SrRuO3 film
US6509280 *Feb 13, 2002Jan 21, 2003Samsung Electronics Co., Ltd.Method for forming a dielectric layer of a semiconductor device
US6514348 *Jul 12, 2001Feb 4, 2003Ebara CorporationSubstrate processing apparatus
US6514828 *Apr 20, 2001Feb 4, 2003Micron Technology, Inc.Method of fabricating a highly reliable gate oxide
US6518610 *Feb 20, 2001Feb 11, 2003Micron Technology, Inc.Rhodium-rich oxygen barriers
US6518634 *Sep 1, 2000Feb 11, 2003Motorola, Inc.Strontium nitride or strontium oxynitride gate dielectric
US6521911 *Jul 19, 2001Feb 18, 2003North Carolina State UniversityHigh dielectric constant metal silicates formed by controlled metal-surface reactions
US6524867 *Dec 28, 2000Feb 25, 2003Micron Technology, Inc.Method for forming platinum-rhodium stack as an oxygen barrier
US6524901 *Jun 20, 2002Feb 25, 2003Micron Technology, Inc.Method for forming a notched damascene planar poly/metal gate
US6673701 *Aug 27, 2002Jan 6, 2004Micron Technology, Inc.Atomic layer deposition methods
US6674138 *Dec 31, 2001Jan 6, 2004Advanced Micro Devices, Inc.Use of high-k dielectric materials in modified ONO structure for semiconductor devices
US6677250 *Aug 17, 2001Jan 13, 2004Micron Technology, Inc.CVD apparatuses and methods of forming a layer over a semiconductor substrate
US6683005 *Jan 17, 2003Jan 27, 2004Micron Technology, Inc.Method of forming capacitor constructions
US6686212 *Oct 31, 2002Feb 3, 2004Sharp Laboratories Of America, Inc.Method to deposit a stacked high-κ gate dielectric for CMOS applications
US6844203 *Aug 30, 2001Jan 18, 2005Micron Technology, Inc.Gate oxides, and methods of forming
US6844260 *Jan 30, 2003Jan 18, 2005Micron Technology, Inc.Insitu post atomic layer deposition destruction of active species
US7160577 *May 2, 2002Jan 9, 2007Micron Technology, Inc.Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US7160817 *Aug 30, 2001Jan 9, 2007Micron Technology, Inc.Dielectric material forming methods
US20020001971 *Jun 27, 2001Jan 3, 2002Hag-Ju ChoMethods of manufacturing integrated circuit devices that include a metal oxide layer disposed on another layer to protect the other layer from diffusion of impurities and integrated circuit devices manufactured using same
US20020019116 *Sep 24, 2001Feb 14, 2002Sandhu Gurtej S.Chemical vapor deposition using organometallic precursors
US20020019125 *Oct 12, 2001Feb 14, 2002Werner JuenglingMethods of forming materials between conductive electrical components, and insulating materials
US20020024080 *Jun 11, 2001Feb 28, 2002Derderian Garo J.Capacitor fabrication methods and capacitor constructions
US20020025628 *Jun 14, 2001Feb 28, 2002Derderian Garo J.Capacitor fabrication methods and capacitor constructions
US20030001212 *Aug 29, 2002Jan 2, 2003Micron Technology, Inc.Conductor layer nitridation
US20030001241 *May 28, 2002Jan 2, 2003Agere Systems Guardian Corp.Semiconductor device and method of fabrication
US20030003635 *May 23, 2001Jan 2, 2003Paranjpe Ajit P.Atomic layer deposition for fabricating thin films
US20030003702 *Aug 26, 2002Jan 2, 2003Micron Technology, Inc.Formation of metal oxide gate dielectric
US20030003722 *Aug 19, 2002Jan 2, 2003Micron Technology, Inc.Chemical vapor deposition systems including metal complexes with chelating O- and/or N-donor ligands
US20030003730 *Aug 28, 2002Jan 2, 2003Micron Technology, Inc.Sequential pulse deposition
US20030004051 *Sep 5, 2001Jan 2, 2003Kim Dong-WanDielectric ceramic composition and method for manufacturing multilayered components using the same
US20030008243 *Jul 9, 2001Jan 9, 2003Micron Technology, Inc.Copper electroless deposition technology for ULSI metalization
US20030017717 *Jul 18, 2001Jan 23, 2003Ahn Kie Y.Methods for forming dielectric materials and methods for forming semiconductor devices
US20030020169 *Apr 1, 2002Jan 30, 2003Ahn Kie Y.Copper technology for ULSI metallization
US20030020180 *Jul 24, 2001Jan 30, 2003Ahn Kie Y.Copper technology for ULSI metallization
US20030027360 *Mar 28, 2001Feb 6, 2003Hsu Sheng TengSingle transistor ferroelectric transistor structure with high-K insulator and method of fabricating same
US20040004244 *Jun 20, 2003Jan 8, 2004Micron Technology, Inc.Structures, methods, and systems for ferroelectric memory transistors
US20040004245 *Jul 8, 2002Jan 8, 2004Micron Technology, Inc.Memory utilizing oxide-conductor nanolaminates
US20040004247 *Jul 8, 2002Jan 8, 2004Micron Technology, Inc.Memory utilizing oxide-nitride nanolaminates
US20040004859 *Jul 8, 2002Jan 8, 2004Micron Technology, Inc.Memory utilizing oxide nanolaminates
US20040005982 *Dec 19, 2002Jan 8, 2004Samsung Electro-Mechanics Co., Ltd.Non-reducible, low temperature sinterable dielectric ceramic composition, multilayer ceramic chip capacitor using the composition and method for preparing the multilayer ceramic chip capacitor
US20040007171 *Jul 10, 2003Jan 15, 2004Mikko RitalaMethod for growing thin oxide films
US20040009679 *Jul 10, 2003Jan 15, 2004Yeo Jae-HyunMethod of forming material using atomic layer deposition and method of forming capacitor of semiconductor device using the same
US20040023461 *Jul 30, 2002Feb 5, 2004Micron Technology, Inc.Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US20040023516 *Oct 2, 2002Feb 5, 2004Londergan Ana R.Passivation method for improved uniformity and repeatability for atomic layer deposition and chemical vapor deposition
US20040028811 *Aug 6, 2003Feb 12, 2004Young-Jin ChoBismuth titanium silicon oxide, bismuth titanium silicon oxide thin film, and method for forming the thin film
US20040033661 *Jun 2, 2003Feb 19, 2004Yeo Jae-HyunSemiconductor device and method for manufacturing the same
US20040033701 *Aug 15, 2002Feb 19, 2004Micron Technology, Inc.Lanthanide doped tiox dielectric films
US20040038554 *Aug 21, 2002Feb 26, 2004Ahn Kie Y.Composite dielectric forming methods and composite dielectrics
US20050009370 *Aug 4, 2004Jan 13, 2005Ahn Kie Y.Composite dielectric forming methods and composite dielectrics
US20050020017 *Jun 24, 2003Jan 27, 2005Micron Technology, Inc.Lanthanide oxide / hafnium oxide dielectric layers
US20050023578 *Aug 25, 2004Feb 3, 2005Micron Technology, Inc.Stable PD-SOI devices and methods
US20050023594 *Aug 31, 2004Feb 3, 2005Micron Technology, Inc.Pr2O3-based la-oxide gate dielectrics
US20050023603 *Aug 30, 2004Feb 3, 2005Micron Technology, Inc.Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators
US20050023613 *Aug 25, 2004Feb 3, 2005Micron Technology, Inc.Stable PD-SOI devices and methods
US20050023624 *Aug 31, 2004Feb 3, 2005Micron Technology, Inc.Atomic layer-deposited HfAlO3 films for gate dielectrics
US20050023625 *Aug 31, 2004Feb 3, 2005Micron Technology, Inc.Atomic layer deposited HfSiON dielectric films
US20050023626 *Aug 31, 2004Feb 3, 2005Micron Technology, Inc.Lanthanide oxide / hafnium oxide dielectrics
US20050023627 *Aug 31, 2004Feb 3, 2005Micron Technology, Inc.Lanthanide doped TiOx dielectric films by plasma oxidation
US20050026349 *Sep 1, 2004Feb 3, 2005Micron Technology, Inc.Flash memory with low tunnel barrier interpoly insulators
US20050026458 *Aug 26, 2004Feb 3, 2005Cem BasceriMethods of forming hafnium-containing materials, methods of forming hafnium oxide, and constructions comprising hafnium oxide
US20050029547 *Aug 31, 2004Feb 10, 2005Micron Technology, Inc.Lanthanide oxide / hafnium oxide dielectric layers
US20050029604 *Aug 31, 2004Feb 10, 2005Micron Technology, Inc.Atomic layer deposited Zr-Sn-Ti-O films using TiI4
US20050029605 *Aug 31, 2004Feb 10, 2005Micron Technology, Inc.Highly reliable amorphous high-k gate oxide ZrO2
US20050032292 *Aug 31, 2004Feb 10, 2005Micron Technology, Inc.Crystalline or amorphous medium-K gate oxides, Y2O3 and Gd2O3
US20050034662 *Aug 31, 2004Feb 17, 2005Micro Technology, Inc.Methods, systems, and apparatus for uniform chemical-vapor depositions
US20060001151 *Aug 26, 2005Jan 5, 2006Micron Technology, Inc.Atomic layer deposited dielectric layers
US20060003517 *Aug 29, 2005Jan 5, 2006Micron Technology, Inc.Atomic layer deposited Zr-Sn-Ti-O films using TiI4
US20060019033 *Jun 24, 2005Jan 26, 2006Applied Materials, Inc.Plasma treatment of hafnium-containing materials
US20070018214 *Jul 25, 2005Jan 25, 2007Micron Technology, Inc.Magnesium titanium oxide films
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7160577 *May 2, 2002Jan 9, 2007Micron Technology, Inc.Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US7662729Feb 16, 2010Micron Technology, Inc.Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US7670646Mar 2, 2010Micron Technology, Inc.Methods for atomic-layer deposition
US7709402Feb 16, 2006May 4, 2010Micron Technology, Inc.Conductive layers for hafnium silicon oxynitride films
US7719065Aug 29, 2005May 18, 2010Micron Technology, Inc.Ruthenium layer for a dielectric layer containing a lanthanide oxide
US7728626Sep 5, 2008Jun 1, 2010Micron Technology, Inc.Memory utilizing oxide nanolaminates
US7867919Dec 8, 2006Jan 11, 2011Micron Technology, Inc.Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer
US7915174Jul 22, 2008Mar 29, 2011Micron Technology, Inc.Dielectric stack containing lanthanum and hafnium
US8071476Dec 6, 2011Micron Technology, Inc.Cobalt titanium oxide dielectric films
US8084370Oct 19, 2009Dec 27, 2011Micron Technology, Inc.Hafnium tantalum oxynitride dielectric
US8125038Jul 11, 2005Feb 28, 2012Micron Technology, Inc.Nanolaminates of hafnium oxide and zirconium oxide
US8154066Dec 1, 2006Apr 10, 2012Micron Technology, Inc.Titanium aluminum oxide films
US8228725Jul 24, 2012Micron Technology, Inc.Memory utilizing oxide nanolaminates
US8237216Aug 7, 2012Micron Technology, Inc.Apparatus having a lanthanum-metal oxide semiconductor device
US8278225Oct 2, 2012Micron Technology, Inc.Hafnium tantalum oxide dielectrics
US8445952May 21, 2013Micron Technology, Inc.Zr-Sn-Ti-O films
US8455959Dec 5, 2011Jun 4, 2013Micron Technology, Inc.Apparatus containing cobalt titanium oxide
US8466016Dec 20, 2011Jun 18, 2013Micron Technolgy, Inc.Hafnium tantalum oxynitride dielectric
US8501563Sep 13, 2012Aug 6, 2013Micron Technology, Inc.Devices with nanocrystals and methods of formation
US8524618Sep 13, 2012Sep 3, 2013Micron Technology, Inc.Hafnium tantalum oxide dielectrics
US8541276Apr 9, 2012Sep 24, 2013Micron Technology, Inc.Methods of forming an insulating metal oxide
US8558325May 17, 2010Oct 15, 2013Micron Technology, Inc.Ruthenium for a dielectric containing a lanthanide
US8759170Jun 11, 2013Jun 24, 2014Micron Technology, Inc.Hafnium tantalum oxynitride dielectric
US8785312Nov 28, 2011Jul 22, 2014Micron Technology, Inc.Conductive layers for hafnium silicon oxynitride
US8895442Jun 3, 2013Nov 25, 2014Micron Technology, Inc.Cobalt titanium oxide dielectric films
US8907486Oct 11, 2013Dec 9, 2014Micron Technology, Inc.Ruthenium for a dielectric containing a lanthanide
US8921914Aug 5, 2013Dec 30, 2014Micron Technology, Inc.Devices with nanocrystals and methods of formation
US9175393 *Aug 31, 2011Nov 3, 2015Alta Devices, Inc.Tiled showerhead for a semiconductor chemical vapor deposition reactor
US20040043541 *Aug 29, 2002Mar 4, 2004Ahn Kie Y.Atomic layer deposited lanthanide doped TiOx dielectric films
US20040043569 *Aug 28, 2002Mar 4, 2004Ahn Kie Y.Atomic layer deposited HfSiON dielectric films
US20060001151 *Aug 26, 2005Jan 5, 2006Micron Technology, Inc.Atomic layer deposited dielectric layers
US20060246741 *Jul 17, 2006Nov 2, 2006Micron Technology, Inc.ATOMIC LAYER DEPOSITED NANOLAMINATES OF HfO2/ZrO2 FILMS AS GATE DIELECTRICS
US20070037415 *Oct 20, 2006Feb 15, 2007Micron Technology, Inc.Lanthanum hafnium oxide dielectrics
US20070049054 *Aug 31, 2005Mar 1, 2007Micron Technology, Inc.Cobalt titanium oxide dielectric films
WO2006121264A1 *May 4, 2006Nov 16, 2006Asm Genitech Korea Ltd.Multiple inlet tomic layer deposition reactor
Classifications
U.S. Classification118/715
International ClassificationC23C16/44, C23C16/455
Cooperative ClassificationC23C16/45591, C23C16/45544, C23C16/45565, C23C16/45525, C23C16/45589
European ClassificationC23C16/455F2D, C23C16/455F2, C23C16/455P4, C23C16/455P2, C23C16/455K2