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Publication numberUS20050087836 A1
Publication typeApplication
Application numberUS 10/690,995
Publication dateApr 28, 2005
Filing dateOct 22, 2003
Priority dateOct 22, 2003
Also published asCN1612339A, CN2772028Y, CN100385663C, US7332791, US20060006494
Publication number10690995, 690995, US 2005/0087836 A1, US 2005/087836 A1, US 20050087836 A1, US 20050087836A1, US 2005087836 A1, US 2005087836A1, US-A1-20050087836, US-A1-2005087836, US2005/0087836A1, US2005/087836A1, US20050087836 A1, US20050087836A1, US2005087836 A1, US2005087836A1
InventorsShien-Yang Wu
Original AssigneeTaiwan Semiconductor Manufacturing Co.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Electrically programmable polysilicon fuse with multiple level resistance and programming
US 20050087836 A1
Abstract
A method to form a programmable resistor device in an integrated circuit device is achieved. The method comprises depositing a semiconductor layer overlying a substrate. The semiconductor layer is patterned to form a plurality of lines. The lines are electrically parallel between a first terminal and a second terminal. Any of the lines may be blown open by a current forced from the first terminal to the second terminal. A metal-semiconductor alloy is selectively formed overlying a first group of the lines but not overlying a second group of the lines. A method to program the programmable resistor device is described.
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Claims(25)
1. A method to form a programmable resistor device in an integrated circuit device comprising:
forming a semiconductor layer overlying a substrate;
patterning said semiconductor layer to form a plurality of lines wherein said lines are electrically parallel between a first terminal and a second terminal and wherein any of said lines may be blown open by a current forced from said first terminal to said second terminal; and
selectively forming a metal-semiconductor alloy overlying a first group of said lines but not overlying a second group of said lines.
2. The method according to claim 1 wherein said semiconductor layer comprises silicon.
3. The method according to claim 1 wherein said semiconductor layer comprises polysilicon.
4. The method according to claim 1 wherein said programmable resistor device is a chip identifier for said integrated circuit device.
5. The method according to claim 1 wherein said metal-semiconductor alloy comprises metal silicide.
6. The method according to claim 1 wherein said step of selectively forming a metal-semiconductor alloy comprises:
forming a masking layer overlying said plurality of lines wherein said masking layer covers said second group of lines but exposes said first group of lines;
depositing a metal layer overlying said masking layer and said plurality of lines wherein said metal layer contacts said first group of lines;
annealing said metal layer to form said metal
semiconductor alloy overlying said first group of lines; and
removing unreacted said metal layer.
7. The method according to claim 1 further comprising selectively doping said plurality of lines prior to said step of selectively forming a metal-semiconductor alloy.
8. The method according to claim 5 wherein said first group of lines is doped and said second group of lines is not doped.
9. The method according to claim 1 wherein said first group comprises a single line, wherein said second group comprises more than one line, and wherein said single line comprises a smallest resistance of all of said lines.
10. A programmable resistor device in an integrated circuit device comprising:
a plurality of lines comprising a semiconductor layer overlying a substrate wherein said lines are electrically
parallel between a first terminal and a second terminal and wherein any of said lines may be blown open by a current forced from said first terminal to said second terminal; and
a metal-semiconductor alloy overlying a first group of said lines but not overlying a second group of said lines.
11. The device according to claim 10 wherein said semiconductor layer comprises silicon.
12. The device according to claim 10 wherein said semiconductor layer comprises polysilicon.
13. The device according to claim 10 wherein said programmable resistor device is a chip identifier for said integrated circuit device.
14. The device according to claim 10 wherein said metal-semiconductor alloy comprises metal silicide.
15. The device according to claim 10 wherein said plurality of lines is doped.
16. The device according to claim 10 wherein said first group of lines is doped and said second group of lines is not doped.
17. The device according to claim 10 wherein said first group comprises a single line, wherein said second group comprises more than one line, and wherein said single line comprises a smallest resistance of all of said lines.
18. A method to program a programmable resistor device wherein said device comprises:
a plurality of lines comprising a semiconductor layer overlying a substrate wherein said lines are electrically parallel between a first terminal and a second terminal and wherein any of said lines may be blown open by a current forced from said first terminal to said second terminal; and
a metal-semiconductor alloy overlying a first group of said lines but not overlying a second group of said lines wherein said device comprises a first resistance between said first and second terminals; and wherein said method comprises:
forcing a programming current from said first terminal to said second terminal wherein said programming current causes a first line in said first group to blow such that said device comprises a second resistance between said first and second terminals; and
removing said programming current.
19. The method according to claim 18 wherein said semiconductor layer comprises silicon.
20. The method according to claim 18 wherein said programmable resistor device is a chip identifier for said integrated circuit device.
21. The method according to claim 18 wherein said metal-semiconductor alloy comprises metal silicide.
22. The method according to claim 18 wherein said plurality of lines is doped.
23. The method according to claim 22 wherein said first group of lines is doped and said second group of lines is not doped.
24. The method according to claim 18 wherein said first group comprises a single line, wherein said second group comprises more than one line, and wherein said single line comprises a smallest resistance of all of said lines.
25. The method according to claim 18 further comprising:
forcing a second programming current from said first terminal to said second terminal wherein said second programming current causes one of said lines in said second group to blow such that said device comprises a third resistance between said first and second terminals; and
removing said second programming current.
Description
    BACKGROUND OF THE INVENTION
  • [0001]
    (1) Field of the Invention
  • [0002]
    The invention relates to an on-chip fuse device, and, more particularly, to an electrically programmable, polysilicon fuse with multiple level resistance.
  • [0003]
    (2) Description of the Prior Art
  • [0004]
    In the art of integrated circuits, many methods are used to provide manufacturing flexibility. Of particular importance are techniques that allow a common circuit design to be easily configured to specific applications or to parametric requirements with little or no effect on the manufacturing process. An example of a configuration method is the use of on-chip programmable fuses. A fuse is a conductive element that can be made into an open circuit. When the element is a conductor, the circuit operates according to a first configuration. When the element is open circuit, the circuit operates according to a second configuration. A typical prior art, on-chip fuse is simply a metal line. A metal line can be made an open circuit by cutting through the line using a laser. This type of fuse can be very useful. However, it requires a laser cutting source that is external to the circuit.
  • [0005]
    An alternative method to form a programmable fuse is a polysilicon line. A polysilicon line can be made an open circuit, or blown, by conducting a current through the polysilicon line that exceeds the current density capability of the material. Programmable polysilicon fuses such as this are found in the art. These fuses have a limitation, however, of only being binary devices. The fuses either are a conductive line or are an open circuit. These states may be thought of as a ‘0’ state or a ‘1’ state. It is highly advantageous to form a programmable fuse device that is capable of multiple states.
  • [0006]
    Several prior art inventions relate to on-chip fuses. U.S. Pat. No. 6,356,496 B1 to Carroll et al describes a method to form polysilicon resistors. The resistors are fuses that can be blown to adjust the value. U.S. Pat. No. 6,242,790 B1 to Tsui et al describes a method to form a variable resistance based on polysilicon resistor/fuses. U.S. Pat. No. 6,175,261 B1 to Sundaraman et al discloses an on-chip fuse circuit.
  • SUMMARY OF THE INVENTION
  • [0007]
    A principal object of the present invention is to provide an effective and very manufacturable integrated circuit device.
  • [0008]
    A further object of the present invention is to provide a method to form a programmable polysilicon fuse device capable of multiple states.
  • [0009]
    A yet further object of the present invention is to provide a method to form a programmable polysilicon fuse device with minimal impact on a CMOS process.
  • [0010]
    A yet further object of the present invention is to provide a method to form a programmable polysilicon fuse device where the state of the device depends on the parallel combination of polysilicon resistors.
  • [0011]
    A yet further object of the present invention is to provide a method to form a programmable polysilicon fuse device where the device is capable of performing in more than two states depending on how many resistors are open circuited.
  • [0012]
    A yet further object of the present invention is to provide a method to form a programmable polysilicon fuse device where the relative resistance of any resistor is controlled by the selective formation of metal silicide.
  • [0013]
    A yet further object of the present invention is to provide a method to form a programmable polysilicon fuse device where the relative resistance of any resistor is controlled by the selective doping of the resistor.
  • [0014]
    Another further object of the present invention is to provide a method to program the programmable polysilicon fuse device using on-chip current sources.
  • [0015]
    A yet further object of the present invention is to provide a method to program the programmable polysilicon fuse device that is capable of programming to more than two states using multiple pulses of current.
  • [0016]
    In accordance with the objects of this invention, a method to form a programmable resistor device in an integrated circuit device is achieved. The method comprises depositing a semiconductor layer overlying a substrate. The semiconductor layer is patterned to form a plurality of lines. The lines are electrically parallel between a first terminal and a second terminal. Any of the lines may be blown open by a current forced from the first terminal to the second terminal. A metal-semiconductor alloy is selectively formed overlying a first group of the lines but not overlying a second group of the lines.
  • [0017]
    Also in accordance with the objects of this invention, a programmable resistor device in an integrated circuit device is achieved. The device comprises a plurality of lines comprising a semiconductor layer overlying a substrate. The lines are electrically parallel between a first terminal and a second terminal. Any of the lines may be blown open by a current forced from the first terminal to the second terminal. A metal-semiconductor alloy overlies a first group of the lines but does not overlie a second group of the lines.
  • [0018]
    Also in accordance with the objects of this invention, a method to program a programmable resistor device is achieved. The device comprises a plurality of lines comprising a semiconductor layer overlying a substrate. The lines are electrically parallel between a first terminal and a second terminal. Any of the lines may be blown open by a current forced from the first terminal to the second terminal. A metal-semiconductor alloy overlies a first group of the lines but does not overlie a second group of the lines. The device comprises a first resistance between the first and second terminals. The method comprises forcing a programming current from the first terminal to the second terminal. The programming current causes a first line in the first group to blow such that the device comprises a second resistance between the first and second terminals. The programming current is then removed.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0019]
    In the accompanying drawings forming a material part of this description, there is shown:
  • [0020]
    FIG. 1 illustrates a preferred embodiment of the present invention showing a top view of a programmable resistor device.
  • [0021]
    FIGS. 2 through 6 illustrate a preferred embodiment of the present invention showing a method to form a programmable resistor device.
  • [0022]
    FIGS. 7 and 8 illustrate a preferred embodiment of the present invention showing a method to program the programmable resistor device.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0023]
    The preferred embodiments of the present invention disclose a method to form a programmable fuse device. The device is described herein. A method to program the device into more than two states is disclosed. It should be clear to those experienced in the art that the present invention can be applied and extended without deviating from the scope of the present invention.
  • [0024]
    Referring now to FIG. 1, a preferred embodiment of the present invention is illustrated. Several important features of the present invention are shown and discussed below. A top view of a programmable fuse device is shown. The device comprises a plurality of lines R1 18 a, R2 18 b, R3 18 c, and R4 18 d comprising a semiconductor layer 18 overlying a substrate. As an important feature, the lines 18 a, 18 b, 18 c, and 18 d are electrically parallel between a first terminal TERMINAL A and a second terminal TERMINAL B. Any of the lines 18 a, 18 b, 18 c, and 18 d may be blown open by a current forced from TERMINAL A to TERMINAL B.
  • [0025]
    As another important feature, a metal-semiconductor alloy overlies a first group of the lines, such as R1 18 a, but not does not overlie a second group of the lines, such as R2 18 b, R3 18 c, and R4 18 d. The metal-semiconductor alloy is selectively formed overlying the first group R1 18 a but not the second group R2 18 b, R3 18 c, and R4 18 d through the use of a metal-semiconductor mask 30 as will be further described below. By selectively forming a metal-semiconductor alloy over part of the lines, significantly different resistance values can be created. For example, if the metal-semiconductor alloy is formed overlying the R1 18 a line, as shown, then this line will exhibit a very low resistivity value. Even though the line R1 18 a is the most narrow line, the selective inclusion of the metal-semiconductor alloy makes the R1 18 a line the lowest value resistor. The resulting thin cross section of R1 18 a, coupled with the low resistance value due to the metal-semiconductor alloy, causes the R1 18 a line to be blown first when the device is subjected to a current pulse exceeding the minimum programming value as will be described below.
  • [0026]
    As another important feature, some of the lines, in this case R1 18 a, R2 18 b, and R3 18 c, are doped while other lines, in this case R4 18, are undoped. The selective doping or non-doping of lines also creates large differences in the resistivity of the lines. Undoped lines R4 18 d will have much larger resistivity values than doped lines R1 18 a, R2 18 b, and R3 18 c. The selective doping allows significantly differing resistor values to be generated. As another important feature, the widths of the lines R1 18 a, R2 18 b, R3 18 c, and R4 18 d can be made different for each line. This also allows different resistor values to be generated.
  • [0027]
    Referring now to FIGS. 2-6, the programmable fuse device is illustrated in cross section. Several important features of the present invention are shown and discussed. In particular, the key features of a preferred method of formation of the present invention are described. Referring again to FIG. 2, as a first preferred feature, a substrate 10 is provided. The substrate 10 may comprise any semiconductor material or may comprise a semiconductor on insulator (SOI) material. Preferably, the substrate 10 comprises silicon. An insulating layer 14 is shown formed overlying the substrate 10. This insulating layer 14 is shown as a shallow trench isolation 14. Alternatively, local field oxidation (LOCOS) could be used to create a non-active area.
  • [0028]
    As an important feature, a semiconductor layer 18 is formed overlying the substrate 10 and, preferably, overlying the insulating layer 14. Known semiconductor materials may be used to form the semiconductor layer 18. However, it is preferred that the semiconductor layer 18 comprises silicon and, more preferred, that the layer 18 comprises polysilicon. For example, a polysilicon layer 18 of between about 500 Å and about 2,500 Å is formed overlying the insulator layer 14. In the most preferred case, the polysilicon layer 18 comprises the same polysilicon layer used in the formation of transistor gates for CMOS devices on the integrated circuit device. In this way, the method of formation of the present invention can be performed with minimal changes to the standard production process. The polysilicon layer 18 may be deposited, for example, using a chemical vapor deposition (CVD) process.
  • [0029]
    The semiconductor layer 18 may be formed as an intrinsic layer or as a doped layer. If intrinsic, then the semiconductor layer 18 has a very low, dopant ion concentration. If doped, then the dopant ion, such as phosphorous, boron, or arsenic, concentration is sufficiently high to cause the semiconductor layer 18 to be described as n-type or p-type. If a polysilicon layer 18 is used, then this film may be deposited intrinsically or deposited with in situ doping. Alternatively, the polysilicon may be conformally doped after deposition to a desired starting concentration.
  • [0030]
    Referring now to FIG. 3, the semiconductor layer 18 is patterned to form a plurality of lines R1 18 a, R2 18 b, R3 18 c, and R4 18 d. The patterning may be performed using any of the known methods. For example, a photosensitive film, not shown, may be deposited overlying the semiconductor layer 18. The film is exposed to actinic light through a mask and then developed. The photosensitive film will expose the semiconductor layer 18 according to the pattern of the mask. The exposed semiconductor layer 18 is then etched away using the film as an on-chip mask. The photosensitive film is then stripped away. The resulting lines R1 18 a, R2 18 b, R3 18 c, and R4 18 d can be made the same width. More preferably, each line is made to a width that corresponds to the desired relative resistance of that line. The most resistive lines are made the thinnest. Likewise, by making a line wider, such as in the case of R4 18 d, that line can carry a large current density without being blown open. This feature can be optimal used to tailor the order that the lines will blow. In the example, four lines R1 18 a, R2 18 b, R3 18 c, and R4 18 d are formed. In practice, the device comprises two or more lines.
  • [0031]
    Referring now to FIG. 4, another important feature of the present invention is illustrated. As described above, the lines R1 18 a, R2 18 b, R3 18 c, and R4 18 d may be selectively doped to create optimal resistivity values for the lines. In this exemplary case, ions are implanted 26 into lines R1 18 a, R2 18 b, and R3 18 c to reduce the resistivity of these lines. A doping mask 22 is defined such that it covers the R4 18 d line and prevents the ion implantation 26 into that line 18 d. In this way, the doped group of lines R1 18 a, R2 18 b, and R3 18 c have a lower resistivity than the non-doped group of lines R4 18 d.
  • [0032]
    Referring now to FIG. 5, an important feature of the present invention is illustrated. A second masking layer 30 is formed exposing a first group of lines while covering a second group of lines. As shown, the first group of lines comprises line R1 18 a and the second group of lines comprises lines R2 18 b, R3 18 c, and R4 18 d. The second masking layer 30 preferably comprises a photosensitive or photoresist layer and may be patterned as described above. A metal layer 34 is then formed overlying the second masking layer 30 and the exposed lines R1 18 a. The metal layer 34 preferably comprises a metal that will react with the semiconductor layer 18 to form a metal-semiconductor alloy. If the semiconductor layer 18 comprises silicon or polysilicon, as is preferred, then it is also preferred that the metal layer 34 comprises cobalt, titanium, nickle, or platinum. The metal layer 34 may be formed by physical or chemical vapor deposition to a thickness of between about 10 Å and about 300 Å.
  • [0033]
    Next, the metal layer 34 and the semiconductor layer 18 are annealed to catalyze the formation of metal-semiconductor alloy on the exposed line R1 18 a. For example, the integrated circuit device may be heated to a temperature of between about 300 C. and about 800 C. Referring now to FIG. 6, a metal-semiconductor alloy layer 38 is formed only on the exposed line R1 18 a. In the preferred case, where the semiconductor layer 18 is silicon or polysilicon, the metal-semiconductor alloy layer 38 comprises a metal silicide material such as TiSi2, CoSi2, NiSi, or PtSix. The metal-semiconductor alloy layer 38 is preferably formed to a thickness of between about 10 Å and about 300 Å. Following the anneal step, the unreacted metal layer 34 is removed.
  • [0034]
    Referring again to FIG. 1, the resulting programmable fuse device is again shown in top view. As noted in the preferred embodiment of the method of formation, the lines R1 18 a, R2 18 b, R3 18 c, and R4 18 d are formed such that R1 18 a is the only line with the metal-semiconductor alloy, such that lines R1 18 a, R2 18 b, and R3 18 c are doped, and such that line R4 18 d is neither doped nor features the metal-semiconductor alloy.
  • [0035]
    In the beginning state, the resistance of the device comprises the parallel combination of the resistance of lines R1-R4. This is the first resistance of the device and represents the first stored state of the device. Note that the first state, where all the lines are connected, represents the smallest resistance of the device.
  • [0036]
    Referring now to FIG. 7, a first programming of the device is now performed. A first programming current IPROGRM1 is forced through the device from TERMINAL A to TERMINAL B. The first programming current IPROGRM1 is large enough to cause the weakest line in the device to be blown open. In this case, the weakest line is R1 18 a. R1 18 a is the weakest line for several reasons. First, the inclusion of the metal-semiconductor alloy greatly reduces the resistivity of the line. Second, line R1 is doped. Third, line R1 is the thinnest line. As a result, most of the programming current is conducted in the R1 line. When the thermal capability of the metal-semiconductor alloy layer is exceeded, this layer is blown open. At this point, the excessive current is immediately conducted in the bulk of line R1 and rapidly exceeds the thermal limit of the semiconductor layer. Therefore, line R1 is blown open as shown. The first programming current IPROGRM1 is designed to be a brief pulse that is large enough in value to blow the weakest line R1 without damaging the other lines R2-R4.
  • [0037]
    As a result of the first programming pulse, the device is programmed to the second state. In the second state, the weakest line R1 is blown open while the remaining lines R2-R4 are left connected. As a result, the device resistance is transformed to a higher value due to the absence of R1. This second resistance value corresponds to the second state of the programmable resistor device.
  • [0038]
    Referring now to FIG. 8, the programming method is repeated to program the device from the second state to the third state. A second programming current IPROGRM2 is force through the device from TERMINAL A to TERMINAL B. The current IPROGRAM2 and duration is sufficient to blow open the next weakest line R2. In this case, line R2 is a doped line. Since this line is the thinnest remaining line, the thermal ability is the least. After the R2 line is blown, the device enters the third state. The third state corresponds to a third resistance that is the parallel combination of R3 and R4. The sequence may be repeated yet a third time to blow open the R3 line 18 c and to program the device to the fourth state where the resistance of the device is merely R4.
  • [0039]
    It can be seen how the unique combination of features of the present invention creates an advantageous device. The device uses a parallel combination of a plurality of lines, the selective formation of a metal-semiconductor alloy on a first group of lines but not a second group of lines, and the selective doping of some lines yet not other lines. The resulting device is particularly useful as a programmable, or trimmable, resistance value for analog circuits. It can be used in combination with built-in self-test (BIST) or built-in self-repair (BISR) circuits. The fuse is scaleable with the prevailing technology of the integrated circuit device. Multiple logical levels may be programmed by repeating the programming pulse. The polysilicon fuse structure of the present invention consists of strips with combinations of N, P, or intrinsic dopant regions and/or silicide or non-silicide regions. This is a unique structure that differs substantially from variable resistor structures formed using variable length or width polysilicon strips.
  • [0040]
    The resulting programmable resistor device may be applied advantageously to the formation of a chip identifier for an integrated circuit device. A single such programmable resistor, or a combination of such programmable resistors, may be used to form a unique identifier for an integrated circuit device.
  • [0041]
    The advantages of the present invention may now be summarized. An effective and very manufacturable integrated circuit device is achieved. A method to form a programmable polysilicon fuse device capable of multiple states is achieved. The method of formation has minimal impact on a standard CMOS process. The method allows the state of the device to depend on the parallel combination of polysilicon resistors. The method allows the device to be capable of performing in more than two states depending on how many resistors are blown open. The method allows utilizes relative resistance of the resistor lines controlled by the selective formation of metal silicide. The method utilizes the relative resistance of the resistor lines controlled by the selective doping of the resistor. A method to program the programmable polysilicon fuse device using on-chip current sources is achieved. The method to program the programmable polysilicon fuse device is capable of programming to more than two states using multiple pulses of current.
  • [0042]
    As shown in the preferred embodiments, the novel methods and device of the present invention provide an effective and manufacturable alternative to the prior art.
  • [0043]
    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7304366 *Aug 2, 2004Dec 4, 2007Taiwan Semiconductor Manufacturing Co., Ltd.Self correcting multiple-link fuse
US7701035 *Nov 30, 2005Apr 20, 2010International Business Machines CorporationLaser fuse structures for high power applications
US7732898Feb 2, 2007Jun 8, 2010Infineon Technologies AgElectrical fuse and associated methods
US7759226Aug 30, 2005Jul 20, 2010Altera CorporationElectrical fuse with sacrificial contact
US7881093Feb 1, 2011International Business Machines CorporationProgrammable precision resistor and method of programming the same
US8003474 *Aug 15, 2008Aug 23, 2011International Business Machines CorporationElectrically programmable fuse and fabrication method
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US8378447Apr 13, 2011Feb 19, 2013International Business Machines CorporationElectrically programmable fuse and fabrication method
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US20070120232 *Nov 30, 2005May 31, 2007International Business Machines CorporationLaser fuse structures for high power applications
US20080186788 *Feb 2, 2007Aug 7, 2008Infineon Technologies AgElectrical fuse and associated methods
US20100025819 *Aug 4, 2008Feb 4, 2010International Business Machines CorporationProgrammable precision resistor and method of programming the same
US20100038747 *Aug 15, 2008Feb 18, 2010International Business Machines CorporationElectrically programmable fuse and fabrication method
US20100177548 *Jul 15, 2010Min Dong-KiMultilevel one-time programmable memory device
US20110186963 *Aug 4, 2011International Business Machines CorporationElectrically programmable fuse and fabrication method
Classifications
U.S. Classification257/529, 438/132, 257/E23.149, 257/E27.071, 438/601
International ClassificationH01L27/10, H01L23/525
Cooperative ClassificationH01L27/101, H01L2924/0002, H01L23/5256
European ClassificationH01L23/525F, H01L27/10C
Legal Events
DateCodeEventDescription
Oct 22, 2003ASAssignment
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WU, SHIEN-YANG;REEL/FRAME:014632/0053
Effective date: 20030818