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Publication numberUS20050098234 A1
Publication typeApplication
Application numberUS 10/979,885
Publication dateMay 12, 2005
Filing dateNov 3, 2004
Priority dateNov 4, 2003
Also published asUS7557018, US20060292835
Publication number10979885, 979885, US 2005/0098234 A1, US 2005/098234 A1, US 20050098234 A1, US 20050098234A1, US 2005098234 A1, US 2005098234A1, US-A1-20050098234, US-A1-2005098234, US2005/0098234A1, US2005/098234A1, US20050098234 A1, US20050098234A1, US2005098234 A1, US2005098234A1
InventorsShu Nakaharai, Tsutomu Tezuka, Shinichi Takagi
Original AssigneeShu Nakaharai, Tsutomu Tezuka, Shinichi Takagi
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Element fabrication substrate
US 20050098234 A1
Abstract
A substrate used for fabricating devices thereon includes an insulating film, and a monocrystal Ge thin layer formed on the insulating film in contact therewith, the monocrystal Ge thin layer having a thickness not more than 6 nm. The monocrystal Ge thin layer has a thickness not less than 2 nm and a compressive strain.
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Claims(15)
1. A substrate used for fabricating a device thereon, comprising:
an insulating film; and
a monocrystal Ge thin layer formed on the insulating film in contact therewith, the layer having a thickness not more than 6 nm.
2. The substrate according to claim 1, wherein the Ge thin layer has a compressive strain.
3. The substrate according to claim 1, wherein the Ge thin layer has a thickness not less than 2 nm and a compressive strain.
4. The substrate according to claim 1, wherein the monocrystal Ge thin layer is made of Si1-xGex formed on the insulating film.
5. The substrate according to claim 1, which includes a Si oxide film formed on the monocrystal Ge thin layer by oxidation.
6. The substrate according to claim 1, wherein the monocrystal Ge thin layer contains Ge composition not less than 60%.
7. A semiconductor device comprising;
an insulating film;
a monocrystal Ge thin layer formed on the insulating film and having a compressive strain and a thickness not more than 6 nm and not less than 2 nm; and
a field effect transistor using the Ge thin layer as a channel.
8. The semiconductor device according to claim 7, wherein the monocrystal Ge thin layer is made of Si1-xGex formed on the insulating film.
9. The semiconductor device according to claim 7, which includes a Si oxide film formed on the monocrystal Ge thin layer.
10. The semiconductor device according to claim 7, wherein the monocrystal Ge thin layer contains Ge composition not less than 60%.
11. A method of manufacturing a substrate used for fabricating a device thereon, comprising:
forming a monocrystal SiGe layer on a monocrystal Si layer formed on an insulating film; and
heating the monocrystal Si layer and the monocrystal SiGe layer to oxidize them for forming a Si oxide film on the monocrystal SiGe layer, and to transform the monocrystal SiGe layer to a monocrystal Ge thin layer having a thickness not more than 6 nm.
12. The method according to claim 11, wherein the monocrystal SiGe layer contains Ge composition not less than 60%, and the heating includes heating the monocrystal Si layer and the monocrystal SiGe layer at a temperature not more than a melting point of the monocrystal SiGe layer, with setting a heating temperature to a temperature exceeding 1000 C. at a time of oxidizing at first, and setting at a temperature not more than 900 C. at last while decreasing the heating temperature gradually, to form the monocrystal Ge thin layer having a compressive strain in a thickness not less than 4 nm.
13. The method according to claim 11, including setting the oxidization temperature at a temperature not more than 850 C. to form the monocrystal Ge thin layer having a compressive strain in a thickness not less than 2 nm.
14. The method according to claim 11, wherein the monocrystal Ge thin layer is made of Si1-xGex formed on the insulating film by crystal growth.
15. The method according to claim 11, wherein Ge composition in the monocrystal SiGe layer before heat treatment is set to 15%.
Description
    CROSS-REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2003-374571, filed on Nov. 4, 2003, the entire contents of which are incorporated herein by reference.
  • BACKGROUND OF THE INVENTION
  • [0002]
    The present invention relates to a substrate for device fabrication, the substrate having a monocrystal Ge thin layer for forming field effect transistors of high-performance thereon, a semiconductor device using this substrate, and a method for manufacturing the substrate.
  • [0003]
    Conventionally, a method for increasing a drive current per a unit gate length by shortening a gate length of an individual transistor and thinning a gate insulation layer is adopted for realizing high-performance/high function of CMOS circuit device. By this method, the size of a transistor to provide a necessary drive current is decreased. This makes it possible to realize a high integration, and to lower a drive voltage, resulting in decreasing a power consumption per a unit element.
  • [0004]
    However, improvement of performance required in late years increases a technical barrier to be solved for the purpose of decreasing a gate length. It is effective to use channel materials of high mobility in order to relax the circumstances. Ge is an influential candidate for the channel materials. Ge has higher mobility than Si with respect to electrons and holes. It is known that hole mobility largely increases by giving a compressive strain to Ge. In a bulk semi-conductor, hole mobility is low in comparison with electron mobility. Therefore, increase of hole mobility contributes to higher performance of a circuitry.
  • [0005]
    There is a problem that a parasitic capacitance of source and drain junctions disturbs a transistor operation which is caused by micronization of a transistor. A fully-depleted type device structure wherein a buried insulator layer is formed under a semi-conductor thin channel layer is considered in order to avoid this problem. The film thickness of the semi-conductor thin channel layer in this case is not more than about 6 nm with respect to a transistor of a gate length 25 nm, for example. If a channel is formed by a strained Ge thin film on a buried insulating layer combining the feature of a strained Ge channel and that of a fully-depleted type device structure, it is possible to fabricate a high performance transistor. However, an on-insulating film laminating strain Ge thin layer having these both features is not realized under the present circumstances.
  • [0006]
    In a document “T. Tezuka, N. Sugiyama, S. Takahi, Appl. Phys. Lett. 79, p1798 (2001)”, the inventors of the present invention proposes the Ge-condensation by oxidation method to make Ge composition in SiGe increase by oxidizing a monocrystal Si layer formed on an insulating film on a supporting substrate and a monocrystal SiGe layer containing Ge composition of about 10% which is formed on the Si layer. However, this method is a method for manufacturing a lattice-relaxed SiGe layer of high Ge composition as a substrate for a strained Si layer, unlike a method for forming a strained Ge thin layer. Further, this method does not consider thinning the film thickness of the Ge layer.
  • [0007]
    The substrate having a strained Ge thin layer on an insulating film is expected as a substrate used for making a field effect transistor with high mobility. However, a technique to form a strained Ge thin layer of extremely thin film thickness on an insulating film has not yet been realized.
  • [0008]
    The present invention is to provide a substrate for device fabrication having an extremely thin Ge layer on an insulating film.
  • BRIEF SUMMARY OF THE INVENTION
  • [0009]
    According to an aspect of the present invention, there is provided a substrate for device fabrication comprising: an insulating film; and a monocrystal Ge thin layer formed on the insulating film in contact therewith, the layer having a thickness not more than 6 nm.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
  • [0010]
    FIGS. 1A to 1D show sectional views of substrate structures in steps of substrate manufacturing according to an embodiment of the present invention;
  • [0011]
    FIG. 2 shows a temperature dependence of melting Ge composition xm(T) of Si1-xGex; and
  • [0012]
    FIG. 3 is a sectional view of an device structure of a MOSFET using the device fabrication substrate of FIG. 1.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0013]
    An embodiment of the present invention will be described referring to drawings.
  • [0014]
    FIGS. 1A to 1D illustrate sectional structures in steps of manufacturing a substrate used for fabricating devices such as transistors thereon, according to an embodiment of the present invention.
  • [0015]
    As shown in FIG. 1A, a SOI substrate 10 is prepared by forming an insulating film 12 of, for example, SiO2 on a Si substrate 11 and then forming a Si thin layer 13 on the insulating film.
  • [0016]
    As shown in FIG. 1B, Si1-xGex crystal is grown to a thickness of di (nm) with Ge composition xi on the Si thin film 13 on the insulating film Si by, for example, the CVD method to form a SiGe layer 15. In the present embodiment, assuming di=40 nm, and xi=0.15.
  • [0017]
    As shown in FIG. 1C, the substrate is subjected to thermal oxidation in oxidation ambient atmosphere. In the step of FIG. 1C, a Si oxidation film 16 is formed by oxidizing only Si in the Si thin layer 13 and SiGe layer 15. In this time, Ge is rejected from the oxide film 16 and accumulated in the SiGe layer 15, resulting in that Ge composition in the SiGe layer 15 increases. When the Ge composition in the SiGe layer 15 is not less than 60%, the oxidation temperature or heating temperature exceeding 1000 C. is desirable. This provides an effect that the Ge composition in the SiGe layer 15 is uniformized and generation of defects is suppressed, and an effect to shorten an oxidation time. The temperature must be decreased with increase of Ge composition. Finally, the oxidation temperature has to be not more than the melting temperature of Ge of 937 C.
  • [0018]
    FIG. 2 shows a relation between the Ge composition of SiGe layer and the melting temperature. It is understood from FIG. 2 that the melting temperature decreases as Ge composition increases according to progress of oxidation. The SiGe layer 15 should not be melted in order to remain a strain in the Ge thin layer that is finally obtained. Accordingly, it is understood that a temperature less than the melting temperature of SiGe but sufficiently high temperature is needed for oxidation of the SiGe layer, and the final heating temperature must be not more than 937 C.
  • [0019]
    According to the experiment of the present inventors, the final oxidation temperature must be not more than 900 C. for formation of a Ge thin layer whose thickness is 15 nm. The final oxidation temperature of 930 C. precludes formation of a high quality GOI layer having a strain. In other words, at a final oxidation temperature near the melting temperature of Ge, for example, 930 C., degradation of crystalline quality is recognized. However, a high quality single crystal was obtained at a final oxidation temperature not more than 900 C. In the case that a final film thickness of Ge layer less than 3 nm, the final oxidation temperature must be further decreased. Concretely, setting the final oxidation temperature of 850 C. for a GOI layer of a thickness less than 3 nm provides a good quality crystal.
  • [0020]
    A conventional Ge condensation by oxidation method needs to set a substrate heating temperature at a high temperature exceeding 1000 C. for the purpose of relaxing the lattice strain of the SiGe layer and uniformize a Ge composition profile. However, although the substrate heating temperature is set at a temperature exceeding 1000 C. in an initial stage, it is important to remain as much strain as possible in the SiGe layer in the final stage (Ge composition more than 80%). Therefore, in the present embodiment, the substrate heating temperature exceeding 1000 C. in the initial stage is decreased gradually to 900 C. in the final stage. The composition profile is able to be uniformized sufficiently even a low temperature not more than 900 C. (a diffusion coefficient of Si in the Ge single crystal is sufficiently large).
  • [0021]
    In this way, in the present embodiment, for fabrication of Ge layer by the Ge condensation by oxidation method, the oxidation temperature is set at a temperature exceeding 1000 C. at first, and the oxidation is done at the temperature of 900 C. at last. As a result, Ge in the SiGe layer 15 is condensed, and a pure monocrystal Ge thin layer 14 (film thickness df) is finally formed on the insulating film as shown in FIG. 1D. In this way, the monocrystal SiGe layer 15 are transformed to the monocrystal Ge thin layer 14.
  • [0022]
    In the present embodiment, a monocrystal strained Ge thin film having a strain of 1.1% and df=6 nm is formed on an insulating film. This substrate for device fabrication has a structure that a strained Ge thin film is directly in contact with a buried insulating film.
  • [0023]
    If the Ge thin layer finally formed is too thin, it is impossible to give a compression strain. According to an experiment of the inventors of the present invention, the following became clear. That is, it is impossible to give a compression strain if the Ge thin layer is thinner than 2 nm. If it is not less than 2 nm, it is possible to give a compression strain. If it is not less than 4 nm, it is possible to give a sufficient compression strain. Accordingly, the lower limit of the thickness of the Ge thin layer is 2 nm, preferably not less than 4 nm.
  • [0024]
    In a conventional method, a perfect monocrystal Ge layer on an insulating film is formed by directly transferring a thin Ge layer on another substrate. In this case, it is difficult to make the thickness of the Ge layer not more than 10 nm. However, in the present embodiment, it is possible to make the thickness of the Ge layer not more than 6 nm, e.g. about 2 nm.
  • [0025]
    Using a substrate for device fabrication as shown in FIG. 1D, a gate electrode 22 is formed via a gate insulating film 21 as shown in FIG. 3. Further, a source region 23 and a drain region 24 are formed. As a result, a high-performance MOSFET is fabricated because of high mobility of a strained Ge channel. It is possible to realize a fully-depleted type device structure having a strained Ge channel by setting the film thickness of the strained Ge thin film 14 at not more than 6 nm with a gate length of 25 nm, and therefore a MOSFET of higher performance is fabricated.
  • [0026]
    The hole mobility largely increases by giving the Ge thin layer 14 a compressive strain, and a difference between the hole mobility and the electron mobility can be reduced. This is effective when a CMOS structure is fabricated.
  • [0027]
    The present invention is not limited to the embodiment. The thickness of the monocrystal Ge thin layer is not limited to the embodiment, and may be not more than 6 nm to get performance enhancement intended by the present invention with respect to a device of a short gate length. Further, various conditions to make the thickness of the Ge thin film not less than 2 nm may be set for the Ge layer to have a sufficient strain. In addition, it is most desirable that the monocrystal Ge thin layer has a strain in the light of mobility. However, even if it has no strain, it provides an enhancement effect on mobility in comparison with Si. In this case, a range of the heating temperature of the SiGe layer, the thickness of the final Ge thin layer and so on becomes wider than in a case for forming a strained Ge thin layer.
  • [0028]
    In addition, the Ge composition in the SiGe layer before heat treatment is set to 15%. However, if the Ge density is too high, high quality single crystal is not provided. Accordingly, it is desirable that Ge composition at the time of the SiGe formation is not less than 60%. Further, a SiGe layer formation method is not limited to a CVD method, and should use a method for forming a thin SiGe layer on a Si layer in uniform and high quality.
  • [0029]
    According to the present invention, by improving an Ge condensation by oxidation method for increasing Ge composition by oxidation, a high quality monocrystal Ge thin film can be formed on an insulating film by oxidizing sufficiently a SiGe layer containing a comparatively large amount of Ge composition at a temperature less than a melting temperature of SiGe.
  • [0030]
    In particular, it is possible to make a Ge thin layer having a compressive strain by making the film thickness of the final Ge thin layer not less than about 2 nm. Fabricating MOSFET by using such a Ge thin layer allows realizing a high-performance CMOS structure.
  • [0031]
    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
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Referenced by
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US7391098 *Dec 7, 2005Jun 24, 2008Jusung Engineering Co., Ltd.Semiconductor substrate, semiconductor device and method of manufacturing the same
US7435690 *Mar 25, 2005Oct 14, 2008Commissariat A L'energie AtomiqueMethod of preparing a silicon dioxide layer by high temperature oxidation on a substrate having, at least on the surface, germanium or a silicon-germanium alloy
US7598145Jun 11, 2007Oct 6, 2009Commissariat A L 'energie AtomiqueMethod for producing Si1-yGey based zones with different contents in Ge on a same substrate by condensation of germanium
US7675115Jun 7, 2005Mar 9, 2010Kabushiki Kaisha ToshibaSemiconductor device and method for manufacturing the same
US7728324Mar 20, 2007Jun 1, 2010Kabushiki Kaisha ToshibaField effect transistor, integrated circuit element, and method for manufacturing the same
US7790540Aug 25, 2006Sep 7, 2010International Business Machines CorporationStructure and method to use low k stress liner to reduce parasitic capacitance
US7935993Dec 21, 2009May 3, 2011International Business Machines CorporationSemiconductor device structure having enhanced performance FET device
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US7985634Jan 28, 2010Jul 26, 2011Kabushiki Kaisha ToshibaSemiconductor device and method for manufacturing the same
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Classifications
U.S. Classification148/33.3, 257/E21.561, 257/E21.703, 257/E29.255, 257/65, 257/E21.411, 257/E21.324, 438/172, 257/E21.12, 257/E29.056, 257/E21.207, 257/E29.297
International ClassificationH01L21/762, H01L29/161, H01L21/205, C30B29/08, H01L21/28, H01L29/786, H01L21/336, H01L29/78, C30B3/00, H01L27/12, H01L21/20, H01L21/324, H01L29/10, H01L21/84
Cooperative ClassificationH01L21/7624, H01L21/02502, H01L21/02532, C30B3/00, H01L21/02381, H01L29/7842, H01L29/78, H01L21/324, C30B29/08, H01L29/78684, H01L21/28255, H01L29/1054, H01L29/66742, H01L21/84, H01L21/0245, H01L21/02488
European ClassificationH01L21/02K4C1A3, H01L21/02K4A1A3, H01L21/02K4B5L2, H01L21/02K4B1J, H01L21/02K4B1A3, H01L29/66M6T6F15, H01L29/78R, H01L21/324, H01L29/10D2B4, H01L21/28E3, H01L21/762D, C30B3/00, C30B29/08, H01L29/78, H01L29/786G
Legal Events
DateCodeEventDescription
Jan 18, 2005ASAssignment
Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NAKAHARAI, SHU;TEZUKA, TSUTOMU;TAKAGI, SHINICHI;REEL/FRAME:016157/0275
Effective date: 20041028