US20050101083A1 - Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing - Google Patents

Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing Download PDF

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US20050101083A1
US20050101083A1 US10/995,849 US99584904A US2005101083A1 US 20050101083 A1 US20050101083 A1 US 20050101083A1 US 99584904 A US99584904 A US 99584904A US 2005101083 A1 US2005101083 A1 US 2005101083A1
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gate
layer portion
comprised
gate layer
metal
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US10/995,849
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Chew Ang
Eng-Hua Lim
Randall Cha
Jia Zheng
Elgin Quek
Mei-Sheng Zhou
Daniel Yen
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GlobalFoundries Singapore Pte Ltd
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Chartered Semiconductor Manufacturing Pte Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Definitions

  • the present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of fabricating dual gate CMOS devices.
  • Some means to resolve these problems will be to use metal gates, in-situ p- or n-doped poly gates (minimum poly depletion effects) and high-k dielectrics.
  • the initial intention of having different work function can be accomplished by varying gate electrodes rather than changing oxide thickness.
  • U.S. Pat. No. 5,122,479 to Audet et al. describes a method of manufacturing a semiconductor device comprising a silicide layer.
  • Another object of the present invention is to provide a method of forming dual gates for CMOS devices using sputtered metal deposition of metallic ion implantation and annealing.
  • a further object of the present invention is to provide a method of forming dual gates for CMOS devices using Si implantation and annealing.
  • a substrate having a gate dielectric layer formed thereover is provided.
  • the substrate having a first gate region and a second gate region.
  • a thin first gate layer is formed over the gate dielectric layer.
  • the thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region.
  • the exposed portion of the thin first gate layer is converted to a thin third gate layer portion.
  • a second gate layer is formed over the thin first and third gate layer portions.
  • the second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.
  • FIGS. 1 to 5 schematically illustrate in cross-sectional representation a first embodiment of the present invention.
  • FIGS. 6 to 10 schematically illustrate in cross-sectional representation a second embodiment of the present invention.
  • the first embodiment extends on the replacement gate method to form the proposed dual gates.
  • a high-k dielectric gate dielectric
  • a thinner layer of poly is deposited over the gate dielectric.
  • the poly is then partially masked, preferably using either the L59, L65 or L70 mask, and the exposed poly is subjected to either a metallic ion implantation or a sputtered metal deposition.
  • a photoresist mask may be used and for a sputtered metal deposition a nitride/oxide mask, for example, is used.
  • the entire poly surface is heated, preferably by a laser treatment.
  • the portion of the poly ‘contaminated’ with metal will be transformed to silicide.
  • Another layer of either poly or metal is formed over the poly/poly-silicide layer followed by planarization, preferably by CMP, to eliminate shorts between the patterned poly gate and poly-silicide gate.
  • the poly and poly-silicide gates have different work functions.
  • FIG. 1 illustrates a cross-sectional view of a substrate 10 , preferably a semiconductor substrate comprised of silicon (Si) or germanium (Ge) and is more preferably comprised of silicon.
  • substrate 10 includes poly/silicide gate region 18 and poly gate region 20 .
  • Shallow trench isolation (STI) 12 may be formed within substrate 10 and serves to isolate the dual gates 32 , 34 to be formed on either side of STI 12 .
  • Other isolation techniques or structures may be used.
  • Gate dielectric layer 14 is formed over substrate 10 to a thickness of preferably from about 10 to 100 ⁇ and more preferably from about 10 to 20 ⁇ .
  • Gate dielectric layer 14 is preferably comprised of grown oxide or a high-k dielectric material, i.e. having a dielectric constant of greater than about 3.0, and is more preferably comprised of grown oxide.
  • Thin first gate layer 16 is then formed over gate dielectric layer 14 to a thickness of preferably from about 100 to 800 ⁇ and more preferably from about 200 to 500 ⁇ .
  • First gate layer 16 is preferably comprised of polysilicon (poly), amorphous silicon or alpha ( ⁇ )-silicon and is more preferably comprised of poly.
  • masking layer 22 is formed over first poly layer 16 within poly gate region 20 leaving first poly layer 16 within poly/silicide gate region 18 exposed.
  • the L59, L65 or L70 mask may be used with masking layer 22 preferably formed of photoresist.
  • a metallic ion implantation 24 is then conducted into the exposed first poly layer 16 within poly/silicide gate region 18 to a preferably concentration of from about 1E16 to 1E20 atoms/cm 3 and more preferably from about 1E17 to 1E19 atoms/cm 3 .
  • germanium may be implanted 24 into exposed first poly layer 16 within poly/silicide gate region 18 to a preferably concentration of from about 1E16 to 1E20 atoms/cm 3 and more preferably from about 1E17 to 1E19 atoms/cm 3 . This forms first poly/germanium layer portion 16 ′.
  • a metal deposition 24 may be conducted, preferably by a sputtered metal deposition, to form a thin layer of metal 25 shown in dashed line. If a sputtered metal deposition 24 is chosen, then mask 22 is comprised of a nitride/oxide layer. In this option layers 16 ′, 16 ′′ are each still comprised of poly.
  • Germanium may also be implanted as at 24 .
  • mask 22 is removed, preferably by a photoresist stripping process, and the structure is cleaned, preferably by a CRS cleaning process. Any metal 25 deposited over mask 22 is removed by an etch-back or a wet clean process.
  • the structure is then annealed, preferably by a laser anneal 28 (die by die, scanning or rastering) to heat at least the first poly/metal layer portion 16 ′ to form metal silicide layer portion 26 by the reaction of the poly and metal within first poly/metal layer portion 16 ′.
  • a laser anneal 28 die by die, scanning or rastering
  • a thin metal layer 25 was formed over poly layer 16 ′ instead of using an ion implantation 24 , then when the structure is annealed, preferably by a laser anneal 28 (die by die, scanning or rastering), at least the first poly layer 16 ′ and thin metal layer 25 are heated to form metal silicide layer portion 26 by the reaction of the poly within first poly layer 16 ′ and the overlying metal layer 25 .
  • a laser anneal 28 die by die, scanning or rastering
  • second gate layer 30 is formed over first gate layer portion 16 ′′ (metal silicide layer portion 26 and first poly layer portion 16 ′′) to a thickness of from about 1000 to 2000 ⁇ and more preferably from about 1000 to 1500 ⁇ .
  • Second gate layer 30 is preferably either: a polysilicon (poly) layer; or a metal layer that is comprised of tungsten or tungsten silicate and more preferably comprised of poly.
  • Second gate layer 30 and the first gate layer are then patterned to form poly/silicide gate 32 within poly/silicide gate region 18 and poly gate 34 within poly gate region 20 .
  • Second gate layer 30 and the first gate layer may be patterned through the use of an L60 gate etch for example.
  • the second embodiment also extends on the replacement gate method to form the proposed dual gates.
  • a high-k dielectric gate dielectric
  • a thinner layer of metal is deposited over the gate dielectric.
  • the metal is then partially masked, preferably using either the L65 or L70 mask, and the exposed metal is subjected to a silicon (Si) implantation.
  • Si silicon
  • the entire metal surface is heated, preferably by a laser treatment.
  • the portion of the metal ‘contaminated’ with silicon will be transformed to silicide.
  • Another layer of the same metal may formed over the metal/metal-silicide layer followed by planarization, preferably by CMP, to eliminate shorts between the patterned metal gate and metal-silicide gate.
  • the metal and metal-silicide gates have different work functions.
  • FIG. 6 illustrates a cross-sectional view of a substrate 110 , preferably a semiconductor substrate comprised of silicon (Si) or germanium (Ge) and is more preferably comprised of silicon.
  • substrate 110 includes metal/silicide gate region 118 and metal gate region 120 .
  • Shallow trench isolation (STI) 112 may be formed within substrate 110 and serves to isolate the dual gates 132 , 134 to be formed on either side of STI 112 .
  • Other isolation techniques or structures may be used.
  • Gate dielectric layer 114 is formed over substrate 110 to a thickness of preferably from about 10 to 100 ⁇ and more preferably from about 10 to 20 ⁇ .
  • Gate dielectric layer 114 is preferably comprised of grown oxide or a high-k dielectric material, i.e. having a dielectric constant of greater than about 3.0, and is more preferably comprised of grown oxide.
  • Thin first gate layer 116 is then formed over gate dielectric layer 114 to a thickness of preferably from about 100 to 800 ⁇ and more preferably from about 200 to 500 ⁇ .
  • First gate layer 116 is preferably comprised of a metal such as tungsten (W), tantalum (Ta), molybdenum (Mo) or germanium (Ge) and is more preferably comprised of a metal such as tungsten (W).
  • masking layer 122 is formed over first metal layer 116 within metal gate region 120 leaving first metal layer 116 within metal/silicide gate region 118 exposed.
  • the L59, L65 or L70 mask may be used with masking layer 122 preferably formed of photoresist.
  • a silicon implantation 124 is then conducted into the exposed first metal layer 16 within metal/silicide gate region 118 to a preferably concentration of from about 1E16 to 1E20 Si atoms/cm 3 and more preferably from about 1E17 to 1E19 Si atoms/cm 3 . This forms first metal/Si layer portion 116 ′.
  • a silicon implantation 124 is conducted into the exposed first germanium layer 116 within metal/silicide gate region 118 to a preferably concentration of from about 1E16 to 1E20 Si atoms/cm 3 and more preferably from about 1E17 to 1E19 Si atoms/cm 3 . This forms first germanium/Si layer portion 116 ′.
  • mask 122 is removed, preferably by a photoresist stripping process, and the structure is cleaned, preferably by a CRS cleaning process.
  • the structure is then annealed, preferably by a laser anneal 128 (die by die, scanning or rastering) to heat at least the first metal/Si layer portion 116 ′ to form metal silicide layer portion 126 by the reaction of the metal and silicon within first metal/Si layer portion 116 ′.
  • a laser anneal 128 die by die, scanning or rastering
  • portion 116 ′ is comprised of germanium/Si
  • the annealing forms germanium silicide layer portion 126 by the reaction of the germanium and silicon within first germanium/Si layer portion 116 ′.
  • second gate layer 130 is formed over first gate layer portion 116 (metal silicide layer portion 126 and first metal layer portion 116 ′′) to a thickness of from about 1000 to 2000 ⁇ and more preferably from about 1000 to 1500 ⁇ .
  • Second gate layer 130 is preferably either: a metal layer that is comprised of tungsten (W), tantalum (Ta) or molybdenum (Mo); or a polysilicon (poly) layer. Second gate layer 130 is more preferably comprised of a metal.
  • Second gate layer 130 and the first gate layer are then patterned to form metal/silicide gate 132 within metal/silicide gate region 118 and metal gate 134 within metal gate region 120 .
  • Second gate layer 130 and the first gate layer may be patterned through the use of an L60 gate etch for example.

Abstract

A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.

Description

    FIELD OF THE INVENTION
  • The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of fabricating dual gate CMOS devices.
    • BACKGROUND OF THE INVENTION
  • The evolution of dual gate technology in integrated circuit (IC) devices has evolved from having doped polycrystalline gates resting on different gate oxide thicknesses to introduction of different metal gates lying over high k dielectrics. Owing to an alteration in work function from the changing oxide thickness and different metals, devices on the same chip can operate by different voltages. However, the polycrystalline gates can suffer from depletion effects as oxides grow thinner, especially for the case of implanted n-doped gates. For the thinner oxides, reliability and integrity also pose serious concerns.
  • Some means to resolve these problems will be to use metal gates, in-situ p- or n-doped poly gates (minimum poly depletion effects) and high-k dielectrics. Preferably, the initial intention of having different work function can be accomplished by varying gate electrodes rather than changing oxide thickness.
  • U.S. Pat. No. 5,236,872 to van Ommen et al. describes a process of forming a silicide layer in a poly layer by a metal ion implantation (I/I) and anneal.
  • U.S. Pat. No. 6,043,157 to Gardner et al. describes a process of forming a semiconductor device having dual gate electrode material.
  • U.S. Pat. No. 5,122,479 to Audet et al. describes a method of manufacturing a semiconductor device comprising a silicide layer.
  • U.S. Pat. No. 6,087,236 to Chau et al. describes a method of making an integrated circuit with multiple gate dielectric structures.
    • SUMMARY OF THE INVENTION
  • Accordingly, it is an object of the present invention to provide a method of forming dual gates for CMOS devices using implantation and annealing processes.
  • Another object of the present invention is to provide a method of forming dual gates for CMOS devices using sputtered metal deposition of metallic ion implantation and annealing.
  • A further object of the present invention is to provide a method of forming dual gates for CMOS devices using Si implantation and annealing.
  • Other objects will appear hereinafter.
  • It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The features and advantages of the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:
  • FIGS. 1 to 5 schematically illustrate in cross-sectional representation a first embodiment of the present invention.
  • FIGS. 6 to 10 schematically illustrate in cross-sectional representation a second embodiment of the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Unless otherwise specified, all structures, layers, etc. may be formed or accomplished by conventional methods known in the prior art.
    • FIRST EMBODIMENT
  • Summary of the First Embodiment
  • The first embodiment extends on the replacement gate method to form the proposed dual gates. After the nitride gate removal, a high-k dielectric (gate dielectric) is deposited. Instead of a whole doped poly deposition as done in a conventional replacement gate process, a thinner layer of poly is deposited over the gate dielectric. The poly is then partially masked, preferably using either the L59, L65 or L70 mask, and the exposed poly is subjected to either a metallic ion implantation or a sputtered metal deposition. It is noted that for a metallic ion implantation, a photoresist mask may be used and for a sputtered metal deposition a nitride/oxide mask, for example, is used. Upon removal of the mask, the entire poly surface is heated, preferably by a laser treatment. The portion of the poly ‘contaminated’ with metal will be transformed to silicide. Another layer of either poly or metal is formed over the poly/poly-silicide layer followed by planarization, preferably by CMP, to eliminate shorts between the patterned poly gate and poly-silicide gate. The poly and poly-silicide gates have different work functions.
  • Initial Structure
  • FIG. 1 illustrates a cross-sectional view of a substrate 10, preferably a semiconductor substrate comprised of silicon (Si) or germanium (Ge) and is more preferably comprised of silicon. Substrate 10 includes poly/silicide gate region 18 and poly gate region 20.
  • Shallow trench isolation (STI) 12 may be formed within substrate 10 and serves to isolate the dual gates 32, 34 to be formed on either side of STI 12. Other isolation techniques or structures may be used.
  • Gate dielectric layer 14 is formed over substrate 10 to a thickness of preferably from about 10 to 100 Å and more preferably from about 10 to 20 Å. Gate dielectric layer 14 is preferably comprised of grown oxide or a high-k dielectric material, i.e. having a dielectric constant of greater than about 3.0, and is more preferably comprised of grown oxide.
  • Thin first gate layer 16 is then formed over gate dielectric layer 14 to a thickness of preferably from about 100 to 800 Å and more preferably from about 200 to 500 Å. First gate layer 16 is preferably comprised of polysilicon (poly), amorphous silicon or alpha (α)-silicon and is more preferably comprised of poly.
  • Ion Implantation or Metal Deposition
  • As shown in FIG. 2, masking layer 22 is formed over first poly layer 16 within poly gate region 20 leaving first poly layer 16 within poly/silicide gate region 18 exposed. For example the L59, L65 or L70 mask may be used with masking layer 22 preferably formed of photoresist.
  • I. A metallic ion implantation 24 is then conducted into the exposed first poly layer 16 within poly/silicide gate region 18 to a preferably concentration of from about 1E16 to 1E20 atoms/cm3 and more preferably from about 1E17 to 1E19 atoms/cm3. This forms first poly/metal layer portion 16′. Instead of metallic ions, germanium may be implanted 24 into exposed first poly layer 16 within poly/silicide gate region 18 to a preferably concentration of from about 1E16 to 1E20 atoms/cm3 and more preferably from about 1E17 to 1E19 atoms/cm3. This forms first poly/germanium layer portion 16′.
  • II. Alternatively, a metal deposition 24 may be conducted, preferably by a sputtered metal deposition, to form a thin layer of metal 25 shown in dashed line. If a sputtered metal deposition 24 is chosen, then mask 22 is comprised of a nitride/oxide layer. In this option layers 16′, 16″ are each still comprised of poly.
  • Preferably, a metallic ion implantation or sputtered metal deposition is conducted. Germanium may also be implanted as at 24.
  • Formation of Metal Silicide Portion 26
  • As shown in FIG. 3, mask 22 is removed, preferably by a photoresist stripping process, and the structure is cleaned, preferably by a CRS cleaning process. Any metal 25 deposited over mask 22 is removed by an etch-back or a wet clean process.
  • I. The structure is then annealed, preferably by a laser anneal 28 (die by die, scanning or rastering) to heat at least the first poly/metal layer portion 16′ to form metal silicide layer portion 26 by the reaction of the poly and metal within first poly/metal layer portion 16′.
  • II. If a thin metal layer 25 was formed over poly layer 16′ instead of using an ion implantation 24, then when the structure is annealed, preferably by a laser anneal 28 (die by die, scanning or rastering), at least the first poly layer 16′ and thin metal layer 25 are heated to form metal silicide layer portion 26 by the reaction of the poly within first poly layer 16′ and the overlying metal layer 25.
  • Formation of Second Gate Layer 30
  • As shown in FIG. 5, second gate layer 30 is formed over first gate layer portion 16″ (metal silicide layer portion 26 and first poly layer portion 16″) to a thickness of from about 1000 to 2000 Å and more preferably from about 1000 to 1500 Å. Second gate layer 30 is preferably either: a polysilicon (poly) layer; or a metal layer that is comprised of tungsten or tungsten silicate and more preferably comprised of poly.
  • Patterning of First and Second Gate Layers 26, 16″; 30 to Form Poly/Silicide Gate 32 and Poly Gate 34
  • Second gate layer 30 and the first gate layer (comprised of metal silicide layer portion 26 and first gate layer portion 16″) are then patterned to form poly/silicide gate 32 within poly/silicide gate region 18 and poly gate 34 within poly gate region 20. Second gate layer 30 and the first gate layer may be patterned through the use of an L60 gate etch for example.
    • SECOND EMBODIMENT
  • Summary of the Second Embodiment
  • The second embodiment also extends on the replacement gate method to form the proposed dual gates. After the nitride gate removal, a high-k dielectric (gate dielectric) is deposited. Instead of a whole metal deposition as done in a conventional replacement gate process, a thinner layer of metal is deposited over the gate dielectric. The metal is then partially masked, preferably using either the L65 or L70 mask, and the exposed metal is subjected to a silicon (Si) implantation. Upon removal of the mask, the entire metal surface is heated, preferably by a laser treatment. The portion of the metal ‘contaminated’ with silicon will be transformed to silicide. Another layer of the same metal may formed over the metal/metal-silicide layer followed by planarization, preferably by CMP, to eliminate shorts between the patterned metal gate and metal-silicide gate. The metal and metal-silicide gates have different work functions.
  • Initial Structure
  • FIG. 6 illustrates a cross-sectional view of a substrate 110, preferably a semiconductor substrate comprised of silicon (Si) or germanium (Ge) and is more preferably comprised of silicon. Substrate 110 includes metal/silicide gate region 118 and metal gate region 120.
  • Shallow trench isolation (STI) 112 may be formed within substrate 110 and serves to isolate the dual gates 132, 134 to be formed on either side of STI 112. Other isolation techniques or structures may be used.
  • Gate dielectric layer 114 is formed over substrate 110 to a thickness of preferably from about 10 to 100 Å and more preferably from about 10 to 20 Å. Gate dielectric layer 114 is preferably comprised of grown oxide or a high-k dielectric material, i.e. having a dielectric constant of greater than about 3.0, and is more preferably comprised of grown oxide.
  • Thin first gate layer 116 is then formed over gate dielectric layer 114 to a thickness of preferably from about 100 to 800 Å and more preferably from about 200 to 500 Å. First gate layer 116 is preferably comprised of a metal such as tungsten (W), tantalum (Ta), molybdenum (Mo) or germanium (Ge) and is more preferably comprised of a metal such as tungsten (W).
  • Silicon Implantation
  • As shown in FIG. 7, masking layer 122 is formed over first metal layer 116 within metal gate region 120 leaving first metal layer 116 within metal/silicide gate region 118 exposed. For example the L59, L65 or L70 mask may be used with masking layer 122 preferably formed of photoresist.
  • A silicon implantation 124 is then conducted into the exposed first metal layer 16 within metal/silicide gate region 118 to a preferably concentration of from about 1E16 to 1E20 Si atoms/cm3 and more preferably from about 1E17 to 1E19 Si atoms/cm3. This forms first metal/Si layer portion 116′.
  • If layer 116 is comprised of germanium, a silicon implantation 124 is conducted into the exposed first germanium layer 116 within metal/silicide gate region 118 to a preferably concentration of from about 1E16 to 1E20 Si atoms/cm3 and more preferably from about 1E17 to 1E19 Si atoms/cm3. This forms first germanium/Si layer portion 116′.
  • Formation of Silicide Portion 126
  • As shown in FIG. 8, mask 122 is removed, preferably by a photoresist stripping process, and the structure is cleaned, preferably by a CRS cleaning process.
  • The structure is then annealed, preferably by a laser anneal 128 (die by die, scanning or rastering) to heat at least the first metal/Si layer portion 116′ to form metal silicide layer portion 126 by the reaction of the metal and silicon within first metal/Si layer portion 116′.
  • If portion 116′ is comprised of germanium/Si, then the annealing forms germanium silicide layer portion 126 by the reaction of the germanium and silicon within first germanium/Si layer portion 116′.
  • Formation of Second Gate Layer 130
  • As shown in FIG. 9, second gate layer 130 is formed over first gate layer portion 116 (metal silicide layer portion 126 and first metal layer portion 116″) to a thickness of from about 1000 to 2000 Å and more preferably from about 1000 to 1500 Å. Second gate layer 130 is preferably either: a metal layer that is comprised of tungsten (W), tantalum (Ta) or molybdenum (Mo); or a polysilicon (poly) layer. Second gate layer 130 is more preferably comprised of a metal.
  • Patterning of First and Second Gate Layers 126, 116″; 130 to Form Metal/Silicide Gate 132 and Metal Gate 134
  • Second gate layer 130 and the first gate layer (comprised of metal silicide layer portion 126 and first gate metal layer portion 116″) are then patterned to form metal/silicide gate 132 within metal/silicide gate region 118 and metal gate 134 within metal gate region 120. Second gate layer 130 and the first gate layer may be patterned through the use of an L60 gate etch for example.
  • Advantages of the Invention
  • The advantages of the present invention include:
      • 1) dual work function to optimize threshold voltage for a NMOSFET and PMOSFET, respectively;
      • 2) no poly depletion for NMOSFET and PMOSFET; and
      • 3) no boron penetration issue is PMOSFET.
  • While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.

Claims (23)

1. A method of fabricating first and second gates, comprising the steps of:
providing a substrate having a gate dielectric layer formed thereover; the substrate having a first gate region and a second gate region;
forming a thin first gate layer over the gate dielectric layer;
masking the thin first gate layer within the second gate region to expose a portion of the thin first gate layer within the first gate region;
converting the exposed portion of the thin first gate layer to a thin third gate layer portion;
forming a second gate layer over the thin first and third gate layer portions;
patterning the second gate layer and the first and third gate layer portions to form a first gate within first gate region and a second gate within second gate region.
2-37. (canceled)
38. A dual gate structure, comprising:
a substrate having a gate dielectric layer formed thereover; the substrate having a first gate region and a second gate region each over a non-implanted portion of the substrate;
a first gate over the gate dielectric layer within the first gate region; the first gate comprising a lower implanted first-gate layer portion and an upper first-gate layer portion; and
a second gate over the gate dielectric layer within the second gate region; the second gate comprising a lower non-implanted second-gate layer portion and an upper second-gate layer portion.
39. The structure of claim 38, wherein the substrate is comprised of silicon or germanium; the gate dielectric layer is comprised of grown oxide or a dielectric material having a dielectric constant of greater than about 3.0; the lower implanted first-gate layer portion is comprised of metal silicide or germanium silicide; the lower non-implanted second-gate layer portion is comprised of poly or amorphous silicon; and the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly or a metal.
40. The structure of claim 38, wherein the substrate is comprised of silicon; the gate dielectric layer is comprised of grown oxide; the lower implanted first-gate layer portion is comprised of metal silicide or germanium silicide; the lower non-implanted second-gate layer portion is comprised of poly or alpha-silicon; and the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly or alpha-silicon.
41. The structure of claim 38, wherein the gate dielectric layer is from about 10 to 100 Å thick; the lower implanted first-gate layer portion and lower non-implanted second-gate layer portion are each from about 100 to 800 Å thick; and the upper first-gate layer portion and upper second-gate layer portion are each from about 1000 to 1500 Å thick.
42. The structure of claim 38, wherein the gate dielectric layer is from about 10 to 20 Å thick; the lower implanted first-gate layer portion and lower non-implanted second-gate layer portion are each from about 200 to 500 Å thick; and the upper first-gate layer portion and upper second-gate layer portion are each from about 1000 to 1500 Å thick.
43. The structure of claim 38, including an isolation structure within the substrate, dividing the first and second gate regions.
44. The structure of claim 38, including a shallow trench isolation structure (STI) within the substrate, dividing the first and second gate regions.
45. The structure of claim 38, wherein the first gate is a poly/metal silicide stack; a poly/germanium silicide stack; a metal/metal silicide stack; or a metal/germanium silicide stack.
46. The structure of claim 38, wherein the lower implanted first-gate layer portion is comprised of germanium silicate, tungsten silicate, tantalum silicate or molybdenum silicate; the lower non-implanted second-gate layer portion is comprised of germanium, tungsten, tantalum or molybdenum; the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly, tungsten, tantalum, molybdenum or tungsten silicate.
47. The structure of claim 38, wherein the substrate is comprised of silicon; the gate dielectric layer is comprised of grown oxide; the lower implanted first-gate layer portion is comprised of tungsten silicate; the lower non-implanted second-gate layer portion is comprised of tungsten; and the upper first-gate layer portion and upper second-gate layer portion are each comprised of a metal.
48. The structure of claim 38, wherein the upper first-gate layer portion and upper second-gate layer portion are each comprised of a metal silicide or germanium silicide.
49. A dual gate structure, comprising:
a silicon or germanium substrate having a gate dielectric layer formed thereover; the substrate having a first gate region and a second gate region each over a non-implanted portion of the substrate; the gate dielectric layer being comprised of grown oxide or a dielectric material having a dielectric constant of greater than about 3.0;
a first gate over the gate dielectric layer within the first gate region; the first gate comprising a lower implanted first-gate layer portion and an upper first-gate layer portion; and
a second gate over the gate dielectric layer within the second gate region; the second gate comprising a lower non-implanted second-gate layer portion and an upper second-gate layer portion.
50. The structure of claim 49, wherein; the gate dielectric layer is comprised of grown oxide; the lower implanted first-gate layer portion is comprised of metal silicide or germanium silicide; the lower non-implanted second-gate layer portion is comprised of poly or amorphous silicon; and the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly or a metal.
51. The structure of claim 49, wherein the substrate is comprised of silicon; the gate dielectric layer is comprised of grown oxide; and the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly.
52. The structure of claim 49, wherein the gate dielectric layer is from about 10 to 100 Å thick; the lower implanted first-gate layer portion and the lower non-implanted second-gate layer portion are each from about 100 to 800 Å thick; and the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly or a metal are each from about 1000 to 2000 Å thick.
53. The structure of claim 49, wherein the gate dielectric layer is from about 10 to 20 Å thick; the lower implanted first-gate layer portion and the lower non-implanted second-gate layer portion are each from about 200 to 500 Å thick; and the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly or a metal are each from about 1000 to 1500 Å thick.
54. The structure of claim 49, including an isolation structure within the substrate, dividing the first and second gate regions.
55. The structure of claim 49, including a shallow trench isolation structure (STI) within the substrate, dividing the first and second gate regions.
56. The structure of claim 49, wherein the lower implanted first-gate layer portion is formed of metal silicide or germanium silicide.
57. The structure of claim 49, wherein the first gate is a poly/metal silicide stack; a poly/germanium silicide stack; a metal/metal silicide stack; or a metal/germanium silicide stack.
58. The structure of claim 49, wherein the upper first-gate layer portion and upper second-gate layer portion are each comprised of poly, tungsten, tantalum, molybdenum or tungsten silicate.
US10/995,849 2003-01-08 2004-11-23 Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing Abandoned US20050101083A1 (en)

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