|Publication number||US20050130407 A1|
|Application number||US 10/733,814|
|Publication date||Jun 16, 2005|
|Filing date||Dec 12, 2003|
|Priority date||Dec 12, 2003|
|Also published as||US7285489, US20050142853|
|Publication number||10733814, 733814, US 2005/0130407 A1, US 2005/130407 A1, US 20050130407 A1, US 20050130407A1, US 2005130407 A1, US 2005130407A1, US-A1-20050130407, US-A1-2005130407, US2005/0130407A1, US2005/130407A1, US20050130407 A1, US20050130407A1, US2005130407 A1, US2005130407A1|
|Original Assignee||Jui-Neng Tu|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (2), Classifications (23), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to a dual damascene process and structure, and more particularly to a dual damascene process for forming a multi-layer low-k dielectric interconnect.
Due to the rapid development of integrated circuit (IC) process, the components in an IC are shrunk to attain high density. For the high density and shrinkage, it is required more advanced wiring structure and new materials for better transmission performance. Thus, copper-based conductor is employed to replace the traditional aluminum wiring. High density of IC increases difficulties to the process and therefore, dual damascene process and structure is developed to simplify the fabrication work.
In general, dual damascene process may reduce overall fabrication steps and copper-based conductor may effectively lower the resistance of wiring. However, in an extremely high density IC, formation of dual damascene interconnect with Cu process still faces high RC delay due to high dielectric constant of the inter-layer dielectric (ILD), and delay of the IC in operation arises. Therefore, low-k dielectric is proposed to resolve the problem of such delay.
Utilization of low-k material for ILD may lower the effective dielectric constant of dual damascene interconnect. In U.S. Pat. No. 6,100,184 issued to Zhao et al., for instance, two low-k dielectric layers and an etch-stop dielectric layer inserted therebetween are deposited at first, and then the two low-k dielectric layers are etched to form dual damascene vias to fill Cu plugs therewith. However, this method of lowering the dielectric constant has its limitation. One of the reasons is that the dielectric constant of the aforementioned etch-stop dielectric layer is higher and this boosts up the total dielectric constant. Another reason for this is that no material of lower dielectric constant may be applied to this process. Kitch had proposed another dual damascene process in U.S. Pat. No. 6,143,641, by which method the original dielectric layer is removed after Cu dual damascene plugs are formed in the dielectric layer to fill another low-k dielectric layer to replace the original dielectric layer. Even though further lowering the effective dielectric constant, this process complicates the process as well and likewise, much lower dielectric constant material may not be applied in this process.
Among various low-k dielectric materials, the dielectric constant of fluorinated silicate glass (e.g., FSG) is about 3.5, CVD oxide (e.g., SiOC) is ranged between 2.5 and 3, and spin-on dielectric has a lowest one and smaller than 2.5. Conventional dual damascene process utilizing dielectric materials with dielectric constant between 2.5 and 3 have touched the limit of lowering effective dielectric constant. Therefore, other materials with much lower dielectric constant must be adopted to further reduce the total dielectric constant. Unfortunately, spin-on low-k dielectric having dielectric constant lower than 2.5 is difficult to apply to large area, uniform or thicker deposition and hence, is not suitable for current dual damascene process. In the process, spin-on low-k dielectrics are difficult to control and are only suitable for trench filling. If spin-on low-k dielectrics are employed to replace the conventional dual damascene dielectrics, the yield will be lowered. In other words, conventional dual damascene processes cannot make good use of spin-on low-k dielectrics to lower the effective dielectric constant of dual damascene interconnects. Therefore, it is desired a modified process to utilize spin-on low-k dielectrics to lower the effective dielectric constant of dual damascene interconnects.
One object of the present invention is to propose a process of forming a multi-layer Cu dual damascene interconnect to lower the effective dielectric constant thereof and thereby reduce the speed delay of the IC employing the multi-layer Cu dual damascene interconnect.
In a dual damascene process for forming a multi-layer low-k dielectric interconnect, according to the present invention, a low-k dielectric layer is deposited on a substrate by CVD and then etched to form a plurality of dual damascene vias, a barrier layer is formed to cover the low-k dielectric layer as well as the exposed surface of the substrate, each dual damascene via is filled with a Cu conductor plug, a second barrier layer is formed to cover on the top of the Cu conductor plugs, the low-k dielectric layer is etched to form trenches between the dual damascene vias, and a spin-on low-k dielectric layer is applied to fill in the trenches.
These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:
As shown in
Next, as shown in
The principle and features of the inventive dual damascene process are described below. CVD is used at first to form the large area and uniform dielectric 10 to the desired thickness, whose dielectric constant is between 2.5 and 3. After the Cu conductor plugs 18 are performed, some parts of the dielectric layer 10 are removed and become thinner thereof. The removed space, i.e., the trenches 22, is filled with spin-on low-k dielectric instead. Thus, the total or equivalent dielectric constant of the resulted ILD is lowered and high yield is maintained.
Repeating the aforementioned steps will obtain a multi-layer dual damascene interconnect. As shown in
While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6605545 *||Jun 1, 2001||Aug 12, 2003||United Microelectronics Corp.||Method for forming hybrid low-K film stack to avoid thermal stress effect|
|US6664641 *||Oct 2, 2002||Dec 16, 2003||Mitsubishi Denki Kabushiki Kaisha||Wiring structure for an integrated circuit|
|US6756321 *||Oct 5, 2002||Jun 29, 2004||Taiwan Semiconductor Manufacturing Co., Ltd||Method for forming a capping layer over a low-k dielectric with improved adhesion and reduced dielectric constant|
|US6794293 *||Oct 5, 2001||Sep 21, 2004||Lam Research Corporation||Trench etch process for low-k dielectrics|
|US20040080050 *||Mar 27, 2003||Apr 29, 2004||Lam Research Corporation||Method and apparats for detecting endpoint during plasma etching of thin films|
|US20040094839 *||Nov 14, 2002||May 20, 2004||International Business Machines Corporation||Reliable low-k interconnect structure with hybrid dielectric|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7348272 *||Aug 3, 2005||Mar 25, 2008||United Microelectronics Corp.||Method of fabricating interconnect|
|US7651941 *||Aug 28, 2007||Jan 26, 2010||Nec Electronics Corporation||Method of manufacturing a semiconductor device that includes forming a via hole through a reaction layer formed between a conductive barrier and a wiring|
|U.S. Classification||438/631, 438/637, 438/633, 257/E21.579, 257/E21.589, 438/634, 257/E23.167|
|International Classification||H01L21/00, H01L23/532, H01L21/768, H01L21/44, H01L21/4763|
|Cooperative Classification||H01L23/53238, H01L23/5329, H01L21/76885, H01L21/76835, H01L2924/0002, H01L21/76807|
|European Classification||H01L21/768C6, H01L21/768B12, H01L23/532N, H01L23/532M1C4, H01L21/768B2D|
|May 24, 2004||AS||Assignment|
Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TU, JUI-NENG;REEL/FRAME:015368/0859
Effective date: 20040517