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Publication numberUS20050130407 A1
Publication typeApplication
Application numberUS 10/733,814
Publication dateJun 16, 2005
Filing dateDec 12, 2003
Priority dateDec 12, 2003
Also published asUS7285489, US20050142853
Publication number10733814, 733814, US 2005/0130407 A1, US 2005/130407 A1, US 20050130407 A1, US 20050130407A1, US 2005130407 A1, US 2005130407A1, US-A1-20050130407, US-A1-2005130407, US2005/0130407A1, US2005/130407A1, US20050130407 A1, US20050130407A1, US2005130407 A1, US2005130407A1
InventorsJui-Neng Tu
Original AssigneeJui-Neng Tu
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Dual damascene process for forming a multi-layer low-k dielectric interconnect
US 20050130407 A1
Abstract
In a dual damascene process for forming a multi-layer low-k dielectric interconnect, the formation of each layer of interconnect comprises deposition of a first low-k dielectric layer, etching of the first low-k dielectric layer to form two dual damascene vias, formation of two Cu conductor plugs enclosed with barrier layers in the two dual damascene vias, etching of the first low-k dielectric layer between the two dual damascene vias to form a trench, and spin-on of a second low-k dielectric layer filled in the trench. The spin-on low-k dielectric layer is selected to have a dielectric constant smaller than that of the first low-k dielectric layer to reduce the equivalent dielectric constant in the layer of interconnect.
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Claims(12)
1. A dual damascene process for forming a multi-layer low-k interconnects, comprising the steps of:
depositing a first dielectric layer of a first low-k on a substrate;
etching said first dielectric layer for forming two dual damascene vias extending through said first dielectric layer to expose a surface of said substrate;
forming a first barrier layer for covering on said first dielectric layer and said surface;
forming two Cu conductor plugs each filled in one of said two dual damascene vias;
forming a second barrier layer for covering on said two Cu conductor plugs to enclose said two Cu conductor plugs by said first and second barrier layers;
etching-back said first dielectric layer for forming a trench between said two dual damascene vias; and
spinning-on a second dielectric layer of a second low-k smaller than said first low-k in said trench.
2. The process of claim 1, wherein said forming two Cu conductor plugs comprises the steps of:
depositing a Cu conductor layer filled in said two dual damascene vias; and
etching-back said Cu conductor layer for leaving said Cu conductor layer in said two dual damascene vias.
3. The process of claim 2, further comprising etching said first barrier layer for leaving said first barrier layer in said two dual damascene vias after said etching-back said Cu conductor layer.
4. The process of claim 1, wherein said forming a second barrier layer comprises the steps of:
depositing said second barrier layer on said two Cu conductor plugs and first dielectric layer; and
applying CMP to said second barrier layer for leaving said second barrier layer over said two dual damascene vias.
5. The process of claim 1, wherein said depositing a first dielectric layer comprises depositing a SiOC by CVD.
6. The process of claim 1, wherein said etching-back said first dielectric layer comprises wet etching said first dielectric layer.
7. The process of claim 1, further comprising etching-back said second dielectric layer for planarizing said second dielectric layer to said second dielectric layer.
8. The process of claim 7, further comprising the steps of:
depositing a third dielectric layer of a third low-k on said second dielectric and barrier layers;
etching said third dielectric and second barrier layers for forming two second dual damascene vias extending through said third dielectric and second barrier layers to expose a surface of said two Cu conductor plugs;
forming a third barrier layer for covering on said third dielectric layer and surface of said two Cu conductor plugs;
forming two second Cu conductor plugs each filled in one of said first two dual damascene vias;
forming a fourth barrier layer for covering on said two second Cu conductor plugs to enclose said two second Cu conductor plugs by said third and fourth barrier layers;
etching-back said third dielectric layer for forming a second trench between said two second dual damascene vias; and
spinning-on a fourth dielectric layer of a fourth low-k smaller than said third low-k in said second trench.
9. A multi-layer low-k dual damascene interconnect comprising:
a first dielectric layer of a first low-k on a substrate;
a second dielectric layer of a second low-k smaller than said first low-k spun-on said first dielectric layer;
a plurality of dual damascene vias formed in said first and second dielectric layers;
a plurality of Cu conductor plugs each filled in one of said plurality of dual damascene vias; and
a barrier layer inserted between said plurality of Cu conductor plugs and first and second dielectric layers.
10. The interconnect of claim 9, wherein said first low-k has a value between 2.5 and 3.
11. The interconnect of claim 9, wherein said first dielectric layer comprises SiOC.
12. The interconnect of claim 9, wherein said second low-k has a value smaller than 2.5.
Description
FIELD OF THE INVENTION

The present invention relates generally to a dual damascene process and structure, and more particularly to a dual damascene process for forming a multi-layer low-k dielectric interconnect.

BACKGROUND OF THE INVENTION

Due to the rapid development of integrated circuit (IC) process, the components in an IC are shrunk to attain high density. For the high density and shrinkage, it is required more advanced wiring structure and new materials for better transmission performance. Thus, copper-based conductor is employed to replace the traditional aluminum wiring. High density of IC increases difficulties to the process and therefore, dual damascene process and structure is developed to simplify the fabrication work.

In general, dual damascene process may reduce overall fabrication steps and copper-based conductor may effectively lower the resistance of wiring. However, in an extremely high density IC, formation of dual damascene interconnect with Cu process still faces high RC delay due to high dielectric constant of the inter-layer dielectric (ILD), and delay of the IC in operation arises. Therefore, low-k dielectric is proposed to resolve the problem of such delay.

Utilization of low-k material for ILD may lower the effective dielectric constant of dual damascene interconnect. In U.S. Pat. No. 6,100,184 issued to Zhao et al., for instance, two low-k dielectric layers and an etch-stop dielectric layer inserted therebetween are deposited at first, and then the two low-k dielectric layers are etched to form dual damascene vias to fill Cu plugs therewith. However, this method of lowering the dielectric constant has its limitation. One of the reasons is that the dielectric constant of the aforementioned etch-stop dielectric layer is higher and this boosts up the total dielectric constant. Another reason for this is that no material of lower dielectric constant may be applied to this process. Kitch had proposed another dual damascene process in U.S. Pat. No. 6,143,641, by which method the original dielectric layer is removed after Cu dual damascene plugs are formed in the dielectric layer to fill another low-k dielectric layer to replace the original dielectric layer. Even though further lowering the effective dielectric constant, this process complicates the process as well and likewise, much lower dielectric constant material may not be applied in this process.

Among various low-k dielectric materials, the dielectric constant of fluorinated silicate glass (e.g., FSG) is about 3.5, CVD oxide (e.g., SiOC) is ranged between 2.5 and 3, and spin-on dielectric has a lowest one and smaller than 2.5. Conventional dual damascene process utilizing dielectric materials with dielectric constant between 2.5 and 3 have touched the limit of lowering effective dielectric constant. Therefore, other materials with much lower dielectric constant must be adopted to further reduce the total dielectric constant. Unfortunately, spin-on low-k dielectric having dielectric constant lower than 2.5 is difficult to apply to large area, uniform or thicker deposition and hence, is not suitable for current dual damascene process. In the process, spin-on low-k dielectrics are difficult to control and are only suitable for trench filling. If spin-on low-k dielectrics are employed to replace the conventional dual damascene dielectrics, the yield will be lowered. In other words, conventional dual damascene processes cannot make good use of spin-on low-k dielectrics to lower the effective dielectric constant of dual damascene interconnects. Therefore, it is desired a modified process to utilize spin-on low-k dielectrics to lower the effective dielectric constant of dual damascene interconnects.

SUMMARY OF THE INVENTION

One object of the present invention is to propose a process of forming a multi-layer Cu dual damascene interconnect to lower the effective dielectric constant thereof and thereby reduce the speed delay of the IC employing the multi-layer Cu dual damascene interconnect.

In a dual damascene process for forming a multi-layer low-k dielectric interconnect, according to the present invention, a low-k dielectric layer is deposited on a substrate by CVD and then etched to form a plurality of dual damascene vias, a barrier layer is formed to cover the low-k dielectric layer as well as the exposed surface of the substrate, each dual damascene via is filled with a Cu conductor plug, a second barrier layer is formed to cover on the top of the Cu conductor plugs, the low-k dielectric layer is etched to form trenches between the dual damascene vias, and a spin-on low-k dielectric layer is applied to fill in the trenches.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:

FIG. 1 is the cross-sectional view after the formation of dual damascene vias;

FIG. 2 is the cross-sectional view after the deposition of Cu conductor layer;

FIG. 3 is the cross-sectional view after the formation of Cu conductor plugs;

FIG. 4 is the cross-sectional view after the deposition of second barrier layer;

FIG. 5 is the cross-sectional view after the etching-back of the second barrier layer;

FIG. 6 is the cross-sectional view after the etching-back of the first low-k dielectric layer;

FIG. 7 is the cross-sectional view after the spinning-on of second dielectric layer;

FIG. 8 is the cross-sectional view after the planarization of the second dielectric as well as barrier layers; and

FIG. 9 is the cross-sectional view after the formation of multi-layer dual damascene interconnect.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1-8 are provided to illustrate an embodiment dual damascene process of the present invention. As shown in FIG. 1, a dielectric layer 10 is deposited on a substrate 12 and then the dielectric layer 10 is etched to form dual damascene vias 14. The substrate 12 is referred as the layer underlying the dual damascene interconnect, for example some semiconductor materials and/or metallization layer that have manufactured with several electronic devices thereof. The dielectric layer 10 may be an oxide with dielectric constant around 3.5 or a SiOC formed by CVD that has a dielectric constant between 2.5 and 3.

As shown in FIG. 2, a barrier layer 16 is formed and covered on the dielectric layer 10 and substrate 12, including the sidewall of the vias 14. The barrier layer 16 is made of materials capable of stopping Cu diffusion. Cu conductor 18 is then deposited to fill in the via 14. As shown in FIG. 3, the Cu conductor 18 and barrier layer 16 are etched back and thereby left only the parts in the vias 14. Next, as shown in FIG. 4, another barrier layer 20 is deposited on the Cu conductor 18, and the barrier layer 20 is also made of materials capable of stopping Cu diffusion. The barrier layers 16 and 20 may be made of materials selected from metal, metal alloy and metal compound. Chemical mechanical polishing (CMP) is applied to etch-back the barrier layer 20 so as to leave only the part above the vias 14, as shown in FIG. 5.

Next, as shown in FIG. 6, the dielectric layer 10 is etched to form trenches 22 each between two Cu conductor plugs 18. A spin-on low-k dielectric layer 24 is filled in the trenches 22, as shown in FIG. 7. The spin-on low-k dielectric layer 24 has a dielectric constant less than 2.5. As shown in FIG. 8, the dielectric layer 24 is etched-back to planarize the top surfaces of the dielectric layer 24 and barrier layer 20. To this point, a single layer of dual damascene interconnect is obtained.

The principle and features of the inventive dual damascene process are described below. CVD is used at first to form the large area and uniform dielectric 10 to the desired thickness, whose dielectric constant is between 2.5 and 3. After the Cu conductor plugs 18 are performed, some parts of the dielectric layer 10 are removed and become thinner thereof. The removed space, i.e., the trenches 22, is filled with spin-on low-k dielectric instead. Thus, the total or equivalent dielectric constant of the resulted ILD is lowered and high yield is maintained.

Repeating the aforementioned steps will obtain a multi-layer dual damascene interconnect. As shown in FIG. 9, for example, repeating the steps of FIGS. 1-8 will form another layer of dual damascene interconnect after the dual damascene interconnect shown in FIG. 8 is completed. In detail, the second layer of dual damascene interconnect comprises a layer of SiOC 30 deposited on the surface of the dielectric 24 and barrier layer 20 by CVD, Cu conductor plugs 34 enclosed by barrier layers extend through the dielectric layer 30 and the barrier layer 20 to electrically connect the Cu conductor plugs 18 underneath, and the spin-on low-k dielectric is further filled between the Cu conductor plugs 34. This way more layers of dual damascene interconnects may thus be achieved in stack layer by layer, each of them comprises a CVD SiOC and spin-on low-k dielectric layer inserted between the Cu conductor plugs.

While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US6605545 *Jun 1, 2001Aug 12, 2003United Microelectronics Corp.Method for forming hybrid low-K film stack to avoid thermal stress effect
US6664641 *Oct 2, 2002Dec 16, 2003Mitsubishi Denki Kabushiki KaishaWiring structure for an integrated circuit
US6756321 *Oct 5, 2002Jun 29, 2004Taiwan Semiconductor Manufacturing Co., LtdMethod for forming a capping layer over a low-k dielectric with improved adhesion and reduced dielectric constant
US6794293 *Oct 5, 2001Sep 21, 2004Lam Research CorporationTrench etch process for low-k dielectrics
US20040080050 *Mar 27, 2003Apr 29, 2004Lam Research CorporationMethod and apparats for detecting endpoint during plasma etching of thin films
US20040094839 *Nov 14, 2002May 20, 2004International Business Machines CorporationReliable low-k interconnect structure with hybrid dielectric
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7348272 *Aug 3, 2005Mar 25, 2008United Microelectronics Corp.Method of fabricating interconnect
US7651941 *Aug 28, 2007Jan 26, 2010Nec Electronics CorporationMethod of manufacturing a semiconductor device that includes forming a via hole through a reaction layer formed between a conductive barrier and a wiring
Classifications
U.S. Classification438/631, 438/637, 438/633, 257/E21.579, 257/E21.589, 438/634, 257/E23.167
International ClassificationH01L21/00, H01L23/532, H01L21/768, H01L21/44, H01L21/4763
Cooperative ClassificationH01L23/53238, H01L23/5329, H01L21/76885, H01L21/76835, H01L2924/0002, H01L21/76807
European ClassificationH01L21/768C6, H01L21/768B12, H01L23/532N, H01L23/532M1C4, H01L21/768B2D
Legal Events
DateCodeEventDescription
May 24, 2004ASAssignment
Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TU, JUI-NENG;REEL/FRAME:015368/0859
Effective date: 20040517