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Publication numberUS20050133860 A1
Publication typeApplication
Application numberUS 10/738,783
Publication dateJun 23, 2005
Filing dateDec 17, 2003
Priority dateDec 17, 2003
Also published asUS7241654, US7339239, US20060261404, WO2005060003A1
Publication number10738783, 738783, US 2005/0133860 A1, US 2005/133860 A1, US 20050133860 A1, US 20050133860A1, US 2005133860 A1, US 2005133860A1, US-A1-20050133860, US-A1-2005133860, US2005/0133860A1, US2005/133860A1, US20050133860 A1, US20050133860A1, US2005133860 A1, US2005133860A1
InventorsLeonard Forbes
Original AssigneeMicron Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Vertical NROM NAND flash memory array
US 20050133860 A1
Abstract
Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of the present invention include NROM memory cells in high density vertical NAND architecture arrays or strings facilitating the use of reduced feature size process techniques. These NAND architecture vertical NROM memory cell strings allow for an improved high density memory devices or arrays that can take advantage of the feature sizes semiconductor fabrication processes are generally capable of and yet do not suffer from charge separation issues in multi-bit NROM cells.
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Claims(40)
1. A vertical NROM NAND memory cell string, comprising:
a substrate, comprising one or more raised areas defining trenches therebetween;
a plurality of NROM memory cells, wherein the NROM memory cells are formed vertically on the sidewalls of one or more raised areas; and
wherein the plurality of NROM memory cells are coupled in a serial string by source/drain regions formed at the top of the one or more raised areas and at the bottom of the one or more trenches.
2. The vertical NROM NAND memory cell string of claim 1, wherein the raised areas are pillars.
3. The vertical NROM NAND memory cell string of claim 1, further comprising:
a plurality of word lines, wherein each word line is coupled to a control gate of a NROM memory cell of the string;
a bitline, wherein the bitline is coupled to a source/drain of a first NROM memory cell of the string; and
a source line, wherein the source line is coupled to a source/drain of a last NROM memory cell of the string.
4. The vertical NROM NAND memory cell string of claim 3, wherein the first and last NROM memory cells are coupled to the bitline and source line through a first and second select transistor.
5. A vertical NROM NAND memory array, comprising:
a substrate, comprising a plurality of pillars and associated intervening trenches;
a plurality of NROM memory cells, wherein the NROM memory cells are formed vertically on the sidewalls of the plurality of pillars; and
wherein the plurality of NROM memory cells are coupled into a plurality of NAND architecture memory strings by source/drain regions formed at the top of the plurality of pillars and at the bottom of the associated trenches.
6. The vertical NROM NAND memory array of claim 5, further comprising:
a plurality of word lines, wherein each word line is coupled to one or more control gates of one or more NROM memory cells, where each of the one or more NROM memory cells is from a differing NAND architecture memory string of the plurality of NAND architecture memory strings;
at least one bitline, wherein the at least one bitline is coupled to a source/drain of a first NROM memory cell of each NAND architecture memory string of the plurality of NAND architecture memory strings; and
at least one source line, wherein the at least one source line is coupled to a source/drain of a last NROM memory cell of each NAND architecture memory string of the plurality of NAND architecture memory strings.
7. The vertical NROM NAND memory array of claim 6, wherein the first and last NROM memory cells of each NAND architecture memory string are coupled to the at least one bitline and the at least one source line through a first and second select transistor.
8. The vertical NROM NAND memory array of claim 5, wherein an isolation region is formed between adjacent NAND architecture memory strings of the plurality of NAND architecture memory strings.
9. The vertical NROM NAND memory array of claim 8, wherein the isolation region is an oxide insulator.
10. The vertical NROM NAND memory array of claim 5, wherein each NAND architecture memory string of the plurality of NAND architecture memory strings is formed on a separate P-well isolation region formed on the substrate.
11. A NROM NAND architecture Flash memory device, comprising:
a NROM NAND architecture memory array formed on a substrate having a plurality of pillars and associated intervening trenches;
a plurality of NROM memory cells, wherein the NROM memory cells are formed vertically on the sidewalls of the plurality of pillars and trenches; and
wherein the plurality of NROM memory cells are coupled into a plurality of NAND architecture memory strings by source/drain regions formed at the top of the plurality of pillars and at the bottom of the associated trenches.
12. The NROM NAND architecture Flash memory device of claim 11, further comprising:
a plurality of word lines, wherein each word line is coupled to one or more control gates of one or more NROM memory cells, where each of the one or more NROM memory cells is from a differing NAND architecture memory string of the plurality of NAND architecture memory strings;
at least one bitline, wherein the at least one bitline is coupled to a source/drain of a first NROM memory cell of each NAND architecture memory string of the plurality of NAND architecture memory strings; and
at least one source line, wherein the at least one source line is coupled to a source/drain of a last NROM memory cell of each NAND architecture memory string of the plurality of NAND architecture memory strings.
13. The NROM NAND architecture Flash memory device of claim 12, wherein the first and last NROM memory cells of each NAND architecture memory string are coupled to the at least one bitline and the at least one source line through a first and second select transistor.
14. The NROM NAND architecture Flash memory device of claim 11, wherein the NROM memory cells of the NAND architecture Flash memory device is adapted to be programmed by one of tunnel injection of electrons, channel hot electron injection (HEI), and substrate enhanced hot electron injection (SEHE).
15. The NROM NAND architecture Flash memory device of claim 11, wherein the NROM memory cells of the NAND architecture Flash memory device is adapted to be erased by one of tunneling, negative voltages applied to the control gate voltages with respect to the substrate or P-well, and substrate enhanced band to band tunneling induced hot hole injection (SEBBHH).
16. A NROM NAND architecture Flash memory device comprising:
a NROM NAND architecture memory array formed on a substrate having a plurality of pillars and associated intervening trenches;
a plurality of NROM memory cells, wherein the NROM memory cells are formed vertically on the sidewalls of the plurality of pillars and trenches;
wherein the plurality of NROM cells are coupled into a plurality of NAND architecture memory strings by source/drain regions formed at the top of the plurality of pillars and at the bottom of the associated trenches;
a control circuit;
a row decoder;
a plurality of word lines coupled to the row decoder, wherein each word line is coupled to one or more control gates of one or more NROM memory cells, where each of the one or more NROM memory cells is from a differing NAND architecture memory string of the plurality of NAND architecture memory strings;
at least one bitline, wherein the at least one bitline is coupled to a source/drain of a first NROM memory cell of each NAND architecture memory string of the plurality of NAND architecture memory strings through a first select gate; and
at least one source line, wherein the at least one source line is coupled to a source/drain of a last NROM memory cell of each NAND architecture memory string of the plurality of NAND architecture memory strings through a second select gate.
17. A system, comprising:
a processor coupled to at least one memory device, wherein the at least one memory device comprises,
a NROM NAND architecture memory array formed on a substrate having a plurality of pillars and associated intervening trenches,
a plurality of NROM memory cells, wherein the NROM memory cells are formed vertically on the sidewalls of the plurality of pillars and trenches, and
wherein the plurality of NROM memory cells are coupled into a plurality of NAND architecture memory strings by source/drain regions formed at the top of the plurality of pillars and at the bottom of the associated trenches.
18. A vertical NROM NAND memory cell string, comprising:
a NAND architecture NROM memory cell memory string formed on a substrate having a plurality of NROM memory cells coupled source/drain to source/drain in a serial string; and
wherein vertical NROM NAND memory cell string is formed by forming a series of substrate pillars and intervening trenches, where the NROM memory cells are formed vertically within the trenches on the sidewalls of an adjacent pillar, such that each trench can hold two NROM memory cells.
19. A NROM NAND architecture Flash memory device comprising:
a NAND architecture memory array formed on a substrate having a plurality of NROM memory cells arranged in rows and columns and coupled into a plurality of NAND memory strings, wherein the NROM memory cells are formed vertically on the sidewalls of the plurality of pillars and associated trenches, and where the plurality of NROM memory cells are coupled into the plurality of NAND memory strings by source/drain regions formed at the top of the plurality of pillars and at the bottom of the associated trenches;
a plurality of word lines, wherein each word line is coupled to one or more gates of a row of the NROM memory cells;
a plurality of bitlines, wherein each bitline is coupled to a source/drain of a first NROM memory cell of one or more strings; and
at least one source line, wherein the at least one source line is coupled to a source/drain of a last NROM memory cell of one or more strings.
20. A method of forming a vertical NROM NAND architecture memory cell string, comprising:
forming one or more raised areas on a substrate, the raised areas defining intervening trenches;
forming a plurality of NROM memory cells on the sidewalls of the one or more raised areas; and
forming one or more source/drain regions on the top of the one or more raised areas and at the bottom of the intervening trenches.
21. The method of claim 20, wherein forming one or more raised areas on a substrate further comprises forming one or more pillars on a substrate.
22. The method of claim 20, wherein forming one or more source/drain regions on the top of the one or more raised areas and at the bottom of the intervening trenches further comprises forming one or more source/drain regions on the top of the one or more raised areas and at the bottom of the intervening trenches in one of before the formation of the plurality of NROM memory cells and after the formation of the plurality of NROM memory cells.
23. The method of claim 20, wherein the substrate is P-doped.
24. The method of claim 20, wherein forming a plurality of NROM memory cells on the sidewalls of the one or more raised areas further comprises forming a plurality of NROM memory cells on the sidewalls of the one or more raised areas by forming a gate-insulator stack on the surface of a plurality of selected sidewalls.
25. The method of claim 24, wherein forming a gate-insulator stack on the surface of a plurality of selected sidewalls further comprises forming a tunnel insulator on the surface of the plurality of selected sidewalls, forming a trapping layer on the tunnel insulator, forming an intergate insulator over the trapping layer, and forming a control gate over the intergate insulator.
26. The method of claim 25, wherein forming a tunnel insulator on the surface of the plurality of selected sidewalls, forming a trapping layer on the tunnel insulator, forming an intergate insulator over the trapping layer, and forming a control gate over the intergate insulator further comprises depositing each separate layer of tunnel insulator, nitride trapping layer, intergate insulator, and control gate over the one or more raised areas and/or trenches, and masking and directionally etching each layer.
27. The method of claim 25, wherein forming a tunnel insulator on the surface of the plurality of selected sidewalls, forming a trapping layer on the tunnel insulator, forming an intergate insulator over the trapping layer, and forming a control gate over the intergate insulator further comprises depositing layers of tunnel insulator, nitride, integate insulator, and control gate over the one or more raised areas and intervening trenches, and masking and directionally etching the combined layers to produce the gate-insulator stack.
28. The method of claim 24, wherein forming a gate-insulator stack on the surface of a plurality of selected sidewalls further comprises forming a gate-insulator stack of one of oxide-nitride-oxide (ONO), oxide-nitride-aluminum oxide, oxide-aluminum oxide-oxide, oxide-silicon oxycarbide-oxide, composite layers of an oxide-an oxide of Ti, Ta, Hf, Zr, or La, and an oxide, composite layers of an oxide-a non-stoichiometric oxide of Si, N, Al, Ti, Ta, Hf, Zr, and La, and an oxide, composite layers of an oxide-a wet oxide not annealed, and an oxide, composite layers of an oxide-a silicon rich oxide, and an oxide, composite layers of an oxide-a silicon rich aluminum oxide, and an oxide, and composite layers of an oxide-a silicon oxide with silicon carbide nanoparticles, and an oxide.
29. A method of forming a vertical NROM NAND architecture memory array, comprising:
forming a plurality of pillars and associated intervening trenches on a substrate;
forming a plurality of NROM memory cells on the sidewalls of the plurality of pillars; and
forming one or more source/drain regions on the top of the plurality of pillars and at the bottom of the associated intervening trenches to form a plurality of NROM NAND architecture memory strings.
30. The method of claim 29, wherein the substrate is P-doped.
31. The method of claim 29, further comprising:
forming a P-well isolation region under each NROM NAND architecture memory string.
32. The method of claim 29, further comprising:
forming an isolation region between adjacent NROM NAND architecture memory strings.
33. The method of claim 32, wherein forming an isolation region between adjacent NROM NAND architecture memory strings further comprises forming an isolation region of an oxide insulator.
34. The method of claim 32, wherein forming an isolation region between adjacent NROM NAND architecture memory strings further comprises forming a plurality of word lines across the isolation region between adjacent NROM NAND architecture memory strings, wherein each word line is coupled to a control gate of a single NROM memory cell of each NROM NAND architecture memory string.
35. The method of claim 29, wherein forming one or more source/drain regions on the top of the plurality of pillars and at the bottom of the associated intervening trenches further comprises forming one or more source/drain regions on the top of the plurality of pillars and at the bottom of the associated intervening trenches in one of before the formation of the plurality of NROM memory cells and after the formation of the plurality of NROM memory cells.
36. The method of claim 29, wherein forming a plurality of NROM memory cells on the sidewalls of the plurality of pillars and associated intervening trenches further comprises forming a plurality of NROM memory cells on the sidewalls of the plurality of pillars and associated intervening trenches by forming a gate-insulator stack on the surface of a plurality of selected sidewalls.
37. The method of claim 36, wherein forming a gate-insulator stack on the surface of a plurality of selected sidewalls further comprises forming a tunnel insulator on the surface of the plurality of selected sidewalls, forming a trapping layer on the tunnel insulator, forming an intergate insulator over the trapping layer, and forming a control gate over the intergate insulator.
38. The method of claim 37, wherein forming a tunnel insulator on the surface of the plurality of selected sidewalls, forming a trapping layer on the tunnel insulator, forming an intergate insulator over the trapping layer, and forming a control gate over the intergate insulator further comprises depositing each separate layer of tunnel insulator, nitride, integate insulator, and control gate over the plurality of pillars and trenches, and masking and directionally etching each layer.
39. The method of claim 37, wherein forming a tunnel insulator on the surface of the plurality of selected sidewalls, forming a trapping layer on the tunnel insulator, forming an intergate insulator over the trapping layer, and forming a control gate over the intergate insulator further comprises depositing layers of tunnel insulator, nitride, integate insulator, and control gate over the plurality of pillars and trenches, and masking and directionally etching the combined layers to produce the gate-insulator stack.
40. The method of claim 36, wherein forming a gate-insulator stack on the surface of a plurality of selected sidewalls further comprises forming a gate-insulator stack of one of oxide-nitride-oxide (ONO), oxide-nitride-aluminum oxide, oxide-aluminum oxide-oxide, oxide-silicon oxycarbide-oxide, composite layers of an oxide-an oxide of Ti, Ta, Hf, Zr, or La, and an oxide, composite layers of an oxide-a non-stoichiometric oxide of Si, N, Al, Ti, Ta, Hf, Zr, and La, and an oxide, composite layers of an oxide-a wet oxide not annealed, and an oxide, composite layers of an oxide-a silicon rich oxide, and an oxide, composite layers of an oxide-a silicon rich aluminum oxide, and an oxide, and composite layers of an oxide-a silicon oxide with silicon carbide nanoparticles, and an oxide.
Description
TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to integrated circuits and in particular the present invention relates to nitride read only memory Flash memory devices.

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to read-only memory (ROM), which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.

Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively.

Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that is typically erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks.” The memory cells of a Flash memory array are typically arranged into a “NOR” architecture (each cell directly coupled to a bit line) or a “NAND” architecture (cells coupled into “strings” of cells, such that each cell is coupled indirectly to a bit line and requires activating the other cells of the string for access). Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.

One recent type of Flash memory is a nitride read only memory (NROM). NROM has some of the characteristics of Flash memory but does not require the special fabrication processes of a conventional Flash memory, thus NROM integrated circuits can be implemented using a standard CMOS process. Because of their unique device characteristics, some NROM memory cells can also store multiple data bits in each cell (typically two bits each).

FIG. 1 illustrates a cross-sectional view of a typical prior art NROM memory cell with a channel length, L. The cell is comprised of a control gate 100 formed on top of an oxide-nitride-oxide (ONO) layer. This layer is comprised of an oxide layer 101 on top of a nitride 103 layer upon which the charge is stored for the various states of the cell. In one embodiment, the cell has trapping areas 105 and 106 for storing two bits of data on the nitride layer 103. The nitride layer 103 is deposited on another oxide layer 104 that is on the substrate.

Two source/drain regions 109 and 111 are at either end of the gate 100. The source/drain regions 109 and 111 are connected by a channel area 110 between the two source/drain regions 109 and 111. The function of each source/drain region 109 or 111 (i.e., whether source or drain) depends upon which bit trapping area 105 or 106 is being read or written. For example, in a read operation, if the carrier is input at the left side source/drain region 111 and output from the right side region 109, the left side is the source 111 and the right side is the drain 109 and the data bit charge is stored on the nitride 103 at the source end 111 for bit trapping area 106.

As integrated circuit processing techniques improve, manufacturers try to reduce the feature sizes of the devices produced and thus increase the density of the IC circuits and memory arrays. In many cases, the feature sizes of the devices are limited by the device characteristics before the minimum feature size that the process is capable of is reached. In NROM devices in particular, as the channel length is reduced, a minimum size is typically reached that is primarily dictated by the device operational characteristics. FIG. 2 illustrates a typical prior art planar NROM device that has a channel length that is less than 100 nm. In this case, the channel length is so short that the trapping areas 205 and 206 of the two data bits/cell NROM device overlap. This overlap may cause data write and read errors.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method and architecture for producing a smaller multiple-bit NROM device array without trapping area overlap.

SUMMARY OF THE INVENTION

The above-mentioned problems with producing high density multiple-bit NROM device arrays without trapping area overlap and other problems are addressed by the present invention and will be understood by reading and studying the following specification.

NROM NAND architecture memory devices and arrays, in accordance with embodiments of the present invention, facilitate the utilization of NROM memory cells in high density NAND architecture arrays or strings with modern reduced feature size process techniques. Memory embodiments of the present invention utilize vertical NROM memory cells to form NAND architecture memory cell strings and memory arrays. These NAND architecture vertical NROM memory cell strings allow for improved high density memory devices or arrays that can take advantage of the feature sizes the semiconductor fabrication processes are generally capable of and yet do not suffer from charge separation issues in typical multi-bit NROM cells.

For one embodiment, the invention provides a vertical NROM NAND memory cell string comprising a substrate, comprising one or more raised areas defining trenches therebetween, a plurality of NROM memory cells, wherein the NROM memory cells are formed vertically on the sidewalls of one or more raised areas, and wherein the plurality of NROM memory cells are coupled in a serial string by source/drain regions formed at the top of the one or more raised areas and at the bottom of the one or more trenches.

For another embodiment, the invention provides a vertical NROM NAND memory array comprising a substrate, comprising a plurality of pillars and associated intervening trenches, a plurality of NROM memory cells, wherein the NROM memory cells are formed vertically on the sidewalls of the plurality of pillars, and wherein the plurality of NROM memory cells are coupled into a plurality of NAND architecture memory strings by source/drain regions formed at the top of the plurality of pillars and at the bottom of the associated trenches.

For yet another embodiment, the invention provides a system comprising a processor coupled to at least one memory device. The at least one memory device comprising a NROM NAND architecture memory array formed on a substrate having a plurality of pillars and associated intervening trenches, a plurality of NROM memory cells, wherein the NROM memory cells are formed vertically on the sidewalls of the plurality of pillars and trenches, and wherein the plurality of NROM memory cells are coupled into a plurality of NAND architecture memory strings by source/drain regions formed at the top of the plurality of pillars and at the bottom of the associated trenches.

For a further embodiment, the invention provides a method of forming a vertical NROM NAND architecture memory cell string comprising forming one or more raised areas on a substrate, the raised areas defining intervening trenches, forming a plurality of NROM memory cells on the sidewalls of the one or more raised areas, and forming one or more source/drain regions on the top of the one or more raised areas and at the bottom of the intervening trenches.

For yet a further embodiment, the invention provides a method of forming a vertical NROM NAND architecture memory array comprising forming a plurality of pillars and associated intervening trenches on a substrate, forming a plurality of NROM memory cells on the sidewalls of the plurality of pillars, and forming one or more source/drain regions on the top of the plurality of pillars and at the bottom of the associated intervening trenches to form a plurality of NROM NAND architecture memory strings.

Other embodiments are also described and claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-sectional view of a typical prior art NROM cell.

FIG. 2 shows a cross-sectional view of a typical prior art NROM cell with a channel less than 100 nm.

FIGS. 3A and 3B detail a planar NAND Flash memory array of the prior art.

FIGS. 4A-4D details vertical NROM NAND Flash memory cells and array strings in accordance with embodiments of the present invention.

FIG. 5 details vertical NAND NROM cells and substrate in accordance with embodiments of the present invention.

FIG. 6 details a schematic of a vertical NAND NROM string in accordance with embodiments of the present invention.

FIG. 7 details a block diagram of an electronic system in accordance with embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The terms wafer and substrate used previously and in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFI) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims and equivalents thereof.

Memory strings, arrays, and devices in accordance with embodiments of the present invention, facilitate the use of NROM memory cells in high density vertical NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of the present invention utilize NROM memory cells in high density vertical NAND architecture arrays or strings, facilitating the use of reduced feature size process techniques, e.g., 0.1 μm or below. Memory embodiments of the present invention include vertical NROM memory cells to form NAND architecture memory cell strings and memory arrays. These NAND architecture vertical NROM memory cell strings allow for an improved high density memory devices or arrays that can take advantage of the feature sizes semiconductor fabrication processes are generally capable of and yet not suffer from charge separation issues.

As stated above, many conventional NROM memory cells suffer from problems with charge separation in multi-bit utilizations when the channel length of the cell gets too small. As a result, the maximum density of an array of typical NROM memory cells can be limited by the need to maintain charge separation, even if the process technology can attain even smaller features and/or channel lengths. In particular, this is an issue in higher capacity memory types, such as NAND architecture Flash arrays and devices, where small changes in the memory cell footprint (e.g., memory cell channel widths) can have a large effect on the overall cell density in the array and the resulting storage capacity. By constructing NROM memory cells/gates in a vertical orientation, embodiments of the present invention allow for increases in memory array cell density and improved utilization of process minimum feature size capabilities while maintaining an appropriate NROM memory cell channel length to allow for effective charge separation.

As previously stated, the two common types of Flash memory array architectures are the “NAND” and “NOR” architectures, so called for the similarity each basic memory cell configuration has to the corresponding logic gate design. In the NOR array architecture, the NROM memory cells of the memory array are arranged in a matrix similar to RAM or ROM. The gates of each NROM memory cell of the array matrix are coupled by rows to word select lines (word lines) and their drains are coupled to column bit lines. The source of each NROM memory cell is typically coupled to a common source line. The NOR architecture NROM memory array is accessed by a row decoder activating a row of NROM memory cells by selecting the word line coupled to their gates. The row of selected memory cells then place their stored data values on the column bit lines by flowing a differing current from the coupled source line to the coupled column bit lines depending on their programmed states. A column page of bit lines is selected and sensed, and individual data words are selected from the sensed data words from the column page and communicated from the Flash memory.

A NAND array architecture also arranges its array of NROM memory cells in a matrix such that the gates of each NROM memory cell of the array are coupled by rows to word lines. However each memory cell is not directly coupled to a source line and a column bit line. Instead, the memory cells of the array are arranged together in strings, typically of 8 16, 32, or more each, where the memory cells in the string are coupled together in series, source to drain, between a common source line and a column bit line. This allows a NAND Flash array architecture to have a higher memory cell density than a comparable NOR Flash array, but with the cost of a generally slower access rate and programming complexity.

A NAND architecture NROM memory array is accessed by a row decoder activating a row of NROM memory cells by selecting the word select line coupled to their gates. In addition, the word lines coupled to the gates of the unselected memory cells of each string are also driven. However, the unselected memory cells of each string are typically driven by a higher gate voltage so as to operate them as pass transistors and allowing them to pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each NROM memory cell of the series coupled string, restricted only by the memory cells of each string that are selected to be read. This places the current encoded stored data values of the row of selected memory cells on the column bit lines. A column page of bit lines is selected and sensed, and then individual data words are selected from the sensed data words from the column page and communicated from the Flash memory.

FIGS. 3A and 3B show a simplified planar NROM NAND Flash memory array of the prior art. FIG. 3A details a top view of a planar NROM NAND Flash memory string 304 of a NROM NAND Flash memory array 300, a side view of the planar NROM NAND Flash memory string 304 is detailed in FIG. 3B. In FIGS. 3A and 3B, a series of NROM memory cells 302 are coupled together in a series NROM NAND string 304 (typically of 8, 16, 32, or more cells). Each NROM memory cell 302 has a gate-insulator stack that is made of a tunnel insulator (typically of an oxide) on top of a substrate 308, a trapping layer (typically of nitride) formed on the tunnel insulator, an intergate insulator formed over the trapping layer, and a control gate 306 (typically formed in a control gate line, also known as a word line) formed over the intergate insulator. N+ doped regions are formed between each gate insulator stack to form the source and drain regions of the adjacent floating gate memory cells; which additionally operate as connectors to couple the cells of the NAND string 304 together. Select gates 310, that are coupled to gate select lines, are formed at either end of the NAND floating gate string 304 and selectively couple opposite ends of the NAND floating gate string 304 to a bit line contact 312 and a source line contact 314.

FIGS. 4A-4D details simplified vertical NROM NAND Flash memory cells and array strings of embodiments of the present invention. FIG. 4A details a side view of a simplified vertical NROM NAND Flash memory array string 404 of a NROM NAND Flash memory array 400, a top view of the vertical NROM NAND Flash memory array 400 is detailed in FIG. 4C showing sections of two vertical NROM NAND Flash memory array strings 404. A three dimensional view of the vertical NROM NAND Flash memory array 400 is detailed in FIG. 4D. Methods of forming vertical memory cells are detailed in U.S. patent application Ser. No. 10/177,208, titled “Vertical NROM having a storage density of 1 bit per 1F2”, filed Jun. 21, 2002, and U.S. Pat. No. 5,936,274, titled “High density flash memory”, issued Aug. 10, 1999, which are commonly assigned. Methods of forming vertical split control gates are detailed U.S. Pat. No. 6,150,687, titled “Memory cell having a vertical transistor with buried source/drain and dual gates”, issued Nov. 21, 2000, and U.S. Pat. No. 6,072,209, titled “Four F folded bit line DRAM cell structure having buried bit and word lines”, issued Jun. 6, 2000, which are also commonly assigned.

In FIG. 4A, a series of vertically formed NROM floating gate memory cells 402 are coupled together in a series NAND string 404 (typically of 8, 16, 32, or more cells). As shown in the detailed section of vertical NROM NAND Flash memory array string 404 of FIG. 4B, in creating the vertical NROM NAND Flash memory array string 404 a series of substrate pillars 428 are formed in a substrate 408 with trenches 430 located between them. The vertical NROM memory cells 402 are then formed on the sidewalls of the pillars 428 within the trenches 430. Each vertical NROM memory cell 402 is formed on the sidewalls of the substrate pillars 428 (for two NROM memory cells 402 per trench 430 and has a gate-insulator stack made of a tunnel insulator 420 formed on the surface of the sidewall, a floating nitride gate 422 formed on the tunnel insulator 420, an intergate insulator 424 formed over the floating gate 422, and a control gate 406 (typically formed in a control gate line, also known as a word line) formed over the intergate insulator 424. In one embodiment the substrate pillars 428 and trenches 430 are formed by patterning a masking material that is layered over the substrate 408 and anisotropically etching the trenches 430. The gate-insulator stack of each NROM memory cell 402 are formed in one embodiment by successive layering of each of the materials of the gate insulator stack over the pillars 428 and trenches 430, followed by a mask and directional etch of the deposit of each layer to leave only the material deposited on the sidewall of the pillars 428. In another embodiment, differing layers of the gate-insulator stack are formed and then masked and directionally etched in a single step.

N+ doped regions 426 are formed at the top of the substrate pillars 428 and at the bottom of the trenches 430 between each vertical NROM memory cell/gate-insulator stack 402 to form the source and drain regions of the adjacent floating gate memory cells 402 and couple the NROM cells 402 together to form the vertical NROM NAND string 404. It is noted that the N+ source/drain regions 426 may be formed before or after the formation of the NROM memory cells/gate-insulator stack 402. Select gates 410, that are coupled to gate select lines, are formed at either end of the NAND floating gate memory string 404 and selectively couple opposite ends of the NAND floating gate memory string 404 to a bit line contact 412 and a source line contact 414.

As stated above, in the top view of the vertical NROM NAND Flash memory array 400 of FIG. 4C and in the three dimensional view of FIG. 4D, sections of two vertical NROM NAND Flash memory array strings 404 are shown. Between the substrate pillars 428 of the two vertical NROM NAND Flash memory array strings 404 isolation regions 432 have been formed to isolate the vertical NROM NAND Flash memory array strings 404 from each other. These isolation regions 432 are typically formed of an oxide insulator. It is noted that the isolation regions 432 between the vertical NROM NAND strings 404 can be extended into the substrate 408 to allow the formation P-wells, where each P-well contains a single NROM NAND string 404 and can be biased in isolation from the other strings 404 of the array 400. It is also noted that the control gate/word address lines 406 cross these isolation regions 432 so that each control gate/word address line 406 controls the operation of NROM memory cells 402 across multiple NROM NAND memory strings 404.

In the vertical NROM NAND Flash memory array 400 and strings 404 of FIGS. 4A-4D, the channel length of each NROM memory cell 402 is determined by the depth of the trenches 430 and not by the minimum feature size. Due to the vertical form of the NROM NAND Flash memory array 400 and strings 404 of embodiments of the present invention, a vertical NROM NAND Flash memory array string 404 can be produced that typically has twice the density for a given string horizontal run length than a corresponding planar NROM NAND Flash memory array string 302.

FIG. 5 details vertical NAND NROM cells 402 and substrate 408 of a vertical NROM NAND Flash memory array string 500 in accordance with embodiments of the present invention. In FIG. 5, the substrate 408 of the vertical NROM NAND memory array string 500 is P-doped. A substrate connection 534 is shown, which can allow for biasing of the P-doped substrate 408. It is noted that other forms of substrate doping, substrate biasing, and substrate types and regions (including, but not limited to silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFI) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor) in embodiments of the present invention are possible and should be apparent to those skilled in the art with the benefit of the present invention.

FIG. 6 details an equivalent circuit schematic 600 of a vertical NAND NROM string 404, showing NROM cells 402 and substrate connection 534, in accordance with embodiments of the present invention. As can be seen, the schematic 600 provides the same equivalent circuit as that of a conventional planar NROM NAND string 304.

It is noted that the NROM memory cells of embodiments of the present invention can be formed from multiple conventional materials. For the gate-insulator stack (gate insulator-trapping layer-top insulator) these materials may include, but are not limited to, oxide-nitride-oxide (ONO), oxide-nitride-aluminum oxide, oxide-aluminum oxide-oxide, oxide-silicon oxycarbide-oxide, composite layers of an oxide-an oxide of Ti, Ta, Hf, Zr, or La, and an oxide, and composite layers of an oxide-a non-stoichiometric oxide of Si, N, Al, Ti, Ta, Hf, Zr, and La, and an oxide. Additional trapping layer materials for NROM memory cell embodiments of the present invention, may also include, but are not limited to, wet oxides not annealed, silicon rich oxides, silicon rich aluminum oxide, silicon oxycarbide, silicon oxide with silicon carbide nanoparticles, and non-stoichiometric oxide of Si, N, Al, Ti, Ta, Hf, Zr, and La.

Programming of the NROM memory cells 402 of the vertical NROM NAND Flash memory strings 404 embodiments of the present invention can be accomplished by conventional tunnel injection of electrons by having a positive gate 406 voltage with respect to the substrate or P-well 408. In another embodiment of the present invention, programming is accomplished by channel hot electron injection (HEI). Erasure of the NROM memory cells 402 of embodiments of the present invention can accomplished by conventional tunneling or negative voltages applied to the control gate 406 voltages with respect to the substrate or P-well 408. With the above listed programming and erasure techniques, the NROM memory cells 402 of embodiments of the present invention can be utilized for two-bit storage as a conventional planar NROM memory cells would be, storing charge in the trapping layer near each source/drain 426, allowing one bit to be read/programmed when biased in the forward direction and the other to be read/programmed when biased in the reverse direction.

In alternative embodiments of the present invention, substrate enhanced hot electron injection (SEHE) can be utilized for NROM memory cell 402 programming and/or substrate enhanced band to band tunneling induced hot hole injection (SEBBHH) for NROM memory cell 402 erasure. However, while the required voltages for these operations may be lower, they may only be suitable for single bit storage operation mode.

FIG. 7 illustrates a functional block diagram of a memory device 700 that can incorporate the vertical NROM Flash memory cells of the present invention. The memory device 700 is coupled to a processor 710. The processor 710 may be a microprocessor or some other type of controlling circuitry. The memory device 700 and the processor 710 form part of an electronic system 720. The memory device 700 has been simplified to focus on features of the memory that are helpful in understanding the present invention.

The memory device includes an array of vertical NROM Flash memory cells 730. In one embodiment, the memory cells are vertical NROM Flash memory cells and the memory array 730 is arranged in banks of rows and columns. The control gates of each row of memory cells are coupled with a wordline while the drain and source connections of the memory cells are coupled to bitlines. As is well known in the art, the connection of the cells to the bitlines depends on whether the array is a NAND architecture or a NOR architecture.

An address buffer circuit 740 is provided to latch address signals provided on address/data bus 762. Address signals are received and decoded by a row decoder 744 and a column decoder 746 to access the memory array 730. It will be appreciated by those skilled in the art, with the benefit of the present description, that the size of address input on the address/data bus 762 depends on the density and architecture of the memory array 730. That is, the size of the input address increases with both increased memory cell counts and increased bank and block counts. It is noted that other address input manners, such as through a separate address bus, are also known and will be understood by those skilled in the art with the benefit of the present description.

The memory device 700 reads data in the memory array 730 by sensing voltage or current changes in the memory array columns using sense/buffer circuitry 750. The sense/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array 730. Data input and output buffer circuitry 760 is included for bi-directional data communication over a plurality of data connections in the address/data bus 762 with the processor/controller 710. Write circuitry 755 is provided to write data to the memory array.

Control circuitry 770 decodes signals provided on control connections 772 from the processor 710. These signals are used to control the operations on the memory array 730, including data read, data write, and erase operations. The control circuitry 770 may be a state machine, a sequencer, or some other type of controller.

Since the NROM memory cells of the present invention use a CMOS compatible process, the memory device 700 of FIG. 7 may be an embedded device with a CMOS processor.

The Flash memory device illustrated in FIG. 7 has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of Flash memories are known to those skilled in the art.

It is also noted that other vertical NROM NAND memory strings, arrays, and memory devices in accordance with embodiments of the present invention are possible and should be apparent to those skilled in the art with benefit of the present disclosure.

Conclusion

Memory devices, arrays, and strings have been described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of the present invention include NROM memory cells in high density vertical NAND architecture arrays or strings facilitating the use of reduced feature size process techniques, e.g., 0.1 μm or below. These NAND architecture vertical NROM memory cell strings allow for an improved high density memory devices or arrays that can take advantage of the feature sizes semiconductor fabrication processes are generally capable of and yet do not suffer from charge separation issues in multi-bit NROM cells.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.

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Classifications
U.S. Classification257/330, 257/390, 257/E27.103, 257/E21.679, 438/259, 438/290, 257/331
International ClassificationH01L27/115, H01L21/8246, G11C16/04
Cooperative ClassificationH01L27/115, G11C16/0483, H01L27/11568, G11C16/0466
European ClassificationH01L27/115, H01L27/115G4
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