US20050145899A1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- US20050145899A1 US20050145899A1 US11/058,245 US5824505A US2005145899A1 US 20050145899 A1 US20050145899 A1 US 20050145899A1 US 5824505 A US5824505 A US 5824505A US 2005145899 A1 US2005145899 A1 US 2005145899A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12535—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.] with additional, spatially distinct nonmetal component
- Y10T428/12542—More than one such component
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
After deposition of a conductor film made of titanium tungsten over a main surface of a semiconductor substrate formed with grooves, an initial conductor film made of aluminium is further deposited. Subsequently, the conductor film is made to reflow and run into the grooves. Thereafter, while heating, further conductor films are respectively deposited, thereby causing these conductor films to run into the grooves. The provision of the initial conductor film suppresses or prevents aluminium in the further conductor films and silicon in the semiconductor substrate from reacting with each other during reflowing of the conductor films.
Description
- The present invention relates to a technique for use in the manufacture of a semiconductor device; and, more particularly, the invention relates to a technique that is effective for application to a wiring process that includes a step of burying a conductive film, that is made mainly of aluminium (Al), inside an opening for wiring.
- The wiring technique studied by us is, for example, as set out below. Initially, an opening for wiring is formed in a semiconductor substrate, after which a titanium (Ti) film, for example, is deposited on the semiconductor substrate, including the inside of the wiring opening. Subsequently, an aluminium film, for example, is deposited on the titanium film at low temperatures and high power to a relatively large thickness (e.g. about 200 nm). Thereafter, the semiconductor substrate is maintained at high temperatures (e.g. about 400° C.) until the aluminium film is deposited to a desired thickness (e.g. about several hundreds of nanometers). The high temperatures are kept continuously over several minutes to cause reflow of the aluminium film, thereby causing the opening to be buried therewith.
- A wiring technique is set out, for example, in Japanese Laid-open Patent Application No. 2001-267569. In this application, a technique is disclosed wherein a source electrode of a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is constituted of a barrier layer that is made, for example, of titanium tungsten, titanium nitride (TiN) or the like, and this barrier layer is built up with pure aluminium thereon, so as to prevent a failure from occurring upon ultrasonic wire bonding.
- We have found that the wiring technique studied by us has the following problems. If the amount of buried aluminium inside the opening for wiring increases, then it becomes necessary to heat the aluminium to higher temperatures so as to enhance the reflowability of the aluminium. Nevertheless, the barrier properties of titanium are not satisfactory, so that when the heating temperature exceeds, for example, about 400° C., a reaction between the aluminium and silicon (Si) proceeds, with some possibility that a junction leakage failure will occur.
- An object of the present invention is to provide a technique that is capable of improving the reliability of semiconductor devices.
- The above and other objects and novel features of the present invention will become apparent from the following description, when taken with reference to the accompanying drawings.
- A typical embodiment of the invention, among those embodiments disclosed in this application, will be briefly described below.
- According to the invention, there is provided a method of manufacture of a semiconductor device, which method comprises the steps of: depositing, on a semiconductor substrate including an opening for wiring, a first conductive film having a structure that is capable of suppressing or preventing a reaction from occurring between an aluminium atom and a constituent atom of the semiconductor substrate upon thermal treatment for re-melting of the conductive film, which is made mainly of aluminium; and thermally treating the conductor film made mainly of aluminium after, or in the course of deposition thereof, until re-melting occurs, thereby causing the aluminium-based conductor film to flow and run into the opening for wiring.
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FIG. 1 is a sectional view of the structure during a step in the process of manufacture of a semiconductor device according to one embodiment of the invention; -
FIG. 2 is a sectional view of the structure during a step in the process of manufacture of the semiconductor device, subsequent to the step ofFIG. 1 ; -
FIG. 3 is a sectional view of the structure during a step in the process of manufacture of the semiconductor device, subsequent to the steps ofFIG. 2 ; -
FIG. 4 is a sectional view of the structure during a step in the process of manufacture of the semiconductor device, subsequent to the steps ofFIG. 3 ; -
FIG. 5 is an enlarged, sectional view of the part A ofFIG. 4 ; -
FIG. 6 is a flowchart of the process for burying a groove formed in the manufacture of the semiconductor device ofFIG. 4 ; -
FIG. 7 is an enlarged, sectional view of the part A in the course of manufacture of the semiconductor device, subsequent to the step ofFIG. 4 ; -
FIG. 8 is an enlarged, sectional view of the part A in the course of manufacture of the semiconductor device, subsequent to the step ofFIG. 7 ; -
FIG. 9 is an enlarged, sectional view of the part A in the course of manufacture of the semiconductor device, subsequent to the step ofFIG. 8 ; -
FIG. 10 is an enlarged, sectional view of the part A in the course of manufacture of the semiconductor device, subsequent to the step ofFIG. 9 ; -
FIG. 11 is an enlarged, sectional view of the part A in the course of manufacture of the semiconductor device, subsequent to the step ofFIG. 10 ; -
FIG. 12 is an enlarged, sectional view of the part A in the course of manufacture of the semiconductor device, subsequent to the step ofFIG. 11 ; -
FIG. 13 is an enlarged, sectional view of the part A in the course of manufacture of the semiconductor device, subsequent to the step ofFIG. 12 ; -
FIG. 14 is an enlarged, sectional view of the structure during a step in the process of manufacture of the semiconductor device, subsequent to the step ofFIG. 13 ; -
FIG. 15 is a top plan view of the structure during a step in the process of manufacture of a semiconductor device according to another embodiment of the invention; -
FIG. 16 is a section, taken along the line X1-X1 ofFIG. 15 ; -
FIG. 17 is an enlarged, sectional view of the structure during a step in the process of manufacture of the semiconductor device, subsequent to the step ofFIG. 16 ; -
FIG. 18 is an enlarged, sectional view of the structure during a step in the process of manufacture of the semiconductor device, subsequent to the step ofFIG. 17 ; -
FIG. 19 is a top plan view of the structure during a step in the process of manufacture of a semiconductor device according to a further embodiment of the invention; -
FIG. 20 is a section, taken along the line X2-X2 ofFIG. 19 ; -
FIG. 21 is an enlarged, sectional view of the structure during a step in the process of manufacture of the semiconductor device, subsequent to the step ofFIG. 20 ; -
FIG. 22 is an enlarged, sectional view of the structure during a step in the process of manufacture of the semiconductor device, subsequent to the step ofFIG. 21 ; and -
FIG. 23 is a sectional view of the structure during a step in the process of manufacture of a semiconductor device according to a still further embodiment of the invention. - Although embodiments of the invention are illustrated by division of the subject matter into a plurality of sections or sub-embodiments, if expediently necessary, these divisions are not to be taken as being mutually irrelevant to one another, unless otherwise stated. More particularly, one division may be in a relation with a modification, details, supplemental explanation and the like of part or all of the others. In the following description of the embodiments, where reference is made to a number and other parameters of elements (including the number, numerical value, quantity, range and the like), they should not be construed as being limited to specified values or numbers, respectively, except for the case where they are otherwise specified or limited to a specific value apparently in principle. That is, those values smaller than or larger than the respective specified values may also be within the scope of the invention.
- Moreover, it is as a matter of course that constituent elements (including steps) in the following embodiments are not always essential, except in the case where otherwise specified or where such elements are considered to be apparently essential in principle. Likewise, if reference is made to the shape, position, relation and the like of the constituent elements, then substantially the same or similar shapes and the like are also within the scope of the invention, except for the case where they are otherwise specified or where such shapes should not be apparently included as a matter of principle. This is true of the above-indicated numbers and ranges as well.
- Throughout the drawings illustrating the embodiments of the invention, like reference numerals indicate like parts or members having the same function, which parts or members are not repeatedly explained after once having been explained.
- In the description of the embodiments of the invention, by the expression, for example, “composed or made of aluminium”, it is intended that aluminium is used as a main component. In general, it is assumed that highly pure aluminium contains impurities, and, thus, a member made, for example, of aluminium should not be construed as excluding the inclusion of additives or impurities therein. This is not limited to aluminium, but is applied to other types of metals and the like (such as titanium tungsten, tungsten, tantalum, nitrides thereof, and tungsten silicide or its nitride).
- The embodiments of the invention will be described in detail with reference to the accompanying drawings.
- (Embodiment 1)
- A semiconductor substrate in accordance with
Embodiment 1 has, for example, a n-channel power MISFET (Power Metal Insulator Semiconductor Field Effect Transistor: power transistor) having a trench gate structure. An example of a method of manufacture of a semiconductor device according toEmbodiment 1 of the invention will be described with reference to FIGS. 1 to 14. -
FIG. 1 is a sectional view of the structure during manufacture of the semiconductor device ofEmbodiment 1. The semiconductor device (hereinafter referred to simply as a substrate) is in the form of a so-called epitaxial wafer (hereinafter referred to simply as a wafer) having, for example, a structure in which an n−type semiconductor layer 1 b is deposited on an n+ semiconductor layer 1 a using an epitaxial technique. Thesemiconductor layers semiconductor layer 1 a is, for example, at about 2.0×1019 cm−3, and that of thesemiconductor layer 1 b is, for example, at about 1.0×1016 cm−3. - The
semiconductor layer 1 b is formed with a p− type semiconductor region 2 (well: first semiconductor region) therein. Thissemiconductor region 2 has channels for a plurality of power MISFET's (hereinafter referred to simply as power MIS('s) to be formed therein. Thesemiconductor region 2 is formed, for example, by distributing boron (B) from the main surface of thesemiconductor layer 1 b to an intermediate position along the thickness of thesemiconductor layer 1 b. The peak concentration of the impurity in thesemiconductor region 2 is set, for example, at about 1×1016 to about 1×1018 cm−3. - A p-type semiconductor region (well) 3 is formed along the outer peripheral end of the
semiconductor region 2 in thesemiconductor layer 1 b. Boron, for example, is contained in thissemiconductor region 3. Anisolation region 4 that is made, for example, of silicon oxide (SiO2 or the like) is formed, according to a LOCOS (Local Oxidization of Silicon) technique or the like, at the isolation region in the main surface of thesemiconductor layer 1 b. Theisolation region 4 may be in the form of a groove (trench isolation). - The active region surrounded by the
isolation region 4 becomes a power MID-forming region. This active region is formed with a plurality of grooves (first grooves) 5 therein. Thegrooves 5, respectively, are provided for every cell, and they extend from the main surface of thesemiconductor layer 1 b to an intermediate position in the direction of the depth of thesemiconductor layer 1 b, as viewed in section, and they extend along a certain direction as viewed in plane view. The inner wall surfaces of thegroove 5 and the upper surface of thesemiconductor layer 1 b at an area around the opening of thegroove 5 have agate insulating film 6, that is made, for example, of silicon oxide, formed thereon. - A trench-
type gate electrode 7 of the power MIS is formed on thegate insulating film 6. Thegate electrode 7 is made, for example, of a low resistance polysilicon film and is shaped in the form of a T in section. More particularly, thegate electrode 7 has afirst portion 7 a that is buried inside the groove, from which it is separated by thegate insulating film 6, and asecond portion 7 b that joins thefirst portion 7 a, projects outwardly from the groove and has a width greater than the width of the groove 5 (i.e. the width along a minor direction). - At the outer periphery of the power MID-forming region, an
extrinsic gate wiring 7L is formed on the main surface of thesemiconductor layer 1 b, from which it is spaced by thegate insulating film 6 and theisolation region 4. Theextrinsic gate wiring 7L is integrally formed with therespective gate electrodes 7 and is to be electrically connected therewith. A cap insulating film (first insulating film) 8, which is made, for example, of a silicon oxide film, is deposited, after patterning, over thegate electrodes 7 and theextrinsic gate wiring 7L. - An n-type semiconductor region (second semiconductor region) 9 a, serving as a source, is formed at a portion of the
semiconductor layer 1 b that is established betweenadjacent gate electrodes 7. Thissemiconductor region 9 a is formed by distributing, for example, arsenic (As) from the main surface of thesemiconductor layer 1 b to an intermediate position along the depth of thesemiconductor region 2, which processing has been already carried out prior to the formation of thegroove 5. The peak concentration of the impurity in thesemiconductor region 9 a is, for example, about 1×1018 to about 1×1020 cm−3. -
FIGS. 2 and 3 are, respectively, sectional views of the structure during the manufacture of the semiconductor device, subsequent to the step shown inFIG. 1 . As shown inFIG. 2 , a resist pattern covering regions other than the source region is formed over the main surface of thesubstrate 1 ofFIG. 1 , after which arsenic, for example, is ion implanted into the main surface of thesubstrate 1 through the mask of the resist pattern to form an n-type semiconductor region (second semiconductor region) 9 for the source on the surface layer of thesemiconductor layer 1 b betweenadjacent gate electrodes 7. Subsequently, an insulatingfilm 10, that is made, for example, of silicon oxide or the like, is deposited over the main surface of thesemiconductor layer 1 b of the substrate (wafer) 1 by a CVD (Chemical Vapor Deposition) method, followed by formation of a photoresist pattern (hereinafter referred to as a resist pattern) thereon, so that the outer peripheral region of the power MIS-forming region is covered therewith, but others are exposed. In this condition, the insulatingfilm 10 on thesubstrate 1 is etched back using an anisotropic dry etching technique to form therespective electrodes 7 at the power MIS-forming region and side walls (second insulating films) 10 a at the side surfaces of thecap insulating films 8, along with an insulatingfilm 10 b being formed around the power MIS-forming region. - Subsequently, as shown in
FIG. 3 , thecap insulating films 8,side walls 10 a and insulatingfilm 10 b are used as an etching mask to etch the exposed portions of thesemiconductor layer 1 b using a dry etching technique, so as to form grooves (second grooves) 11. Therespective grooves 11 extend from the main surface of thesemiconductor layer 1 b to an intermediate position along the depth of thesemiconductor region 2, as viewed in section, and they also extend along a given direction, as viewed in plane view. Thereafter, boron difluoride (BF2), for example, is ion implanted into thesemiconductor layer 1 b at 80 keV and about 3×1015 cm−2, thereby forming a p+-type semiconductor region (third semiconductor region) 12 at the bottom of thegroove 11. -
FIG. 4 is a sectional view of the structure during the manufacture of the semiconductor device, subsequent to the step shown inFIG. 3 .FIG. 5 is an enlarged, sectional view of region A inFIG. 4 . In this step, thesubstrate 1 is subjected to wet etching to slightly etch the exposed surface portions of the insulatingfilm 10 and thegate insulating film 6 in such a way that the side surface of theside wall 10 a is recessed from the side surface of thegroove 11. In this way, part of the main surface of thesemiconductor layer 1 b around the opening of thegroove 11 is exposed. This contributes to an increase in the contact area between the source electrode and thesemiconductor source region 9 a. The above-mentioned etching permits a groove (second groove) 13 to be formed, which groove is located above and is wider than thegroove 11 and runs into thegroove 11. - As shown in
FIG. 5 , the total depth D1 of thegrooves groove 11 is, for example, 0.4 μm. The depth D3 of thegroove 13 is, for example, about 0.8 μm, and the width D4 of thegroove 11 is, for example, about 0.5 to 0.6 μm. In this connection, however, the wiring formation method ofEmbodiment 1, as described hereinafter, may also be applied to the case where no etching is carried out for the purpose of the formation of thegroove 13, i.e., the case of a structure wherein thegroove 13 is so arranged that its width is not larger than, but is equal to that of, thegroove 11. After completion of the etching, ordinary photolithographic and dry etching techniques using a resist pattern as a mask are performed to form acontact hole 14, so that part of theextrinsic gate wiring 7L is exposed at the insulatingfilm 10 b and thecap insulating film 8. -
Such grooves deep grooves substrate 1 proceeds, with the attendant problem that a junction failure takes place at the channel portion of the power MIS. On the other hand, there is a problem as to how thegrooves Embodiment 1. -
FIG. 6 is a flow chart of the process for burying thegrooves FIG. 4 in the course of the manufacture of the semiconductor device, according to the respective steps of the flow chart ofFIG. 6 . - As shown in
FIG. 7 , a conductor film (first conductor film) 15 a is deposited on the main surface of the substrate (wafer) 1 (step 100 inFIG. 6 ). This permits athin conductor film 15 a to be deposited on the inner surfaces (inner wall surfaces and bottom surface) of thegrooves FIG. 4 ), so that thegrooves contact hole 14 are not buried completely. Thisconductor film 15 a has a barrier function for suppressing or preventing the aluminium used as a main wiring material, as will be described hereinafter, from diffusing into the aluminium film side, and it also prevents the silicon of thesemiconductor layer 1 b from diffusing into the side of the aluminium film used as the main wiring material. Especially, inEmbodiment 1, if the reflow of aluminium, as will be described hereinafter, is carried out at high temperatures, for example, 400° C. or over, theconductor film 15 a is considered to provide a structure (from the aspects of material, thickness, function and the like) that is capable of suppressing or preventing a reaction from occurring between the aluminium used as a main wiring material and the silicon in thesemiconductor layer 1 b. - According to our studies, it has been found that where titanium (Ti) is selected as a material for the
conductor film 15 a, the resultant titanium film is converted to a silicide thereof substantially entirely along the thickness direction thereof when subjected to annealing after the deposition thereof. Eventually, when aluminium used as a main wiring material is deposited and subjected to reflow treatment at high temperatures (400° C. or over), the reaction between the aluminium and the silicon proceeds, thus leading to a junction leakage failure at the channel portion of power MIS. In order to suppress or prevent a reaction from occurring between the aluminium and the silicon, as mentioned above, theconductor film 15 a should be made of a high heat resistance material, which is not converted into a silicide entirely along the thickness of theconductor film 15 a by annealing subsequent to the deposition of theconductor film 15 a. In other words, theconductor film 15 a is so selected as to provide a structure wherein the silicide layer is formed only at a portion in contact with thesemiconductor layer 1 b; and, thus, theconductor film 15 a is interposed between the silicide layer and the aluminium film that is used as a main wiring material in order to prevent direct contact between the silicide layer and the aluminium that is used as a main wiring material. In this manner, if the thermal treatment temperature of the aluminium that is used as a main wiring material, as will be described hereinafter, is made high, the reaction between the aluminium and the silicon in thesubstrate 1 can be suppressed or prevented by means of theconductor film 15 a. Accordingly, the main wiring material of aluminium can be thermally treated at high temperatures, and, thus, thegrooves - As a specific material for the
conductor film 15 a, a number of materials could be selected, of which titanium tungsten (TiW) is most preferred. Titanium tungsten has favorable properties in that it exhibits a low reactivity with silicon, is thermally stable and low in heat resistance, and is low in contact resistance and electrical resistance, because this material is a kind of metal. Where titanium tungsten is selected as a material for theconductor film 15 a, its thickness is, for example, at about 200 nm. It will be noted that the “thickness” of theconductor film 15 a refers to a design thickness (which is substantially equal to the thickness of theconductor film 15 a that is deposited on the upper surface of thecap insulating film 8 and the insulatingfilm 10 b). The thickness of theconductor film 15 a attached on the side walls and the bottom surfaces of thegrooves - Other types of materials for the
conductor film 15 a include, for example, high-melting metals, such as tungsten (W), tantalum (Ta) and the like. In this case, they are high in heat resistance and are low in contact and electrical resistances, because of the nature of the metal thereof. Further types of materials for theconductor film 15 a include, for example, high melting metal nitride films, such as a titanium tungsten nitride film (TiWN), a tungsten nitride film (WN), a tantalum nitride film (TaN) and the like. Still further types of materials for theconductor film 15 a include, for example, tungsten silicide (WSi2) and a nitride thereof (WSiN). Where tungsten suicide (WSi2) or its nitride (WSiN) is selected, silicon is present in theconductor film 15 a. The bonding between tungsten and silicon is stronger than the bonding between aluminium and silicon, so that the reactivity between aluminium and silicon becomes low. As a result, substantially similar effects are obtained as in the case where titanium tungsten is selected. Using such materials as indicated above or other types of materials as theconductor film 15 a, proper control of the thickness of theconductor film 15 a may cause such action and effect as set out hereinabove. - Next, the substrate (wafer) 1 is annealed in an atmosphere of an inert gas, such as, for example, nitrogen gas (N2) or the like, at 650° C. for about 30 minutes (
step 101 inFIG. 6 ). As shown inFIG. 8 , this permits a very thin silicide layer (compound layer) 15 b, that is made, for example, of titanium silicide (TiSi2) or the like, to be formed at the interface of the contact surface of theconductor film 15 a with thesemiconductor layer 1 b and theextrinsic gate wiring 7L (seeFIG. 4 ). - In
Embodiment 1, theconductor film 15 a is not wholly converted to a silicide, as mentioned above, but thesilicide layer 15 b is formed only at the interface portion of contact between theconductor film 15 a and thesemiconductor layer 1 b, with theconductor layer 15 b being left at the upper layer or portion thereof. The contact resistance between the source electrode and the semiconductor region for the source, to be described hereinafter, can be reduced through the formation of such asilicide layer 15 b, thus enabling the ON resistance of the power MID to be reduced. This treatment likewise can be carried out for the case where theconductor film 15 a is made of a material other than titanium tungsten. In this case, a silicide layer is formed only at a contact portion between theconductor film 15 a and thesemiconductor layer 1 b, like the case using titanium tungsten, with theconductor film 15 a being left at an upper layer relative to the silicide layer. - Subsequently, as shown in
FIG. 9 , a conductor film (second conductor film) 15 c made of a high-melting metal film, such as titanium (Ti) or the like, is deposited, for example, to a design thickness of about 50 nm by a sputtering method (seestep 102 inFIG. 6 ). In doing so, theconductor film 15 c is so attached as to cover the surface of theconductor film 15 a at the inner surface (including the inner wall surfaces and bottom surfaces) of thegrooves contact hole 14 without fully burying thegrooves FIG. 4 ) therewith. Thisconductor film 15 c has the functions of improving the wettability of an aluminium film to be subsequently deposited and suppressing or preventing aluminium and silicon from reacting with each other. Theconductor film 15 formed of the above-statedconductor films - Next, as shown in
FIG. 10 , a conductor film that is made, for example, of aluminium (an aluminium-based conductor film made mainly of aluminium or a first aluminium-based conductor film made mainly of aluminium) 16 a is deposited on the main surface of the substrate (wafer) 1 by a sputtering method (step 103 inFIG. 6 ). Thisconductor film 16 a serves as an underlying film having the function of ensuring the continuity of an aluminium film to be formed in a subsequent deposition procedure of hot aluminium, and it is formed as a film at a low temperature (e.g. a normal temperature: 30° C.). - More particularly, when an aluminium film is deposited, under high temperature conditions, on the
conductor film 15 c that is made of titanium or the like, small lumps of aluminium are formed on the surface of theconductor film 15 c, thus not ensuring the continuity of the aluminium film. In order to establish the continuity of an aluminium film, aconductor film 16 a that is made of an aluminium film is formed under low temperature conditions prior to the formation of an aluminium film under high temperature conditions. - The thickness of the
conductor film 16 a is at a level sufficient to bury thegroove 11 of a relatively small width, and, more particularly, at such a level that the portion of theconductor film 15 c is not exposed at the corner (i.e. a portion formed at the intersection between the main surface of thesemiconductor layer 1 b and the side surface of the groove 11) of thesemiconductor layer 1 b around the opening of thegroove 11. This is provided for the reason that, if part of theconductor film 15 c is exposed, the continuity of a subsequently deposited aluminium film cannot be ensured. The design thickness of theconductor film 16 a formed in this way is, for example, at about 400 nm. At this stage, theconductor film 16 a is in such a state as to be attached through thethin conductor films grooves contact hole 14 without completely burying thegroove 13 and the contact hole 14 (FIG. 4 ) therewith. - After the deposition of the
conductor film 16 a, the substrate (water) 1 is annealed, as shown inFIG. 11 , within a sputtering apparatus wherein theconductor film 16 a has been deposited, thereby causing theconductor film 16 a to be made to reflow (seestep 104 inFIG. 6 ). In this manner, theconductor film 16 a is made to flow and run into thegrooves Embodiment 1. More particularly, annealing is carried out, for example, at 450° C. for several minutes. This enables the reflow property of the aluminium to be improved. More particularly, a great quantity of aluminium is charged or caused to run into thegrooves grooves grooves - As stated hereinabove, in
Embodiment 1, theconductor 15 a is formed so that even if the annealing temperature is set at a level, for example, of higher than 400° C., the reaction between the aluminium and the silicon in thesemiconductor layer 1 b can be suppressed or prevented. Thus, the occurrence of junction failure at the channel portion of the power MIS ascribed to the reaction can be suppressed or prevented, with the possibility of improved yield and increased reliability of the power MIS. - At this stage, the
conductor film 16 a does not completely bury thegrooves FIG. 4 ) therewith, but is in a state of being attached to the inner surfaces (i.e. the inner wall surfaces and bottom surfaces) of thegrooves contact hole 14 through thethin conductor films conductor film 16 a within thegroove 13. Thereafter, a conductor film (second aluminium-based conductor film) 16 b made, for example, of aluminium or the like is deposited, as shown inFIG. 12 , by a sputtering method at a low rate within the same sputtering apparatus as used for the deposition of theconductor film 16 a (step 105 inFIG. 6 ). At this time, theconductor 16 b is deposited while heating the substrate (wafer) 1 from the back side thereof (so-called heat sputtering). In this way, theconductor films grooves conductor film 16 a can be obtained. - The deposition rate of the
conductor film 16 b should be lower than the deposition rate of an aluminium film to be subsequently deposited. This is because the recessed portion in thegroove 13 is well buried with theconductor film 16 b, while ensuring the continuity of theconductor film 16 b. The deposition rate of theconductor film 16 b is, for example, 0.4 μm per unit time (of about several minutes). The design thickness of theconductor film 16 b that is deposited at this stage is about half of the width D3 (seeFIG. 5 ) of thegroove 13, and it is particularly, for example, about 400 nm. This permits the remaining recess in thegroove 13 to be substantially completely buried with theconductor film 16 b. It will be noted that, although a boundary line between theconductor films FIG. 12 , this indication is provided only for the sake of ease in viewing the drawing, and such a boundary line is not actually formed. - Thereafter, as seen in
FIG. 13 , a conductor film (second aluminium-based conductor film) 16 c, that is made, for example, of aluminium or the like, is deposited on the main surface of the semiconductor substrate (wafer) 1 at a high rate according to a sputtering method within the same sputtering apparatus as used for the deposition of theconductor film 16 b (step 106 inFIG. 6 ). In this case, theconductor film 16 c is deposited while heating the substrate (wafer) 1 from the back side thereof. The heating temperature is set, for example, at a level of higher than 400° C., and, it is particularly, for example, about 450° C. In this way, similar effects as in the case of theconductor films - The deposition rate of the
conductor film 16 c is made higher than the deposition rate of theconductor film 16 b. This is for the reason that, at this stage, thegroove 13 is substantially completely buried with theconductor film 16 b, so that priority is put on the shortage in deposition time of the aluminium film over the burying property and continuity of the groove being ensured, thereby improving the throughput. The deposition rate of theconductor film 16 c is, for example, about 4.1 μm per unit time (of about several minutes, which is the same as the unit time for the deposition rate of theconductor film 16 b). The thickness of theconductor film 16 c deposited that is deposited at this time should be sufficient to lower the ON resistance of the power MIS and is particularly as thick as about 4.1 μm, for example. - The conductor film formed of the thus deposited
conductor films grooves FIG. 4 ) are, respectively, buried with theconductor film 16 to a full extent. - According to this
Embodiment 1, the aluminium-basedconductor film 16 that is made mainly of aluminium can be buried in thegrooves - If the
grooves such grooves conductor film 16. Thus, the microfabrication of thegrooves conductor films FIG. 13 , such indication is provided only for the sake of ease in viewing the drawing, and these boundary lines are not formed actually. -
FIG. 14 is a sectional view of the structure in the manufacture of the semiconductor device, subsequent to the step shown inFIG. 13 . In this step, theconductor films gate electrode 17 and asource electrode 18, each having theconductor films substrate 1. Thegate electrode 17 is electrically connected to theextrinsic gate wiring 7L via thecontact hole 14, and the source electrode is electrically connected to thesemiconductor regions semiconductor layer 1 b via thegrooves - After deposition of a surface protective film on the main surface of the
substrate 1, a bonding area thereof is removed by etching to form a bonding pad. Thereafter, the substrate (wafer) 1 is polished on the back surface thereof, and a drain electrode is formed at the back surface. Subsequently, a semiconductor device having a power MIS is manufactured through an ordinary assembling procedure of the semiconductor device. This power MIS is so arranged that, in a state where a positive voltage is applied to the drain electrode and a ground voltage (0 V) is applied to thesource electrode 18, the power MIS commences to work when a positive voltage is applied to thegate electrode 17 from a state where thegate electrode 17 has been supplied with the ground voltage and, thus, does not work. When a positive voltage is applied to thegate electrode 17, an inversion layer (n-channel) is formed in the p−-type semiconductor region 2, under which the n-type semiconductor region 9 for the source and the semiconductor layers 1 a and 1 b for the drain are connected through the inversion layer. As a result, electrons pass from thesource electrode 18 to the drain electrode at the back surface of thesubstrate 1 via the n-type semiconductor region 9, inversion layer,semiconductor layer 1 b andsemiconductor layer 1 a on the main surface of thesubstrate 1. More particularly, an electric current passes from the drain electrode to thesource electrode 18, so that the power MIS is turned on. In this way, the drain current of the power MID runs along the thickness of the substrate. On the other hand, when the gate voltage is changed from a positive voltage to a ground or negative voltage, the above-mentioned inversion layer disappears, so that no electric current passes between the n-type semiconductor region 9 and the semiconductor layers 1 a, 1 b, rendering the power MIS off. - (Embodiment 2)
- In
Embodiment 2, an application to a Damascene wiring formation technique is illustrated with reference to FIGS. 15 to 18.FIG. 15 is a plan view of the structure in the manufacture of a semiconductor device ofEmbodiment 2, andFIG. 16 is a section taken along the line X1-X1 inFIG. 15 .FIGS. 17 and 18 are, respectively, a sectional view of the device at a portion corresponding to the line X1-X1 ofFIG. 15 in the course of the manufacture of the semiconductor device subsequent to the step shown inFIG. 16 . - As shown in
FIGS. 15 and 16 , a MISFET (hereinafter referred to simply as MIS) Q is formed, for example, at an active region surrounded by anisolation portion 4 on the main surface of a substrate (wafer) 1. Thesubstrate 1 is not made of an epitaxial wafer, but is made of an ordinary semiconductor wafer. Theisolation portion 4 has a so-called trench isolation structure, wherein it is formed by burying an insulating film in a groove made in the main surface of thesubstrate 1. MIS Q has source and drainsemiconductor regions 20 formed in the main surface of thesubstrate 1, agate insulating film 21 formed on the main surface of thesubstrate 1, and agate electrode 22 formed thereon. - The
semiconductor region 20 is formed by introducing, for example, arsenic (As) or phosphorus (P), if MIS Q is an n-channel device, and it is formed by introducing, for example, boron (B) or boron difluoride (BF2) for a MIS Q that is a p-channel device. Thegate insulating film 21 is made, for example, of a silicon oxide film, a silicon oxynitride film or a builtup structure of a silicon oxide film and a silicon nitride film. Thegate electrode 22 is made, for example, of a single film structure of a polysilicon film of low resistance, a so-called polycide structure wherein a silicide film is formed on a low resistance polysilicon film, or a so-called polymetal structure wherein a metal film is provided on a low resistance polysilicon film through a barrier conductor film. - The
substrate 1 has deposited, on the main surface thereof, an insulating film made, for example, of a silicon oxide film, so as to cover the MIS Q therewith. This insulatingfilm 23 is formed with a wiring groove (opening for wiring) 23 a and a contact hole (opening for wiring) 24 b reaching the main surface of thesubstrate 1 from the bottom. As viewed in plane view, as shown inFIG. 15 , thewiring groove 24 a is formed as a band-shaped pattern extending in vertical directions ofFIG. 15 . On the other hand, as viewed in section, as shown inFIG. 16 , thegroove 24 a is formed as a rectangular groove having a depth extending to an intermediate position along the thickness of the insulatingfilm 23. Thecontact hole 24 b, as viewed in plane view, as shown inFIG. 15 , is formed as a circular pattern whose diameter is smaller than the width (minor size) of thewiring groove 24 a, and part (part of thesemiconductor regions 20 for source and drain) of the main surface of thesubstrate 1 is exposed from the bottom of thecontact hole 24 b. As viewed in section, as shown inFIG. 16 , thecontact hole 24 b is formed in such a state as to extend from the bottom surface of thewiring groove 24 a to the main surface of thesubstrate 1. - As shown in
FIG. 17 , aconductor film 15 and aconductor film 16 are successively deposited in order from the lower layer on the main surface of thesubstrate 1 in the same manner as in the foregoingEmbodiment 1. Theconductor films Embodiment 1. InEmbodiment 2, theconductor film 16 can be well buried in thewiring groove 24 a and thecontact hole 24 b in a space-free condition, likeEmbodiment 1, and deposited while ensuring the continuity thereof. Subsequently,additional conductor films wiring 25 having theconductor films wiring groove 24 a and thecontact hole 24 b. - (Embodiment 3)
- In
Embodiment 3, an application to a buried electrode (plug) formation technique is illustrated with reference to FIGS. 19 to 22.FIG. 19 is a plan view of the structure in the course of the manufacture of a semiconductor device ofEmbodiment 3, andFIG. 20 is a sectional view taken along the line X2-X2 ofFIG. 19 .FIGS. 21 and 22 are, respectively, a sectional view of the device at a portion corresponding to the line X2-X2 ofFIG. 19 in the course of the manufacture of the semiconductor device, subsequent to the step shown inFIG. 19 . - As shown in
FIGS. 19 and 20 , an insulatingfilm 26 that is made, for example, of a silicon oxide film or the like is deposited on the main surface of a substrate (wafer) 1. This insulatingfilm 26 has formed therein a contact hole (opening for wiring) 24 b of a circular form, as seen in plane view, that reaches the main surface of thesubstrate 1. As shown inFIG. 21 ,conductor films substrate 1, like the foregoingEmbodiments conductor films Embodiments Embodiment 3, theconductor film 16 can be well buried in thecontact hole 24 b in a space-free condition and deposited while ensuring the continuity thereof, likeEmbodiments additional conductor films conductor films contact hole 24 b, as shown inFIG. 22 . - (Embodiment 4)
- In
Embodiment 4, a modification of the foregoingEmbodiment 3 is illustrated.FIG. 23 is a sectional view of the structure in the course of the manufacture of a semiconductor device ofEmbodiment 4. Initially, after carrying out the steps of FIGS. 19 to 21 with respect to the foregoingEmbodiment 3, theconductor films FIG. 21 are, respectively, patterned through use of a resist pattern as an etching mask according to ordinary photolithographic and dry etching techniques to formwirings 28 having theconductor films film 26, as shown inFIG. 23 . Thewirings 28 are electrically connected to thesemiconductor regions 20 for the source and drain of MIS Q through the contact holes 24 b, respectively. - Although various embodiments of the invention which has been made by us have been particularly described hereinabove, the invention should not be construed as being limited to these embodiments, and many modifications and changes may be possible without departing from the spirit of the invention.
- For instance, although an application to a n-channel power MID has been described by way of example in connection with the foregoing
Embodiment 1, the invention is not limited to this case, but may be applied to a p-channel power MIS. - Further, application to a power MIS having a trench gate electrode structure has been described by way of example in connection with
Embodiment 1, but the invention is not limited to this application, and may be applied to a power MID having a transverse gate electrode structure formed on the main surface of the substrate. - Moreover, the
annealing step 104 inFIG. 6 may be omitted. More particularly, after deposition of theconductor film 16 a made of aluminium or the like according to the low temperature sputtering method as employed by way of example inEmbodiment 1, theconductor films Embodiment 1. Additionally, thesteps FIG. 6 may be omitted in some cases. More particularly, theconductor film 16 a that is made of aluminium or the like may be deposited using a low temperature sputtering method inEmbodiment 1, followed by annealing (step 104 inFIG. 6 ) in the same manner as inEmbodiment 1, thereby causing grooves or holes to be buried with theconductor film 16 a made of aluminium or the like. - In the foregoing, applications to the manufacturing method of a semiconductor device having a power MIS, which is in the field of utility to which the present invention is directed, have been described, but the invention should not be construed as being limited only to these applications, but it may be applied, for example, to the manufacture of a semiconductor device having an IGBT (Insulated Gate Bipolar Transistor) with a trench gate electrode structure. More particularly, the invention is applicable to the technique of forming a base electrode and an emitter electrode of an IGBT, each made of aluminium or the like. Alternatively, the invention is also applicable to a power IC (integrated circuit) wherein cell arrays, which respectively have a plurality of transistor cells, each made of a transistor having a trench gate electrode structure and control circuits, are mixed in the same substrate.
- The effects of typical embodiments according to the invention will be summarized below.
- A first conductor film, which has a structure capable of suppressing or preventing the reaction between aluminium atoms and constituent atoms in a semiconductor substrate upon re-melting or thermal treatment of the conductor film made mainly of aluminium, is deposited on the semiconductor substrate, including openings for wiring. Thereafter, the conductor film made mainly of aluminium flows and is charged into the openings for wiring through a thermal treatment for re-melting after or during the deposition of the conductor film, thus making it possible to suppress or prevent a junction failure from occurring. This eventually leads to improved reliability of the resultant semiconductor device.
Claims (9)
1. A semiconductor device including a plurality of MISFETs, comprising:
a semiconductor substrate having a first conductivity type, serving as a drain of the plurality of MISFETs;
a channel-forming region of the plurality of MISFETs, having a second conductivity type opposite to the first conductivity type, formed over the semiconductor substrate;
a plurality of sources of the plurality of MISFETs, having the first conductivity type, formed over the channel-forming region;
a plurality of trenches formed on a main surface of the semiconductor substrate and reaching the semiconductor substrate;
a plurality of gate insulating films of the plurality of MISFETs, formed on an inner wall of the plurality of trenches;
a plurality of gates of the plurality of MISFETs, formed on the plurality of gate insulating films, wherein the plurality of gates are electrically connected;
an interlayer insulating film formed over the plurality of gates;
a source electrode, electrically connected with the plurality of source regions, formed over the interlayer insulating film;
a drain electrode, electrically connected with the semiconductor substrate, formed on a back surface of the semiconductor substrate;
wherein the plurality of gates are electrically connected;
a plurality of contact holes exposing the plurality of the sources and the channel-forming region, formed in the interlayer insulating film; and
a plurality of conductive plugs buried in the plurality of contact holes, wherein the plurality of sources and the source electrode are electrically connected via the plurality of conductive plugs.
2. A semiconductor device according to claim 1 , wherein a plurality of grooves under the plurality of contact holes are formed in the main surface of the semiconductor substrate; wherein each of the grooves are formed between the adjacent sources; wherein each of the grooves and contact holes are connected; and wherein the plurality of plugs are buried in the plurality of grooves.
3. A semiconductor device according to claim 2 , wherein side surfaces of the sources and the plugs in the grooves are contacted.
4. A semiconductor device according to claim 1 , wherein the plurality of plugs are formed by:
forming a conductive film in the plurality of contact holes and on a main surface of the interlayer insulating film; and
removing a part of the conductive film, formed on the main surface of the interlayer insulating film, using a CMP method.
5. A semiconductor device according to claim 1 , wherein the plurality of MISFETs comprise a power MISFET.
6. A semiconductor device according to claim 1 , wherein the semiconductor substrate is comprised of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer; and wherein the second semiconductor layer is formed by an epitaxial growth method.
7. A semiconductor device according to claim 1 , wherein the first and second conductivity types are n-type and p-type, respectively.
8. A semiconductor device according to claim 1 , wherein an extrinsic gate wiring is formed over the main surface of the semiconductor substrate; wherein the plurality of gates are electrically connected with the extrinsic gate wiring; and wherein the extrinsic gate wiring and the plurality of gates are made of a same layer.
9. A semiconductor device according to claim 8 , wherein a gate electrode is formed over the extrinsic gate wiring; wherein the gate electrode and the extrinsic gate wiring are electrically connected; and wherein the gate electrode and the source electrode are made of a same layer.
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US6872653B2 (en) | 2005-03-29 |
US20030199156A1 (en) | 2003-10-23 |
JP2003318395A (en) | 2003-11-07 |
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