US20050145919A1 - [multi-level memory cell] - Google Patents
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- US20050145919A1 US20050145919A1 US10/707,677 US70767704A US2005145919A1 US 20050145919 A1 US20050145919 A1 US 20050145919A1 US 70767704 A US70767704 A US 70767704A US 2005145919 A1 US2005145919 A1 US 2005145919A1
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- 239000000758 substrate Substances 0.000 claims abstract description 39
- 230000005641 tunneling Effects 0.000 claims abstract description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 25
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 25
- 125000006850 spacer group Chemical group 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 230000005684 electric field Effects 0.000 abstract description 11
- 238000000034 method Methods 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000002131 composite material Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000013500 data storage Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
Definitions
- the present invention relates to a semiconductor device. More particularly, the present invention relates to a multi-level memory cell.
- Electrically erasable programmable read-only memory is a type data storage device that allows multiple data writing, reading and erasing operations. In addition, the stored data will be retained even after power to the device is removed. With these advantages, it has been broadly applied in personal computers and electronic equipment.
- a typical EEPROM has a floating gate and a control gate fabricated using doped polysilicon.
- the electrons When electrons are injected into the floating gate during a programming operation, the electrons distribute evenly within the polysilicon floating gate layer. However, if the tunneling oxide layer underneath the polysilicon floating gate layer contains some defects, a leakage current may flow from the device and compromise the reliability of the device.
- an EEPROM with a stacked gate structure having an oxide/nitride/oxide (ONO) composite layer known as a SONOS read-only memory is currently used.
- the silicon nitride layer replaces the polysilicon floating gate as the charge-trapping layer. Because electrons are injected into the silicon nitride layer mainly through a localized region, the leakage current is less sensitive to any defects in the tunneling oxide layer.
- FIG. 1 is a schematic cross-sectional view of a conventional SONOS read-only memory (ROM) cell.
- the SONOS ROM cell includes a substrate 100 , a composite layer 114 that includes a silicon oxide layer 102 , a silicon nitride layer 104 and a silicon oxide layer 106 (ONO), a gate 108 , a pair of spacers 110 , a channel 118 and a pair of source/drain regions 112 .
- the silicon oxide layer 102 , the silicon nitride layer 104 and the silicon oxide layer 106 constituting the composite layer 114 are sequentially formed over the substrate 100 .
- the gate 108 is formed over the composite layer 114 .
- the gate 108 and the composite layer 114 together form a gate structure 116 .
- the spacers 110 are positioned on the sidewalls of the gate structure 116 .
- the source/drain regions 112 are formed in the substrate 100 on each side of the gate structure 116 .
- the channel 118 is formed in an area underneath the silicon oxide layer 102 between the source/drain region 112 .
- the so-called Fowler-Nordheim tunneling effect is utilized.
- a voltage is applied to the gate 108 so that a large electric field is setup between the gate 108 and the substrate 100 .
- the electric field induces the electrons in the substrate 100 to inject from the channel 118 through the tunneling dielectric layer 102 into the charge-trapping layer 104 , thereby increasing the threshold voltage of the transistor. In this way, a single bit of data is programmed into a memory cell.
- At least one objective of the present invention is to provide a multi-level memory cell with a larger memory capacity.
- the invention provides a multi-level memory cell.
- the multi-level memory cell includes a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions.
- the tunneling dielectric layer, the charge-trapping layer and the top dielectric layer made from silicon oxide, silicon nitride and silicon oxide material respectively are sequentially formed over the substrate.
- the tunneling dielectric layer has a thickness between 20 ⁇ to 40 ⁇ so that charges may tunnel from the substrate into the charge-trapping layer through the Fowler-Nordheim tunneling effect.
- the charge-trapping layer has a thickness between 40 ⁇ to 60 ⁇ for capturing and holding charges.
- the top dielectric layer has at least two portions with each portion having a different thickness.
- a voltage is applied to the gate, different electric field strength is set up between the gate and the substrate in each portion. With different electric field strength in each portion, the amount of charges that can be accommodated within the charge-trapping layer will be different. Therefore, a single memory cell can register multiple data bits.
- the tunneling dielectric layer, the charge-trapping layer and the top dielectric together with the gate form a gate structure.
- spacers are formed on the sidewalls of the gate structure.
- the spacers are fabricated using an insulating material such as silicon oxide.
- the source/drain regions are formed in the substrate on each side of the gate structure.
- each memory cell can be activated by a group of different threshold voltage values so that multiple data bits are registered. In other words, the storage capacity of each memory cell is increased.
- FIG. 1 is a schematic cross-sectional view of a conventional SONOS read-only memory (ROM) cell.
- FIGS. 2A through 2F are schematic cross-sectional views showing the steps for fabricating a multi-level memory cell according to one preferred embodiment of this invention.
- FIG. 3 is a schematic cross-sectional view of a multi-level memory cell according to another preferred embodiment of this invention.
- FIGS. 2A through 2F are schematic cross-sectional views showing the steps for fabricating a multi-level memory cell according to one preferred embodiment of this invention.
- a substrate 200 such as a P-type semiconductor substrate is provided.
- a tunneling dielectric layer 202 having a thickness between 20 ⁇ to 40 ⁇ is formed over the substrate 200 .
- the tunneling dielectric layer 202 is a silicon oxide layer formed, for example, by performing a chemical vapor deposition process. Since the tunneling dielectric layer 202 is fabricated using silicon oxide material, the tunneling dielectric layer 202 is also referred to as a bottom oxide layer.
- a charge-trapping layer 204 having a thickness between 40 ⁇ to 60 ⁇ is formed over the tunneling dielectric layer 202 , for example, by performing a chemical vapor deposition process.
- the charge-trapping layer 204 is fabricated using silicon nitride or other materials that have a charge trapping capability.
- a top dielectric layer 206 is formed over the charge-trapping layer 204 , for example, by performing a chemical vapor deposition process using silicon oxide. Since the top dielectric layer 206 is fabricated using silicon oxide as material, the top dielectric layer 206 is also referred to as a top oxide layer. The top dielectric layer 206 is divided into a plurality of portions. Two portions labeled A and B are shown in FIG. 2B . Thereafter, a etching back process or a repetition of the chemical vapor deposition process is carried out so that the top dielectric layer 206 has different thickness in portion A and portion B.
- a doped polysilicon layer 208 is formed over the top dielectric layer 206 .
- the doped polysilicon layer 208 is formed, for example, by performing a chemical vapor deposition process to form a polysilicon layer (not shown) over the top dielectric layer 206 and then implanting dopants into the polysilicon layer. Alternatively, the dopants are added in-situ with the polysilicon deposition. In general, P-type or N-type dopants may be implanted according to the particular fabrication process.
- a photolithographic and etching process is carried out to pattern out a gate structure 216 .
- the gate structure 216 includes a patterned tunneling dielectric layer 202 a , a charge-trapping layer 204 a , a top dielectric layer 206 a and a gate 208 a .
- the top dielectric layer 206 a includes the portions A and B. Furthermore, the top dielectric layer 206 a has a different thickness in portion A and B. In other words, the top dielectric layer 206 a has parts with different thickness.
- an ion implantation is carried out using the gate structure 216 as a mask to form lightly doped regions 214 in the substrate 200 .
- spacers 210 are formed on the sidewalls of the gate structure 216 .
- the spacers 210 are silicon oxide layers formed, for example, by performing a chemical vapor deposition process to form a conformal silicon oxide layer (not shown) over the substrate 200 and covering the gate structure 216 and then performing an anisotropic etching operation.
- a doping operation is carried out using the spacers 210 as a mask to form heavily doped regions 218 in the substrate 200 .
- a multi-level memory cell is formed.
- the heavily doped region 218 and the lightly doped region 214 together constitute a source/drain region 212 .
- the doping operation includes an ion implantation, for example.
- FIG. 2F shows a fully formed multi-level memory cell according to this invention.
- the multi-level memory cell includes a substrate 200 , a tunneling dielectric layer 202 a , a charge-trapping layer 204 a , a top dielectric layer 206 a , a gate 208 a , a pair of spacers 210 and a pair of source/drain regions 212 .
- the tunneling dielectric layer 202 a , the charge-trapping layer 204 a and the top dielectric layer 206 a made from silicon oxide, silicon nitride and silicon oxide material respectively are sequentially formed over the substrate 200 .
- the tunneling dielectric layer 202 a has a thickness between 20 ⁇ to 40 ⁇ .
- the tunneling dielectric layer 202 a is a layer that facilitates the tunneling of charges from the substrate 200 into the charge-trapping layer 204 a through the Fowler-Nordheim tunneling effect.
- the charge-trapping layer 204 a having a thickness between 40 ⁇ to 60 ⁇ is used for capturing and holding electric charges.
- the tunneling dielectric layer 202 a , the charge-trapping layer 204 a and the top dielectric layer 206 a together constitute a gate structure 216 .
- the spacers 210 are formed on the sidewalls of the gate structure 216 .
- the spacers 210 are fabricated using an insulating material including silicon oxide, for example.
- the source/drain regions 212 are located in the substrate 200 on each side of the gate structure 216 .
- the top dielectric layer 206 a is divided into portion A and portion B. Since the top dielectric layer 206 a in portion A has a thickness that differs from the one in portion B, the electric field strength between the gate 208 a and the substrate 200 are different in these two portions. Hence, the electric field strength inside the charge-trapping layer 204 a is different due to a different thickness in the top dielectric layer 206 a between these two portions.
- the memory cell When the memory cell is activated, charges are injected from the substrate 200 into the charge-trapping layer 204 a via the tunneling dielectric layer 202 a due to the Fowler-Nordheim effect. The injected charges are retained within the charge-trapping layer 204 a .
- the amount of charges injected into the charge-trapping layer 204 a is related to the electric field strength.
- the electric field strength between the gate 208 a and the substrate 200 in the portion with a thinner top dielectric layer 206 a is greater. Therefore, more charges will tunnel through the tunneling dielectric layer 202 a into the charge-trapping layer 204 a .
- the electric field strength between the gate 208 a and the substrate 200 in the portion with a thicker top dielectric layer 206 a is smaller. Therefore, less charges will tunnel through the tunneling dielectric layer 202 a into the charge-trapping layer 204 a . Consequently, the amount of charges trapped within the charge-trapping layer of each portion is different so that a single memory cell can hold a multiple of data bits.
- two different threshold voltages can be used to activate a single memory cell.
- the top dielectric layer inside each multi-level memory cell according to this invention can be divided into a multiple of portions.
- the aforementioned embodiment has two portions with different thickness, there is no restriction on the number of portions in the top dielectric layer.
- FIG. 3 is a schematic cross-sectional view of a multi-level memory cell according to another preferred embodiment of this invention. All the elements in FIG. 3 identical to the aforementioned embodiment are labeled identically. Since the materials and method of fabrication are mostly identical to the aforementioned embodiment, detailed description is omitted.
- the top dielectric layer 206 a has three portions A, B and C with the top dielectric layer 206 a inside each portion having a different thickness.
- the electric field strength between the gate and the substrate corresponding to the portion A, B and C are all different.
- the amount of charges trapped within the charge-trapping layer in each portion is different.
- three different threshold voltages can be used to activate a single memory cell. Therefore, the storage capacity of each memory cell is further increased.
- each memory cell can be activated by a group of different threshold voltage values so that multiple data bits are registered. In other words, the storage capacity of each memory cell is increased.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device. More particularly, the present invention relates to a multi-level memory cell.
- 2. Description of the Related Art
- Electrically erasable programmable read-only memory (EEPROM) is a type data storage device that allows multiple data writing, reading and erasing operations. In addition, the stored data will be retained even after power to the device is removed. With these advantages, it has been broadly applied in personal computers and electronic equipment.
- A typical EEPROM has a floating gate and a control gate fabricated using doped polysilicon. When electrons are injected into the floating gate during a programming operation, the electrons distribute evenly within the polysilicon floating gate layer. However, if the tunneling oxide layer underneath the polysilicon floating gate layer contains some defects, a leakage current may flow from the device and compromise the reliability of the device.
- To prevent the flow of a leakage current, an EEPROM with a stacked gate structure having an oxide/nitride/oxide (ONO) composite layer known as a SONOS read-only memory is currently used. Here, the silicon nitride layer replaces the polysilicon floating gate as the charge-trapping layer. Because electrons are injected into the silicon nitride layer mainly through a localized region, the leakage current is less sensitive to any defects in the tunneling oxide layer.
-
FIG. 1 is a schematic cross-sectional view of a conventional SONOS read-only memory (ROM) cell. As shown inFIG. 1 , the SONOS ROM cell includes asubstrate 100, a composite layer 114 that includes asilicon oxide layer 102, a silicon nitride layer 104 and a silicon oxide layer 106 (ONO), agate 108, a pair ofspacers 110, achannel 118 and a pair of source/drain regions 112. Thesilicon oxide layer 102, the silicon nitride layer 104 and thesilicon oxide layer 106 constituting the composite layer 114 are sequentially formed over thesubstrate 100. Thegate 108 is formed over the composite layer 114. Thegate 108 and the composite layer 114 together form agate structure 116. Thespacers 110 are positioned on the sidewalls of thegate structure 116. The source/drain regions 112 are formed in thesubstrate 100 on each side of thegate structure 116. Thechannel 118 is formed in an area underneath thesilicon oxide layer 102 between the source/drain region 112. - To program data into the aforementioned SONOS ROM cells, the so-called Fowler-Nordheim tunneling effect is utilized. First, a voltage is applied to the
gate 108 so that a large electric field is setup between thegate 108 and thesubstrate 100. The electric field induces the electrons in thesubstrate 100 to inject from thechannel 118 through the tunnelingdielectric layer 102 into the charge-trapping layer 104, thereby increasing the threshold voltage of the transistor. In this way, a single bit of data is programmed into a memory cell. - In a conventional SONOS ROM, a single bit of data is stored within each memory cell. However, with the expansion of computer software applications, the need for high storage capacity memory increases exponentially. To produce a deep sub-micron memory with a large memory capacity, the structure and some of the steps for forming the SONOS ROM must somehow be modified.
- Accordingly, at least one objective of the present invention is to provide a multi-level memory cell with a larger memory capacity.
- To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a multi-level memory cell. The multi-level memory cell includes a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions. The tunneling dielectric layer, the charge-trapping layer and the top dielectric layer made from silicon oxide, silicon nitride and silicon oxide material respectively are sequentially formed over the substrate. The tunneling dielectric layer has a thickness between 20 Å to 40 Å so that charges may tunnel from the substrate into the charge-trapping layer through the Fowler-Nordheim tunneling effect. The charge-trapping layer has a thickness between 40 Å to 60 Å for capturing and holding charges.
- The top dielectric layer has at least two portions with each portion having a different thickness. When a voltage is applied to the gate, different electric field strength is set up between the gate and the substrate in each portion. With different electric field strength in each portion, the amount of charges that can be accommodated within the charge-trapping layer will be different. Therefore, a single memory cell can register multiple data bits.
- In addition, the tunneling dielectric layer, the charge-trapping layer and the top dielectric together with the gate form a gate structure. Furthermore, spacers are formed on the sidewalls of the gate structure. The spacers are fabricated using an insulating material such as silicon oxide. The source/drain regions are formed in the substrate on each side of the gate structure.
- With the top dielectric layer of the multi-level memory cell hsa at least two portions, the amount of charges stored in the charge-trapping layer of each portion is different. Hence, each memory cell can be activated by a group of different threshold voltage values so that multiple data bits are registered. In other words, the storage capacity of each memory cell is increased.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
-
FIG. 1 is a schematic cross-sectional view of a conventional SONOS read-only memory (ROM) cell. -
FIGS. 2A through 2F are schematic cross-sectional views showing the steps for fabricating a multi-level memory cell according to one preferred embodiment of this invention. -
FIG. 3 is a schematic cross-sectional view of a multi-level memory cell according to another preferred embodiment of this invention. - Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
-
FIGS. 2A through 2F are schematic cross-sectional views showing the steps for fabricating a multi-level memory cell according to one preferred embodiment of this invention. As shown inFIG. 2A , asubstrate 200 such as a P-type semiconductor substrate is provided. A tunnelingdielectric layer 202 having a thickness between 20 Å to 40 Å is formed over thesubstrate 200. Thetunneling dielectric layer 202 is a silicon oxide layer formed, for example, by performing a chemical vapor deposition process. Since thetunneling dielectric layer 202 is fabricated using silicon oxide material, thetunneling dielectric layer 202 is also referred to as a bottom oxide layer. Thereafter, a charge-trapping layer 204 having a thickness between 40 Å to 60 Å is formed over the tunnelingdielectric layer 202, for example, by performing a chemical vapor deposition process. The charge-trapping layer 204 is fabricated using silicon nitride or other materials that have a charge trapping capability. - As shown in
FIG. 2B , atop dielectric layer 206 is formed over the charge-trapping layer 204, for example, by performing a chemical vapor deposition process using silicon oxide. Since thetop dielectric layer 206 is fabricated using silicon oxide as material, thetop dielectric layer 206 is also referred to as a top oxide layer. Thetop dielectric layer 206 is divided into a plurality of portions. Two portions labeled A and B are shown inFIG. 2B . Thereafter, a etching back process or a repetition of the chemical vapor deposition process is carried out so that thetop dielectric layer 206 has different thickness in portion A and portion B. - As shown in
FIG. 2C , a dopedpolysilicon layer 208 is formed over thetop dielectric layer 206. The dopedpolysilicon layer 208 is formed, for example, by performing a chemical vapor deposition process to form a polysilicon layer (not shown) over thetop dielectric layer 206 and then implanting dopants into the polysilicon layer. Alternatively, the dopants are added in-situ with the polysilicon deposition. In general, P-type or N-type dopants may be implanted according to the particular fabrication process. - As shown in
FIG. 2D , a photolithographic and etching process is carried out to pattern out agate structure 216. Thegate structure 216 includes a patternedtunneling dielectric layer 202 a, a charge-trapping layer 204 a, atop dielectric layer 206 a and agate 208 a. Thetop dielectric layer 206 a includes the portions A and B. Furthermore, thetop dielectric layer 206 a has a different thickness in portion A and B. In other words, thetop dielectric layer 206 a has parts with different thickness. - As shown in
FIG. 2E , an ion implantation is carried out using thegate structure 216 as a mask to form lightly dopedregions 214 in thesubstrate 200. Thereafter,spacers 210 are formed on the sidewalls of thegate structure 216. Thespacers 210 are silicon oxide layers formed, for example, by performing a chemical vapor deposition process to form a conformal silicon oxide layer (not shown) over thesubstrate 200 and covering thegate structure 216 and then performing an anisotropic etching operation. - As shown in
FIG. 2F , a doping operation is carried out using thespacers 210 as a mask to form heavily dopedregions 218 in thesubstrate 200. Thus, a multi-level memory cell is formed. The heavily dopedregion 218 and the lightly dopedregion 214 together constitute a source/drain region 212. The doping operation includes an ion implantation, for example. -
FIG. 2F shows a fully formed multi-level memory cell according to this invention. As shown inFIG. 2F , the multi-level memory cell includes asubstrate 200, atunneling dielectric layer 202 a, a charge-trapping layer 204 a, atop dielectric layer 206 a, agate 208 a, a pair ofspacers 210 and a pair of source/drain regions 212. Thetunneling dielectric layer 202 a, the charge-trapping layer 204 a and thetop dielectric layer 206 a made from silicon oxide, silicon nitride and silicon oxide material respectively are sequentially formed over thesubstrate 200. Thetunneling dielectric layer 202 a has a thickness between 20 Å to 40 Å. Thetunneling dielectric layer 202 a is a layer that facilitates the tunneling of charges from thesubstrate 200 into the charge-trapping layer 204 a through the Fowler-Nordheim tunneling effect. The charge-trapping layer 204 a having a thickness between 40 Å to 60 Å is used for capturing and holding electric charges. - In addition, the
tunneling dielectric layer 202 a, the charge-trapping layer 204 a and thetop dielectric layer 206 a together constitute agate structure 216. Thespacers 210 are formed on the sidewalls of thegate structure 216. Thespacers 210 are fabricated using an insulating material including silicon oxide, for example. The source/drain regions 212 are located in thesubstrate 200 on each side of thegate structure 216. - Note that the
top dielectric layer 206 a is divided into portion A and portion B. Since thetop dielectric layer 206 a in portion A has a thickness that differs from the one in portion B, the electric field strength between thegate 208 a and thesubstrate 200 are different in these two portions. Hence, the electric field strength inside the charge-trapping layer 204 a is different due to a different thickness in thetop dielectric layer 206 a between these two portions. When the memory cell is activated, charges are injected from thesubstrate 200 into the charge-trapping layer 204 a via thetunneling dielectric layer 202 a due to the Fowler-Nordheim effect. The injected charges are retained within the charge-trapping layer 204 a. Furthermore, the amount of charges injected into the charge-trapping layer 204 a is related to the electric field strength. In other words, during the memory programming operation, the electric field strength between thegate 208 a and thesubstrate 200 in the portion with a thinner topdielectric layer 206 a is greater. Therefore, more charges will tunnel through thetunneling dielectric layer 202 a into the charge-trapping layer 204 a. Conversely, the electric field strength between thegate 208 a and thesubstrate 200 in the portion with a thicker topdielectric layer 206 a is smaller. Therefore, less charges will tunnel through thetunneling dielectric layer 202 a into the charge-trapping layer 204 a. Consequently, the amount of charges trapped within the charge-trapping layer of each portion is different so that a single memory cell can hold a multiple of data bits. - Because the amount of charges trapped in the charge-trapping layer in portion A and portion B is different in this embodiment, two different threshold voltages can be used to activate a single memory cell.
- Note that the top dielectric layer inside each multi-level memory cell according to this invention can be divided into a multiple of portions. Although the aforementioned embodiment has two portions with different thickness, there is no restriction on the number of portions in the top dielectric layer.
-
FIG. 3 is a schematic cross-sectional view of a multi-level memory cell according to another preferred embodiment of this invention. All the elements inFIG. 3 identical to the aforementioned embodiment are labeled identically. Since the materials and method of fabrication are mostly identical to the aforementioned embodiment, detailed description is omitted. In this embodiment, thetop dielectric layer 206 a has three portions A, B and C with thetop dielectric layer 206 a inside each portion having a different thickness. When a voltage is applied to the gate, the electric field strength between the gate and the substrate corresponding to the portion A, B and C are all different. Thus, the amount of charges trapped within the charge-trapping layer in each portion is different. In this embodiment, three different threshold voltages can be used to activate a single memory cell. Therefore, the storage capacity of each memory cell is further increased. - With the top dielectric layer of the multi-level memory cell has at least two portions, the amount of charges stored in the charge-trapping layer of each portion is different. Hence, each memory cell can be activated by a group of different threshold voltage values so that multiple data bits are registered. In other words, the storage capacity of each memory cell is increased.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
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Cited By (7)
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KR100630680B1 (en) | 2004-03-19 | 2006-10-02 | 삼성전자주식회사 | Non-volatile Memory Device with Asymmetrical Gate Dielectric Layer and Manufacturing Method thereof |
US20090075466A1 (en) * | 2005-08-15 | 2009-03-19 | Ho Chiahua | Method of manufacturing a non-volatile memory device |
US20100133612A1 (en) * | 2005-12-22 | 2010-06-03 | Sandhu Gurtej S | Electronic device with asymmetric gate strain |
US20140124755A1 (en) * | 2012-11-06 | 2014-05-08 | Samsung Display Co., Ltd. | Thin film transistor and method of manufacturing the same |
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