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Publication numberUS20050145955 A1
Publication typeApplication
Application numberUS 11/027,093
Publication dateJul 7, 2005
Filing dateDec 30, 2004
Priority dateJun 28, 2002
Also published asUS6853035, US6861707
Publication number027093, 11027093, US 2005/0145955 A1, US 2005/145955 A1, US 20050145955 A1, US 20050145955A1, US 2005145955 A1, US 2005145955A1, US-A1-20050145955, US-A1-2005145955, US2005/0145955A1, US2005/145955A1, US20050145955 A1, US20050145955A1, US2005145955 A1, US2005145955A1
InventorsTsu-Jae King
Original AssigneeProgressant Technologies, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Negative differential resistance (NDR) memory device with reduced soft error rate
US 20050145955 A1
Abstract
An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAM) using such elements is disclosed. Soft error rate (SER) performance for NDR FETs and such memory devices are enhanced by adjusting a location of charge traps in a charge trapping layer that is responsible for effectuating an NDR behavior. Both an SER and a switching speed performance characteristic can be tailored by suitable placement of the charge traps.
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Claims(25)
1. A method of forming a semiconductor field effect transistor (PET) for a memory device, the PET having a control gate, a source region, a drain region, the method comprising the steps of:
forming a channel for carrying a current between the source and drain regions; and
forming a trapping layer located proximate to and forming an interface with said channel, said trapping layer including trapping sites adapted for trapping at least warm carriers from said channel so as to effectuate a negative differential resistance mode for the FET;
wherein an operational switching steed for the FET is directly related to a distance which said trapping sites are located from said interface, such that locating said trapping sites at a distance D1 results in a maximum operational switching speed S1, and such that locating said trapping sites at a distance D2 (D2>D1) results in a minimum operational switching speed S2 (S2<S1); and
distributing said trapping sites within said trapping layer at an approximate distance D (D2>D>D1) in accordance with a target operational switching speed S for the FET (S1>S>S2) and a target soft error rate for the memory device.
2. The method of claim 1, wherein D1 is about 0.5 nm, and D2 is about 1.5 nm.
3. The method of claim 1 wherein S2 is about 1 nanosecond and S1 is about 1 picosecond.
4. The method of claim 1, wherein the target soft error rate is about 1000 failures in time per Mbit.
5. The method of claim 1, further including a step of forming an additional set of trapping sites at an approximate distance D′ from the interface where (D2>D′>D1).
6. The method of claim 1, wherein said trapping sites are distributed at a particular distance by adjustment of an implant energy and dosage.
7. The method of claim 1, wherein a concentration of said trapping sites in a bulk region of said trapping layer is controlled by adjustment of a temperature and/or time characteristic of a heat treatment process.
8. The method of claim 1, wherein said trapping layer consists of a first dielectric layer and a second dielectric layer, and said trapping sites are located only within said first dielectric layer.
9. The method of claim 1, wherein said trapping sites are located along only a limited portion of the interface.
10. The method of claim 9, wherein said portion is nearer said source region than said drain region.
11. The method of claim 1, wherein said trapping sites are distributed so that substantially all of said trapping sites are within 1-1.5 nm of said interface.
12. A memory cell comprising:
a data transfer element adapted to facilitate a read operation or a write operation involving a storage node of the memory cell;
a first negative differential resistance (NDR) element coupled to said data transfer element, said storage node and a first voltage potential, wherein said first NDR element is adapted to operate with a first NDR characteristic between said storage node and said first voltage potential;
a second NDR element coupled to said first NDR element, said data transfer element, said storage node and a second voltage potential wherein said second NDR element is adapted to operate with a second NDR characteristic between said storage node and said second voltage potential;
said first NDR element and said second NDR element both including a trap layer in which charge traps are used to effectuate said first NDR characteristic and said second NDR characteristics; and
wherein said charge traps are distributed in said trap layer so as to cause the memory cell to achieve a soft error rate of approximately 1,000 failures-in-time (FITs)/Mbit or less.
13. The memory device of claim 12, wherein said memory device is a static random access memory (SRAM) cell.
14. The memory device of claim 12, wherein said first NDR element and said second NDR element are NDR-capable FETs.
15. The memory device of claim 14, wherein said charge traps are distributed in said trap layer so as to NDR-capable FETs to switch with a switching speed between 1 picosecond and 10 nanoseconds.
16. In a memory cell including a transfer field effect transistor (FET), a first negative differential resistance (NDR) element and a second NDR element that are operably interconnected to store a data value, the improvement comprising:
at least one of the first NDR element and the second NDR element being implemented as an NDR-capable FET, said NDR-capable FET using a charge trapping mechanism to achieve an NDR behavior suitable for storing the data value; and
wherein charge traps are distributed in a charge trapping layer of said NDR capable FET so as to cause the memory cell to achieve a switching speed between 1 picosecond and 10 nanoseconds and a soft error rate of approximately 1,000 failures-in-time (FITs)/Mbit or less.
17. The memory cell of claim 16, wherein said traps are formed by a doping impurity such as Boron.
18. The memory cell of claim 16, wherein said traps have a trap density of approximately 1 to 5*1014 traps/cm2 at a distance of about 0.5 nm from an interface of said trapping layer with a channel of said NDR-capable FET.
19. The memory cell of claim 16, wherein said traps have an energy level of about 0.5 eV about a conduction band edge of a channel of said NDR-capable FET.
20. The memory cell of claim 16, wherein said trapping layer is comprised of two separate layers, including a first dielectric layer with a high concentration of said charge traps, and a second dielectric layer with a substantially smaller concentration of said charge traps.
21. In a process for making a memory cell having three elements, including a transfer field effect transistor (FET), a first negative differential resistance (NDR) element and a second NDR element that are operably interconnected to store a data value, the improvement comprising the steps of:
forming at least one of the first NDR element and the second NDR element as an NDR-capable PET, said NDR-capable FET including a charge trapping layer for effectuating an NDR characteristic; and
distributing charge traps in said charge trapping layer of said NDR capable FET in accordance with a target switching speed and a target soft error rate for the memory cell.
22. The process of claim 21 wherein said memory cell as formed achieves a switching speed between 1 picosecond and 10 nanoseconds and a soft error rate of approximately 1,000 failures-in-time (FITs)/Mbit or less.
23. The process of claim 21, wherein said trapping layer is formed as two separate layers in two separate processing steps, including a first dielectric layer with a high concentration of said charge traps, and a second dielectric layer with a substantially smaller concentration of said charge traps.
24. The process of claim 21, wherein said charge traps are implanted into a channel region of said NDR capable FET, and a rapid thermal anneal step is performed before said charge trapping layer is formed at an interface with said channel region.
25. The process of claim 21, wherein said charge traps are impurities that are directly implanted into said trapping layer after said trapping layer is formed.
Description
CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of U.S. patent application Ser. No. 10/831,867, entitled: “Negative Differential Resistance (NDR) Memory Device With Reduced Soft Error Rate”, filed Apr. 26, 2004, which is a continuation of application Ser. No. 10/298,700 filed Nov. 18, 2002, now U.S. Pat. No. 6,727,548 which in turn is a divisional of U.S. patent application Ser. No. 10/185,569 filed Jun. 28, 2002, now U.S. Pat. No. 6,567,292. all of which are hereby incorporated by reference as if fully set forth herein.

FIELD OF THE INVENTION

This invention generally relates to semiconductor memory devices and technology, and in particular to negative differential resistance (NDR) elements and static random access memory (SRAM) devices that utilize the same.

BACKGROUND OF THE INVENTION

A new type of FET and SRAM device using the same (NDR FETs) is described in detail in a patent application Ser. No. 10/029,077 filed Dec. 21, 2001 assigned to the present assignee, and published on May 9, 2002 as Publication No. 2002/0054502. The NDR FET structure, operation and method of making the same are discussed in detail in patent application Ser. No. 09/603,101 filed Jun. 22, 2000 by King er al., which is also assigned to the present assignee. Such details are also disclosed in a corresponding PCT application PCT/US01/19825 which was published as publication no. WO 01/99153 on Dec. 27, 2001. The above materials are hereby incorporated by reference.

As is well known, soft errors in memory devices are caused by, among other things, cosmic rays (neutrons), and alpha particles present in semiconductor materials and packaging. In typical SRAMs, the failure rate attributable to soft-errors (the so-called soft-error rate—SER) is measured by a metric known as Failures In Time (FIT); the basic unit of this benchmark refers to a malfunction occurrence frequency, where 1 FIT represents one malfunction every one billion hours (approximately 100,000 years) per device. For a conventional SRAM operating under normal conditions an FIT value of up to several thousand is considered adequate, and a value of less than approximately 1000 FIT/Mbit is preferable for embedded memory applications. In some applications more stringent requirements may be needed (i.e. on the order of 10-100 FIT/Mbit).

Soft errors can also influence SRAM embodiments which use NDR devices. Thus there is clearly a need for NDR FET and an NDR FET based SRAM device that have superior soft error characteristics.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a memory device such as a static random access memory (SRAM) cell which utilizes NDR FETs, and which has improved soft error rate (SER) performance.

A first aspect of the invention concerns a method of forming a semiconductor field effect transistor (FET) for a memory device, the FET having a control gate, a source region, and a drain region. This method includes generally the following steps: forming a channel for carrying a current between the source and drain regions; and forming a trapping layer located proximate to and forming an interface with the channel. The trapping layer includes trapping sites adapted for trapping at least warm carriers from the channel so as to effectuate a negative differential resistance mode for the FET. To tailor characteristics of the FET, including an operational switching speed for the FET, the trapping sites are also tailored. In other words, the FET speed is directly related to a distance which the trapping sites are located from the interface, such that locating the trapping sites at a distance D1 results in a maximum operational switching speed S1, and such that locating the trapping sites at a distance D2 (D2>D1) results in a minimum operational switching speed S2 (S2<S1). Thus, the trapping sites are distributed within the trapping layer at an approximate distance D (D2>D>D1) in accordance with a target operational switching speed S for the FET (S1>S>S2) and a target soft error rate for the memory device.

The trapping sites are distributed at a particular distance by adjustment of an implant energy and dosage, and/or a thermal anneal operation. In a preferred embodiment, D1 is about 0.5 nm, and D2 is about 1.0 nm. Preferably no traps are included in the bulk of the trapping layer that forms a gate dielectric for the NDR FET. The operational speed of the FET is thus between about 10 nanoseconds and 1 picosecond using contemporary conventional technology. This also achieves a soft error rate of less than about 1000 failures in time per Mbit.

In other variations, an additional set of trapping sites are formed at an approximate distance D′ from the interface where (D2>D′>D1).

To prevent them from achieving a high concentration in a bulk region, a rapid thermal anneal (RTA) is performed after such implant. Alternatively the trapping layer can be formed by two distinct layers, including a first dielectric layer and a second dielectric layer, where the trapping sites are located only within the first dielectric layer.

In yet another variation, the trapping sites are located laterally along only a limited portion or region near the interface. Preferably this limited portion is nearer the source than the drain of the NDR capable FET.

Another aspect of the invention concerns a memory device which uses a trap layer in which charge traps are used to effectuate NDR characteristics for the load and driver elements. The charge traps are distributed in the trap layer so as to cause the memory cell to achieve a soft error rate of approximately 1,000 failures-in-time (FITs)/Mbit or less.

In a preferred embodiment, the memory device is a static random access memory (SRAM) cell, and the load and driver elements are both NDR-capable FETs. The charge traps are distributed in the trap layer so that the NDR-capable FETs switch with a switching speed between 1 picosecond and 10 nanoseconds.

Other particular aspects of the invention pertain to the character of the traps, such as their material properties (preferably a doping impurity such as Boron), their density (preferably about 1 to 5*1014 traps/cm2 at a distance of about 0.5 nm from an interface of the trapping layer with a channel of the NDR-capable FET) their energy (preferably about 0.5 eV above a conduction band edge of a channel of the NDR-capable FET), and methods for forming the same within a memory cell.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a preferred embodiment of a static random access memory (SRAM) cell consisting of the combination of two NDR-FET elements which form a bistable latch and one n-channel enhancement-mode IGFET access element;

FIG. 2 is a plot of the current-vs.-voltage characteristic of the bistable latch formed by the combination of two NDR-FETs as shown in FIG. 1;

FIG. 3A is a schematic cross-sectional view of an NDR FET of a preferred embodiment of the present invention and which is preferably incorporated as one or both of the two NDR FET elements of the SRAM cell of FIG. 1;

FIG. 3B is a graph generally illustrating a relationship between SER and switching speed for an NDR FET and NDR based SRAM device constructed in accordance with the present teachings.

DETAILED DESCRIPTION OF THE INVENTION

As noted earlier, FIG. 1 is a circuit diagram of a preferred embodiment of a static memory (SRAM) cell 105 consisting of two NDR elements 102, 103 which form a bistable latch 104 and one enhancement-mode IGFET access element 101.

FIG. 2 is a current-vs.-voltage plot illustrating the operational characteristics of the static memory cell 105 of FIG. 1.

NDR elements 102, 103 of the present invention are preferably an NDR FET of the type referred to above in the aforementioned King et al. applications and constructed in accordance with such teachings except as noted below. The details of the same are provided for example in the aforementioned applications, and such documents are incorporated by reference herein primarily for the purpose of providing non-essential background information on representative types of environments in which the present inventions can be practiced.

The SRAM cell using NDR FETs described in application Serial No. 10/029,077 is already believed to have superior SER performance over prior art SRAM cells due to its unique architecture and physical operation. This SRAM cell is particularly advantageous for embedded SRAM applications, which are becoming more and more critical for system on chip (SOC) devices.

Nonetheless, to achieve even better SER performance, the inventor has determined that the structure and manufacture of the basic NDR FETs 102, 103 used in the embodiment of FIG. 1 can be tailored to create different distributions of the charge traps (which assist in bringing about an NDR characteristic). Thus, for any particular desired design or needed performance characteristic, both a switching benchmark and an error benchmark can be controlled. While the description herein is presented in the context of a conventional bulk silicon based memory cell, it will be understood by those skilled in the art that the present teachings could also be exploited in so-called Silicon on Insulator (SOI) based SRAM cells. The advantages of SOI technology include the fact that the SER is generally lower as compared with bulk-Si technology because of the overall reduced p-n junction sizes.

As shown in FIG. 3A, the overall structure as shown in cross section of a preferred NDR FET 100 of the present invention is similar to that shown in the aforementioned Ser. No. 10/029,077 and includes generally a substrate 120 with a body bias terminal 125; a source region 140 (with a source terminal 145) coupled through a channel region 140 to a drain region 150 (with a drain terminal 155) by a channel region 140; a gate dielectric 130 and a gate electrode 110 connected to a bias signal through a gate terminal 115.

The primary difference, as described herein, is that the charge traps (131, 132) of the present invention are tailored to be placed at a particular location (or locations) in gate dielectric in accordance with a desired SER and switching speed for an NDR FET. It will be appreciated by those skilled in the art that the cross section of FIG. 3A is not to scale, and that certain features have been simplified and/or omitted to make the present discussion more germane to the claimed invention.

From theoretical calculations, simulations and experiments the inventor has determined that the speed of the NDR mechanism is directly related to, among other things, the trap density and physical location of the trap states: in other words, the farther the traps are from the interface (d2>d1) the slower the NDR mechanism. Preliminary data suggests that if charge traps are incorporated as a charge trap distribution 131—i.e., right at or very near the channel/dielectric interface (i.e., d1 is almost 0) during a manufacturing process using a concentration (preferably Boron) greater than 1*1019/cm3, then the switching speed (to go in/out of an NDR mode) is on the order of 1 picosecond. This concentration of Boron in fact yields a trap density of about 2*1014/cm2 which is more than adequate for significant charge trapping behavior. However, if the charge traps are incorporated instead as a charge trap distribution 132—i.e., positioned slightly away from such interface (i.e., about 1 nm into the dielectric as noted at d2) during a manufacturing process then the switching speed is on the order of 1 nanosecond. It will be understood of course that other alternative locations and distributions for the charge traps can be provided for NDR FET 100, and that locations d1 and d2 are merely representative. Moreover, for some applications it may be desirable to form distributions at more than one general location with different processing steps.

In any event, this mechanism limits the speed at which data can be written into an SRAM cell of the type shown in FIG. 1—i.e., the slower the NDR mechanism, the longer the write access time. From the above it can be seen that the switching speed can be controlled by a factor of 1000 or more simply by adjusting the traps to be distributed in locations 131 or 132.

Nonetheless, the inventor has also noted that one positive side effect of moving the charge traps farther from the semiconductor-insulator interface is that immunity to soft-errors increases concomitantly with the distance. The location of the traps can still be adapted to provide an extremely fast switching speed as may be required for a particular application.

This phenomenon is illustrated basically in the graph of FIG. 3B, which for a particular switching speed (S1) there is a corresponding soft error rate (SER1), and for a lower switching speed (S2) there is a corresponding lower soft error rate (SER2). While the precise relationship between these parameters will vary, it is expected nonetheless that it should be roughly linear as shown, or at least its form easily determinable for any particular set of given process parameters without undue experimentation.

Accordingly, for any particular design and process, both a switching benchmark and an error benchmark can be satisfied through routine modeling and testing. Where it is appropriate, a trade-off between fast write speed and high immunity to soft-errors can be tailored by adjusting the fabrication process to adjust the physical location of the charge traps. The specific location of the traps to achieve a particular SER benchmark and write speed benchmark will vary of course based on geometry, process variations, and desired performance characteristics.

To actually distribute the traps in a particular location and with a particular concentration, the teachings of the aforementioned King et al applications can be used, in which the energy and concentration of an ion implant (preferably Boron) into the channel region are adjusted through any conventional means. For example, an implant of Boron at 20 KeV and at 2 to 3*104/cm2 into channel region 140 results in an acceptable concentration of charge traps into the trapping layer 130 as noted above and with the requisite amount of energy. In a preferred approach, the traps have an energy preferably about 0.5 eV above a conduction band edge of channel 140 so that it is not necessary for the electrons in the channel to be “hot,” but rather only slightly energized, or “warm” to be trapped. This further ensures that they easily de-trapped as well. The traps are incorporated into a channel/dielectric interface region and the bulk of gate dielectric layer 130 through the process of forming the latter using conventional gate oxidation processes as explained in the former King et al application. Thus, by controlling how they are initially implanted into channel region 140, the final distribution and location of the traps is also determined within trapping layer 130.

In another variation, trapping sites are located along only a limited portion of the channel/dielectric layer interface. In other words, the channel implant is masked to ensure that only a portion of dielectric layer 130 (in the horizontal direction parallel to channel 140) includes traps, and thus a trapping mechanism will only occur in such region. For some applications for example it may be desirable to have a trapping activity occur closer to a source region than a drain region, as this avoids trapping hot carriers (generated excessively on the drain side) and thus it makes it more easy to control a threshold voltage of NDR FET 100.

Finally, the inventor has discovered that there is another reason why it is desirable to try to keep the traps confined to the channel/dielectric interface region. Namely, if the dopant concentration is too high in gate dielectric layer 130, this can result in unacceptable leakage characteristics. To prevent the traps from achieving a high concentration in the bulk of the remainder of trapping layer 130, a variety of different techniques can be used. For example, a rapid thermal anneal (RTA) step (or an equivalent heat treatment step) tends to minimize such diffusion by annealing out implantation induced defects (after the channel region is implanted), and thus is preferable for most applications. Thus the traps can be further manipulated and distributed by adjusting a time, temperature, or ramping characteristic of such heat process.

Alternatively the trapping layer 130 can be formed as two separate dielectric layers, such as a deposited Si02 layer followed by a thermally grown Si02 layer. Other materials are also possible, of course, including mixtures of SiN, SiON, etc. The traps are then primarily distributed only at the channel interface, within the deposited Si02 layer and an interface with the thermal Si02 layer. Yet another variation would be to directly implant the charge traps into a particular location and concentration only after channel region 140 and gate dielectric layer 130 are formed.

Other techniques will be apparent to those skilled in the art, and the present invention is not limited by such considerations. Accordingly, the particular details can be determined for any particular architecture and can be implemented in the same in silicon form with conventional techniques known to those skilled in the art, such as through routine simulations, process experiments, etc.

Thus for 6—T SRAM technologies below 0.1 3 um, where soft-error rate is emerging as a very serious problem in embedded applications, this aspect of the invention can be exploited to form embedded soft-error rate optimized SRAMs. Conventional error-correction techniques can also be supplementally employed with such embodiments to bring the overall FIT rate to acceptable levels.

Other embodiments of the same will be apparent from the present teachings, and the present invention is by no means limited to the examples herein. Other supporting structures may also be incorporated within an SRAM cell 105 as operational elements, including NDR diodes. In such instances, only one NDR FET may be used, and only such NDR FET may require trap tailoring.

While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. It will be clearly understood by those skilled in the art that foregoing description is merely by way of example and is not a limitation on the scope of the invention, which may be utilized in many types of integrated circuits made with conventional processing technologies. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. Such modifications and combinations, of course, may use other features that are already known in lieu of or in addition to what is disclosed herein. It is therefore intended that the appended claims encompass any such modifications or embodiments. While such claims have been formulated based on the particular embodiments described herein, it should be apparent the scope of the disclosure herein also applies to any novel and non-obvious feature (or combination thereof) disclosed explicitly or implicitly to one of skill in the art, regardless of whether such relates to the claims as provided below, and whether or not it solves and/or mitigates all of the same technical problems described above. Finally, the applicants further reserve the right to pursue new and/or additional claims directed to any such novel and non-obvious features during the prosecution of the present application (and/or any related applications).

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8026481 *Feb 1, 2007Sep 27, 2011Hitachi High-Technologies CorporationCharged particle apparatus, scanning electron microscope, and sample inspection method
Classifications
U.S. Classification257/405, 438/288
International ClassificationG11C5/00, G11C11/412
Cooperative ClassificationG11C11/4125, G11C5/005
European ClassificationG11C11/412R, G11C5/00R
Legal Events
DateCodeEventDescription
Dec 21, 2006ASAssignment
Owner name: SYNOPSYS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PROGRESSANT TECHNOLOGIES, INC.;REEL/FRAME:018837/0769
Effective date: 20061218