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Publication numberUS20050178505 A1
Publication typeApplication
Application numberUS 10/506,558
PCT numberPCT/KR2002/000715
Publication dateAug 18, 2005
Filing dateApr 19, 2002
Priority dateMar 4, 2002
Also published asWO2003075333A1
Publication number10506558, 506558, PCT/2002/715, PCT/KR/2/000715, PCT/KR/2/00715, PCT/KR/2002/000715, PCT/KR/2002/00715, PCT/KR2/000715, PCT/KR2/00715, PCT/KR2000715, PCT/KR2002/000715, PCT/KR2002/00715, PCT/KR2002000715, PCT/KR200200715, PCT/KR200715, US 2005/0178505 A1, US 2005/178505 A1, US 20050178505 A1, US 20050178505A1, US 2005178505 A1, US 2005178505A1, US-A1-20050178505, US-A1-2005178505, US2005/0178505A1, US2005/178505A1, US20050178505 A1, US20050178505A1, US2005178505 A1, US2005178505A1
InventorsYoung Yul Kim
Original AssigneeYoung Yul Kim
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Electrode for dry etching a wafer
US 20050178505 A1
Abstract
Disclosed is an electrode for dry etching a wafer. The electrode includes a first electrode and a second electrode. The first electrode includes a first flat plate and a ring-shaped first protrusion corresponding to one surface of the edge of a wafer, and the second electrode includes a second flat plate and a ring-shaped second protrusion corresponding to the other surface of the edge of the wafer. The first plate and the second flat plate are the same dimension, and the first protrusion and the second protrusion are the same dimension.
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Claims(2)
1. An electrode for dry etching a wafer, said electrode comprising a first electrode and a second electrode for removing foreign materials from the edge of the wafer by plasma, said first electrode including a first flat plate and a ring-shaped first protrusion corresponding to one surface of the edge of a wafer, and said second electrode including a second flat plate and a ring-shaped second protrusion corresponding to the other surface of the edge of the wafer, wherein said first protrusion and said second protrusion are the same size.
2. The electrode for dry etching a wafer as set forth in claim 1, wherein an insulation layer is deposited on or an insulating material is attached to an inner area of the upper surface of the first electrode, which is inside of the first protrusion.
Description
TECHNICAL FIELD

The present invention relates to a dry etching of a semiconductor wafer, and more particularly to an electrode for dry etching a semiconductor wafer using plasma, thereby removing foreign material deposited on the edge of the semiconductor wafer for manufactuing integrated circuit chips.

BACKGROUND ART

As well known to those skilled in the art, during the fabrication of high integrated semiconductor chips, multiple layers 110 and 120 such as a poly-silicon layer, a nitride layer, a metal layer, etc. are deposited and accumulated on the edge of a semiconductor wafer 100, as shown in FIG. 5. Further, as shown in FIG. 6, particles broken off the deposited layers on the edge of the semiconductor wafer 100 are generated while transferring the semiconductor wafer 100 or by equipment 200, and introduced into the central portion of the semiconductor wafer 100, thereby contaminating the integrated circuit chips.

Moreover, a gate electrode of a semiconductor chip has been recently changed from tungsten silicide to tungsten, and an insulation layer of a capacitor has been changed from an ONO (oxide-nitride-oxide) structure to tantalum oxide. An organic bottom anti-reflective coating (hereinafter, referred to as ARC) layer and an inorganic ARC layer such as SiON have been recently used to form fine photoresist patterns, and Ti and TiN layers have been used as a barrier metal layer. Therefore, these materials contaminate the semiconductor wafer by the aforementioned route during fabrication.

That is, these materials act as a particle source during fabrication and contaminate the semiconductor wafer 100. Particularly, in case that the diameter of the wafer increases from 200 mm to 300 mm, the radius of the edge of the wafer also increases, thereby more increasing the contamination of the semiconductor wafer by the particles.

Since the materials deposited and accumulated on the edge of the semiconductor wafer 100 reduce the yield and the reliability of the semiconductor chip, these materials need to be fully removed.

Accordingly, in order to remove the materials deposited and accumulated on the edge of the semiconductor wafer, several methods have been used as follows.

For example, hereinafter, a wet etching process for removing a nitride layer, which comprises five steps, is described with reference to FIGS. 7 a to 7 e.

i. An oxide layer 102 is deposited on the nitride layer 101 of the silicon semiconductor wafer 100 by a plasma depositing apparatus (FIG. 7 a).

ii. A photoresist layer 103 is formed on the oxide layer 102 by coating photosensitizer, and the photoresist layer 103 on the edge of the semiconductor wafer 100 is removed, thereby exposing the oxide layer 102 of the edge of the semiconductor wafer 100 (FIG. 7 b).

iii. The exposed oxide layer 102 of the edge of the semiconductor wafer 100 is removed by a chemical solution (NHF4+HF) using a wet etching device (FIG. 7 c).

iv. The photoresist layer 103 on the oxide layer 102 is removed using a dry etching device and residual photoresist 103 is washed by a chemical solution (H2SO4/H2O2) using a washing apparatus (FIG. 7 d).

v. The exposed nitride layer 101 of the edge of the semiconductor wafer 100 is removed by a phosphoric acid (H3PO4) solution of high temperature using a wet etching device (FIG. 7 e).

The above-described wet etching process of the nitride layer is complex. Further, this wet etching process of the nitride layer requires different apparatuses for performing the deposition of the oxide layer, the coating of the photoresist, the removal of the photoresist by dry etching, the removal of the oxide layer by wet etching, the full removal of the residual photoresist, the washing, and the wet etching of the nitride layer.

On the other hand, a dry etching process for removing the poly-silicon layer, which comprises five steps, is described with reference to FIGS. 8 a to 8 e.

i. The oxide layer 102 is deposited on the poly-silicon layer 104 on the silicon semiconductor wafer 100 using a plasma depositing apparatus (FIG. 8 a).

ii. A photoresist layer 103 is formed on the oxide layer 102 by coating photosensitizer, and the photoresist layer 103 on the edge of the semiconductor wafer 100 is removed, thereby exposing the oxide layer 102 on the edge of the semiconductor wafer 100 (FIG. 8 b).

iii. The exposed oxide layer 102 on the edge of the semiconductor wafer 100 is removed by a chemical solution (NHF4+HF) using a wet etching device (FIG. 8 c).

iv. The photoresist layer 103 on the oxide layer 102 is removed using a dry etching device and residual photoresist 103 is washed by a chemical solution (H2SO4H2O2) using a washing apparatus (FIG. 8 d).

v. The exposed poly-silicon layer 104 of the edge of the semiconductor wafer 100 is removed using the conventional dry etching device (FIG. 8 e).

Identically with the aforementioned wet etching of the nitride layer, the above-described dry etching process of the poly-silicon layer is complex. Further, this dry etching process of the poly-silicon layer requires different apparatuses for performing the deposition of the oxide layer, the coating of the photoresist, the removal of the photoresist by dry etching, the removal of the oxide layer by wet etching, the washing, and the dry etching of the poly-silicon layer.

When the poly-silicon layer of the edge of the semiconductor wafer is removed using the conventional dry etching apparatus, the poly-silicon layer on the upper surface of the edge of the semiconductor wafer can be removed but the poly-silicon layer on the lower and the side surfaces of the edge of the semiconductor wafer cannot be fully removed, or can only be imperfectly removed.

Further, since different conventional etching apparatuses are respectively used in each step for forming patterns on the semiconductor wafer, that is, since one etching apparatus is used only to remove one foreign material, it is impossible to use one etching apparatus to remove various materials.

As shown in FIG. 9, the conventional dry etching device used for forming fine circuit patterns of the semiconductor chip forms an electric field between a flat-shaped first electrode 300 and a flat-shaped second electrode 300′ in a reactive gas atmosphere, and generates plasma into the upper surface of the semiconductor wafer 100, thereby etching a deposited layer on the upper surface 100 a of the semiconductor wafer 100 and forming a fine pattern 103 a Herein, the deposited layer on the edge of the semiconductor wafer 100 is removed. Reference number 400 denotes an RF (radio frequency) generator and reference number 500 denotes a matching network.

In the conventional dry etching device, the semiconductor wafer 100 is mounted on one electrode 300′ and etched, thereby not etching the side surface 100 b and the lower surface 100 c of the semiconductor wafer 100. Therefore, the deposited layer on the side surface 100 b and the lower surface 100 c of the semiconductor wafer cannot be removed.

DISCLOSURE OF THE INVENTION

Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide an electrode for dry etching a semiconductor wafer using plasma, which can effectively remove foreign materials deposited on the lower and the sides surfaces as well as the upper surface of the edge of the semiconductor wafer without causing damage to the wafer.

In accordance with the present invention, the above and other objects can be accomplished by the provision of an electrode for dry etching a semiconductor wafer. The electrode comprises a first electrode and a second electrode for removing foreign materials from the edge of the semiconductor wafer using plasma. The first electrode includes a first flat plate and a ring-shaped first protrusion corresponding to one surface of the edge of a semiconductor wafer, and the second electrode includes a second flat plate and a ring-shaped second protrusion corresponding to the other surface of the edge of the semiconductor wafer. Herein, the first protrusion and the second protrusion are the same size.

Preferably, an insulation layer may be deposited on or an insulating material may be attached to an inner area of the upper surface of the first electrode, which is inside of the first protrusion.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a partial cross-sectional view of an electrode for dry etching a semiconductor wafer in accordance with the present invention;

FIG. 2 is a schematic view illustrating the etching of the upper and the side surfaces of a semiconductor wafer using the electrode of the present invention;

FIG. 3 is a schematic view illustrating the etching of the lower and the side surfaces of the semiconductor wafer using the electrode of the present invention;

FIG. 4 is a cross-sectional view of a dry etching device provided with the electrode of the present invention;

FIG. 5 is a side view of semiconductor wafer, on which multiple layers are deposited;

FIG. 6 is a schematic view illustrating the attachment of foreign materials on the semiconductor wafer by equipment.

FIGS. 7 a to 7 e are cross-sectional views illustrating a process for removing a nitride layer using a conventional wet etching;

FIGS. 8 a to 8 e are cross-sectional views illustrating a process for removing a poly-silicon layer using a conventional dry etching; and

FIG. 9 is a schematic view illustrating the etching of a semiconductor wafer using a conventional electrode.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a partial cross-sectional view of an electrode for dry etching a semiconductor wafer in accordance with the present invention. The electrode of the present invention comprises a pair of electrodes, i.e., a first electrode 10 and a second electrode 20. The first electrode 10 and the second electrode 20 are means for generating plasma for removing foreign materials deposited and accumulated on the edge of the semiconductor wafer.

Herein, the first electrode 10 is used as an anode and the second electrode 20 is used as a cathode. However, the first electrode 10 may be used as a cathode and the second electrode 20 may be used as an anode.

The same as the conventional electrode, the first electrode 10 is shaped as a flat circle. A ring-shaped first protrusion 10 a is formed on the bottom surface of the first electrode 10. A gas inlet hole 10 b is formed between the first protrusion 10 a and the circumference of the first electrode 10. The gas inlet hole 10 b serves to introduce a reactive gas for generating plasma into a vacuum chamber (not shown), in which the first electrode 10 and the second electrode 20 are formed.

The second electrode 20 is also shaped as a flat circle having the same diameter of that of the first electrode 10. An opening 20 a is formed on the center of the second electrode 20 and a ring-shaped second protrusion 20 b having the same dimension as that of the first protrusion 10 a is formed between the opening 20 a and the circumference of the second electrode 20.

A flat portion of the outside of the first protrusion 10 a of the first electrode 10 and a flat portion of the outside of the second protrusion 20 b of the second electrode 20 are referred to as a first flat portion 10 c and a second flat portion 20 c.

An insulation layer or an insulator 11 is deposited on or attached to an inner area of the bottom surface of the first protrusion 10 a. The attached insulating material 11 serves to prevent an electric field or an electromagnetic field from being formed between the first electrode 10 and the second electrode 20, when a RF power is supplied between the first electrode 10 and the second electrode 20. Polymide, Teflon, silicon, quartz, or ceramic may be used as the insulator 11.

FIGS. 2 and 3 illustrate the etching of a semiconductor wafer using the electrode of the present invention. Hereinafter, with reference to FIGS. 2 and 3, an interaction between the first and the second electrodes 10, 20 of the present invention and the semiconductor wafer 30 is described.

As shown in FIG. 2, the semiconductor wafer 30 is interposed between the first electrode 10 as the anode and the second electrode 20 as the cathode by an electrostatic chuck 40. The electrostatic chuck 40 is installed at a lowering position via the opening 20 a of the second electrode 20, thereby bringing the lower surface 30 c of the edge of the semiconductor wafer 30 into contact with the upper surface of the second protrusion 20 b of the second electrode 20.

A reactive gas is introduced via the gas inlet hole 10 b of the first electrode 10 and power is supplied from the RF generator 50 to the second electrode 20, thereby forming an electric field or an electromagnetic field through the first protrusion 10 a and the first flat portion 10 c of the first electrode 10 and the second protrusion 20 b and the second flat portion 20 c of the second electrode 20. Then, two types of plasma with different intensity are generated by the reactive gas between the first protrusion 10 a and the second protrusion 20 b and between the first flat portion 10 c and the second flat portion 20 c.

Herein, plasma is formed along width of the first protrusion 10 a and the second protrusion 20 b. The width of the first protrusion 10 a and the second protrusion 20 b corresponds to the width B of the edge of the semiconductor wafer 30 to be etched. Therefore, an area A of the semiconductor wafer 30, in which fine circuit pattern 31 is formed, is not affected by this plasma. The side surface 30 b of the semiconductor wafer 30 is etched by plasma C formed between the first flat portion 10 c and the second flat portion 20 c.

Since the lower surface 30 c of the semiconductor wafer 30 is in contact with the upper surface of the second protrusion 20 b of the second electrode 20, the etching is mainly performed on the upper surface 30 a and the side surface 30 b of the semiconductor wafer 30 by RIB Reactive Ion Etching).

Further, since the insulating material 11 attached to the inner area of the first electrode 10, an electric field or an electromagnetic field is not formed in the area A, thereby preventing plasma from being generated on the area A and improving the efficiency of the etching.

Herein, reference number 60 denotes a matching network.

As shown in FIG. 3, the electrostatic chuck 40 is elevated via the opening 20 a of the second electrode 20, thereby bringing the upper surface 30 a of the edge of the semiconductor wafer 30 into contact with the upper surface of the first protrusion 10 a of the first electrode 10. Then, the reactive gas is introduced via the gas inlet hole 10 b of the first electrode 10 and the power is supplied from the RF generator 50, thereby generating plasma between the first protrusion 10 a and the second protrusion 20 b. Herein, the etching is mainly performed on the lower surface 30 c and the side surface 30 b of the semiconductor wafer 30 by plasma, thereby removing the foreign materials deposited on the area B.

FIG. 4 is a cross-sectional view of a vacuum chamber 70, in which the electrode of the present invention is installed. The vacuum chamber 70 comprises a blow pipe 71 for introducing a reactive gas for generating plasma into the first electrode 10 and the second electrode 20, a port 70 a for entering the semiconductor wafer 30, an outlet 70 b for exhausting the gas after the etching of the semiconductor wafer 30, and the electrostatic chuck 40 for moving the semiconductor wafer 30 upward and downward.

The semiconductor wafer 30 is entered into the vacuum chamber 70 via the port 70 a and mounted on the electrostatic chuck 40. Under a reactive gas atmosphere, the RF generator 50 supplies a voltage via the second electrode 20. At this time, the upper surface of the central portion of the semiconductor wafer 30 is protected by the insulating material 11 of the first electrode 10, and plasma is generated between the first protrusion 10 a and the second protrusion 20 b and between the first flat portion 10 c and the second flat portion 20 c. Then, the upper, the lower, and the side surfaces 30 a, 30 c, and 30 b of the edge of the semiconductor wafer 30 are etched through the aforementioned process.

During the etching process, the same as the conventional case, the foreign materials removed from the semiconductor wafer 30 and the reactive gas are pumped out via the outlet 70 b.

Hereinafter, Table 1 illustrates the reactive gases used in the dry etching of the edge of the semiconductor wafer using the electrode of the present invention and the foreign materials removed using the corresponding reactive gas.

TABLE 1
Material Reactive Gas
Organic ARC (SiON) CF4, SF6
Inorganic ARC (CxSiy) CF4, O2
Oxide layer (SiO2) CF4, CHF3, C4F8, C2F6, Ar, O2,
CH2F2
Nitride layer (Si3N4) CF4, SF6, CHF3, Ar, O2
Poly-silicon (Si) HBr, Cl2, CCl4, SF6, O2
Tungsten silicide (WSix) SF6, Cl2
Tungsten (W) SF6, CF4, Ar, O2
Aluminum (Al) Cl2, CCl4, BCl3
Copper (Cu) Cl2
Tantalum oxide (TaO2) SF6, Cl2, CF4
Tantalum (TaON) SF6, Cl2, CF4
Titanium (Ti) CF4, SF6
Titanium silicide (TiSix) SF6, CF4, O2
SOG, [RxSiOySiO2]n, H(SiO3/2)n SF6, CF4, O2

As described above, the conventional etching device has been used to remove only one type of materials, i.e., a wet etching device for removing the nitride layer or a dry etching device for forming a fine circuit pattern on a semiconductor wafer. Therefore, the process for etching the semiconductor wafer is very complex and each step of the process requires a corresponding etching device.

Further, with the structure of the electrode of the conventional etching device, foreign materials deposited on the upper surface and the side surface of the edge of the semiconductor wafer can be removed. However, foreign materials deposited on the lower surface of the edge of the semiconductor wafer cannot be removed.

However, the electrode of the present invention is used to remove all foreign materials shown in Table 1 by sequentially supplying appropriate reactive gases corresponding to each material without additional equipment, thereby simplifying the whole process.

Moreover, portions other than the upper, the side and the lower surfaces of the edge of the semiconductor wafer are not affected by plasma, thereby effectively etching the edge of the semiconductor wafer and not damaging the fine circuit pattern formed on the center of the semiconductor wafer.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

INDUSTRIAL APPLICABILITY

As apparent from the above description, the present invention provides a an electrode for dry etching a semiconductor wafer, which removes foreign materials deposited on the upper, the side and the lower surfaces of the edge of the semiconductor wafer, without additional equipment or step, thereby simplifying the whole process, reducing the process cost, and improving the yield, the quality of the semiconductor wafer, and its productivity.

Referenced by
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US7094698 *Apr 19, 2002Aug 22, 2006Hyo Sang KangMethod for dry etching a semiconductor wafer
US7615131 *Nov 18, 2003Nov 10, 2009Sosul Co., Ltd.Plasma etching chamber and plasma etching system using same
US7718542Aug 25, 2006May 18, 2010Lam Research CorporationLow-k damage avoidance during bevel etch processing
US7744771 *Oct 2, 2006Jun 29, 2010Hon Hai Precision Industry Co., Ltd.Method for removing protective film on article
US7858898Jan 26, 2007Dec 28, 2010Lam Research CorporationBevel etcher with gap control
US7909960 *May 24, 2006Mar 22, 2011Lam Research CorporationApparatus and methods to remove films on bevel edge and backside of wafer
US7938931 *Jun 5, 2007May 10, 2011Lam Research CorporationEdge electrodes with variable power
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US7951261 *Aug 3, 2006May 31, 2011Jusung Engineering Co. Ltd.Plasma etching apparatus
US8012306Feb 15, 2006Sep 6, 2011Lam Research CorporationPlasma processing reactor with multiple capacitive and inductive power sources
US8137501Feb 8, 2007Mar 20, 2012Lam Research CorporationBevel clean device
US8252140 *Apr 12, 2011Aug 28, 2012Lam Research CorporationPlasma chamber for wafer bevel edge processing
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US8308896Mar 21, 2011Nov 13, 2012Lam Research CorporationMethods to remove films on bevel edge and backside of wafer and apparatus thereof
US8349126 *Feb 23, 2010Jan 8, 2013Samsung Electronics Co., Ltd.Apparatus for etching edge of wafer
US8440051 *Apr 7, 2011May 14, 2013Lam Research CorporationPlasma processing chamber for bevel edge processing
US8500951Mar 23, 2010Aug 6, 2013Lam Research CorporationLow-K damage avoidance during bevel etch processing
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US8911590Feb 27, 2006Dec 16, 2014Lam Research CorporationIntegrated capacitive and inductive power sources for a plasma etching chamber
US20090325382 *Jun 30, 2008Dec 31, 2009Tai-Heng YuBevel etcher and the related method of flattening a wafer
US20100212833 *Feb 23, 2010Aug 26, 2010Chong-Kwang ChangApparatus for Etching Edge of Wafer
US20110186227 *Apr 12, 2011Aug 4, 2011Lam Research CorporationPlasma chamber for wafer bevel edge processing
US20130098390 *Oct 25, 2011Apr 25, 2013Infineon Technologies AgDevice for processing a carrier and a method for processing a carrier
WO2008097996A1 *Feb 5, 2008Aug 14, 2008Andrew Bailey IiiBevel clean device
WO2008109239A1 *Feb 14, 2008Sep 12, 2008Lam Res CorpEdge electrodes with variable power
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WO2009006072A2 *Jun 23, 2008Jan 8, 2009Lam Res CorpMethods and arrangements for plasma processing system with tunable capacitance
WO2009085238A1 *Dec 22, 2008Jul 9, 2009Lam Res CorpCopper discoloration prevention following bevel etch process
Classifications
U.S. Classification156/345.47
International ClassificationH01L21/3065, H01J37/32, C23F1/00
Cooperative ClassificationH01J37/32009, H01J37/32541
European ClassificationH01J37/32M, H01J37/32O6B