|Publication number||US20050194169 A1|
|Application number||US 10/800,173|
|Publication date||Sep 8, 2005|
|Filing date||Mar 11, 2004|
|Priority date||Mar 5, 2004|
|Also published as||EP1721497A2, EP1721497B1, US6949707, US6967282, US20050194168, WO2005088708A2, WO2005088708A3|
|Publication number||10800173, 800173, US 2005/0194169 A1, US 2005/194169 A1, US 20050194169 A1, US 20050194169A1, US 2005194169 A1, US 2005194169A1, US-A1-20050194169, US-A1-2005194169, US2005/0194169A1, US2005/194169A1, US20050194169 A1, US20050194169A1, US2005194169 A1, US2005194169A1|
|Original Assignee||Tonomura Samuel D.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (33), Classifications (38), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation in part of parent application titled “Improved Flip Chip MMIC on Board Performance Using Periodic Electromagnetic Bandgap Structures” filed ______ 2004, Ser. No. ______.
1. Field of Invention
This invention is in the field of cross-talk suppression in a hybrid assembly at microwave frequencies.
2. Description of the Related Art
Monolithic Integrated Circuits (MMIC), an example of a semiconductor structure, support many of the present generation of military and commercial radio frequency sensors and communication applications. MMICs include active devices, such as field effect transistors and bipolar transistors, passive elements such as capacitors, thin film/bulk resistors, and inductors integrated on a single semi-insulating substrate, such as Gallium Arsenide.
Hybrid technology relates to methods used for interconnecting a plurality of separate semiconductor structures, such as MMICs, to a host substrate, in single, or multi-layer configurations. In a hybrid, inter-connections between the semiconductor structures is sometimes along the surface of the host substrate. These interconnections are frequently made using metallized paths connected to bumps (soft solder, or hard plated bumps). These bumps, located on the surface of the substrate, engage conductive pads on the semiconductor structures thus forming conductive, interconnecting paths between the host substrate and the semiconductor structures. The bumps are used as a substitute in place of wire bonds for connections. The advantage of bumps over wire bonds include the elimination of wafer backside processing steps such as wafer thinning, via formation, and metal deposition.
Another advantage to using surface bumps for interconnection purposes is the lower thermal resistance between the semiconductor structures and the host substrate. The lower thermal resistance of the bump connection is due to the relatively large surface area of contact between the host substrate and the semiconductor structures. Heat transfer is also facilitated by the large diameter and short length of the bump, as compared to a wire interconnect. Although both the bump and the wire are made of thermally conductive metal, the favorable aspect ratio of the bump and wider surface area present a lower thermal resistance as compared to a typically thin, long wire bond. The lower thermal path presented by the bump facilitates the conduction of heat away from the semiconductor structures, allowing higher power density for the semiconductor/substrate hybrid assembly, especially when using thermal bumps directly under heat sources. The higher power density allows higher performance for the hybrid.
Yet another advantage of using bumps for interconnect purposes is the elimination of parasitic effects such as capacitance, inductance and radio emissions present with wire bonds and vias. At high frequencies, the thin, long wire bonds, and the vias traversing the thickness of the substrate can be considered as antennas for the emission of electromagnetic interference. The same wires and vias present capacitance to adjacent structures, as well as an inductance to the signals transmitted by the wires.
Other advantages of bumps are their lower cost and higher reliability. Typically bump type connections can be efficiently completed using a single epoxy cure/solder reflow die-attach process. This presents fewer steps during manufacture as compared to wire bond techniques. With bump interconnect, there are no mechanical wire connections to shake loose, be intermittent or fail due to thermal cycling.
While bumps are advantageous as compared to wire inter-connections, their presence between a semiconductor structure and a host substrate presents unique electromagnetic resonance and emission packaging problems. First, there is the optimization of the vertical radio frequency interconnect transitions presented by the interface between the bumps on the host substrate and the semiconductor structure mounted thereon. Then there is the potential electromagnetic coupling effects presented at the interface between the semiconductor structure and the host substrate, as well as the host substrate opposing surfaces.
A particular difficulty introduced by the semiconductor structure mounted on the host substrate is the potential formation of electromagnetic boundaries which support unwanted, parallel plate, waveguide like (surface modes) of energy propagation. Such unwanted modes can propagate near the surface of the host substrate causing degradation in semiconductor performance because of signal interference. The degradation in semiconductor performance are caused by unwanted signal transfer among semiconductor structure inputs and outputs, affecting gain and phase response, loss of isolation between adjacent paths in multiple path/multiple channel circuit applications, and circuit instability. These negative effects are due to the introduction of unwanted coupling or feedback paths.
Maximum frequency operation of the semiconductor in the presence of these unwanted feedback paths are undesirably dependent on the dimensions of the semiconductor structure. Thus, semiconductor structures with large dimensions with respect to wavelength operating frequency present a potential difficulty. This difficulty is prevalent with fast Gallium Arsenide (GaAs) semiconductor structures mounted on a host substrate. The relatively large semiconductor size of GaAs as compared to the wavelength of the operating frequency approach the cutoff frequencies at the upper edge of the operational band. Near cutoff, the semiconductor structure may be functional, but unable to operate because the incoming signals are interfering with each other.
In the prior art, signal interference is reduced by incorporating grounded interconnect bumps strategically placed on the semiconductor structure surface to break up surface modes of energy propagation. By making direct contact to ground pads on the host substrate, the path of the surface modes is disrupted. These grounded interconnect bumps act like shields and attempt to change the path to be followed by the electromagnetic energy propagated along the surface of the host substrate. Unfortunately, because of semiconductor structure limitations and assembly requirements, this practice of using redundant ground bumps as obstacles to surface propagated electromagnetic waves results in a further increase in both semiconductor structure and substrate size, increasing weight, power consumption and reducing reliability of the resulting hybrid.
Another approach described in the parent application to reduce surface modes is to tessellate the area of the substrate located in the proximity of the semiconductor structures with multiple layers of EBG regular polygons. The limitation here is that a plurality of of EBG layers may have to be used to achieve the level of attenuation desired. The plurality of EBG layers, as compared to a single EBG layer, reduce reliability and increase cost of the hybrid.
Above limitations are improved by a hybrid assembly comprising a single electromagnetic band gap (EBG) layer on a substrate having an upper surface and a lower surface and a semiconductor structure (MMIC) mounted above the EBG layer. The hybrid operates typically at microwave operating frequencies. Conductive paths are etched on the upper surface for conducting high frequency signals along the upper surface of the substrate.
A plurality of stars made of an EBG material, forming the EBG layer, are preferably printed, or deposited, on the upper surface. The EBG material has slow wave characteristics. The plurality of stars tessellates the upper surface between the conductive paths, generally in an area below the semiconductor structures.
Each of the stars has a center section formed from a regular polygon, the center section having projections extending from the center section. The projections and the center section form a periphery. The periphery engages adjacent stars along the periphery. Stars are separated from adjacent stars by an interspace. The interspace is preferably constant along the periphery. Stars are also separated by a distance from the conductive paths. Each of the stars is connected to a conductive via, in turn connected to ground potential. In one embodiment, the lower surface is covered with a conductive layer at ground potential. This conductive layer is electrically continuous with vias used to interconnect all stars forming the EBG layer.
In the Drawing:
The present invention describes an apparatus and method for improved cross talk suppression in a hybrid assembly by incorporating a single layer made of electromagnetic band-gap (EBG) stars on a hybrid substrate such as, for example, alumina, LTCC (low temperature co-fired ceramic) as well as HTCC (high temperature co-fired ceramic).
The EBG stars reduce the cross talk induced by undesired surface/waveguide modes at high operating frequencies (10 to 20 Ghz) between input/output and power (or ground) pins on the operation of the hybrid.
In the configuration of
A plurality of hexagonal elements 301 form single layer EBG lattice structure 303, generally printed on substrate 101. Undesired signals traveling from bump 107 towards bump 105 now encounter the effects of the EBG lattice 303 and are attenuated. The thickness of lattice structure 303, shown as t, is, for example, in the order of 1 to 3 mils, depending on the type of ink used to print the lattice structure 303 onto substrate 101, the frequency band to be attenuated, physical dimensions of the semiconductor structure 103.
Each periodic element, or polygon of EBG layer 303, such as polygon 301 and polygon 305, is connected to ground plane 307 using a via. For example, via 309 connects polygon 311, part of EBG layer 303 to ground plane 307.
Unfortunately, a single EBG layer made of regular polygons such as hexagons typically offers limited, sometimes insufficient attenuation of undesired surface waves.
Stars 400,402,404 and 406 form a window 418 between their respective peripheries. This window 418 is used to accommodate vias passing through the plane of stars 400, 402, 404 and 406.
Star 402 has a center via 422 traversing the substrate and connecting to ground potential as shown in
A plurality of stars such as 400 and 402 are made of an electromagnetic band gap material on upper surface 111, the electromagnetic band gap material having slow wave characteristics. The plurality of stars tessellate upper surface 111 between conductive paths.
Each of stars such as 400 and 402 have a center section formed from a regular polygon. The center section has projections extending from the center section. The projections on the center section form a periphery. The periphery of each star engages the periphery of adjacent stars along their respective peripheries. The peripheries of adjacent stars are separated from each other by an interspace I.
The polygon, for example a square 408 in
Interspace I can be accommodated by reducing the side S of the large square 15408 forming star 400, increasing the distance between the center of stars 400 and 402, or both. Also the size of smaller squares needs to be reduced to allow for interspace I as shown. The width of interspace I is meant to be constant over the peripheries of all stars. I is chosen to be compatible with the operating band of the hybrid, the degree of attenuation desired, and the type of EBG material used. Typically, I will become smaller as the frequency of operation of the hybrid increases.
The tessellation of stars shown in
For example, in
Conductive via 604 and 606 are connected to ground potential, ground plane 307. Typically, a plurality of stars interdigitated as shown in
The method for manufacturing the hybrid assembly of this invention comprises the steps of:
A star such as 400 or 402 is formed from a polygonal center section (e.g. a first square 408) with projections extending from it. This first square has four equal first sides, each of the four first sides meeting at a ninety degree angle with the the next first side to form first four corners, each of the four first sides having a first length S.
The projections extending from said center section are four second squares, 410, 412, 414 and 416. Each of said second squares have four second sides, each of said second sides one half of said first length, S/2. Each of said second sides meet at a ninety degree angle with the next second side to form four second corners. The four second squares are centered on the first four corners of first square 408.
The first length chosen for the dimension of the first square is inversely proportional to the operating frequency of said hybrid. Similarly, the interspace I between stars along the periphery is inversely proportional to the operating frequency of the hybrid.
The semiconductor structures (MMIC 602) are typically mounted over, or in near vertical proximity, to the stars. The semiconductor structures have a plurality of electrical contacts with said conductive paths.
Vias, such as via 604 and via 606, connect stars such as 400 and 402 respectively to a ground potential. Typically, the vias traverse substrate 101 and connect to a conductive layer, ground plane 307 on the lower surface of substrate 101.
Conveniently, the intersection of four stars forms a window 418 between the four intersecting stars, providing a location for vertical structures, such as bump 608 to pass without electrically connecting to EBG layer 612, or stars such as 400 and 402 part of EBG layer 612.
All references cited in this document are incorporated herein in their entirety by reference.
Although presented in exemplary fashion employing specific embodiments, the disclosed structures are not intended to be so limited. For example, although polygon examples are squares, other polygons, such as triangles can be used to form stars for periodic lattices for tessellating substrate surface 111.
Those skilled in the art will also appreciate that numerous changes and modifications could be made to the embodiment described herein without departing in any way from the invention.
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|U.S. Classification||174/392, 257/E23.114, 257/E23.07, 257/E23.079|
|International Classification||H05K1/03, H01L23/14, H01L23/66, H05K9/00, H05K1/02, H01L23/552, H01L23/498, H01L23/50, H05K1/09, H01L23/00|
|Cooperative Classification||H01L2924/1305, H01L2224/16225, H05K2201/09336, H01L2224/81801, H01L23/552, H05K2201/0715, H05K1/0236, H01L23/49838, H01L23/50, H01L2224/16237, H05K1/0306, H01L2924/3025, H05K1/09, H05K2201/09681, H01L2924/09701, H01L2924/01079, H01L23/66, H01P1/2005|
|European Classification||H01P1/20C, H05K1/02C2F, H01L23/50, H01L23/66, H01L23/552, H01L23/498G|
|Mar 11, 2004||AS||Assignment|
|Apr 6, 2009||REMI||Maintenance fee reminder mailed|
|Apr 20, 2009||FPAY||Fee payment|
Year of fee payment: 4
|Apr 20, 2009||SULP||Surcharge for late payment|
|Feb 27, 2013||FPAY||Fee payment|
Year of fee payment: 8