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Publication numberUS20050195629 A1
Publication typeApplication
Application numberUS 10/792,350
Publication dateSep 8, 2005
Filing dateMar 2, 2004
Priority dateMar 2, 2004
Also published asCN1926632A, CN1926632B, DE602005022053D1, EP1723654A1, EP1723654B1, US8099687, US8438515, US8775991, US20080062734, US20120199973, US20130341790, WO2005093757A1
Publication number10792350, 792350, US 2005/0195629 A1, US 2005/195629 A1, US 20050195629 A1, US 20050195629A1, US 2005195629 A1, US 2005195629A1, US-A1-20050195629, US-A1-2005195629, US2005/0195629A1, US2005/195629A1, US20050195629 A1, US20050195629A1, US2005195629 A1, US2005195629A1
InventorsMichael Leddige, Kuljit Bains, John Sprietsma
Original AssigneeLeddige Michael W., Bains Kuljit S., Sprietsma John T.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Interchangeable connection arrays for double-sided memory module placement
US 20050195629 A1
Abstract
A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate.
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Claims(16)
1. A memory module, comprising:
an array of connections arranged in rows and columns such that there are first and second outer columns, and those connections in the first and second outer columns can be interchanged.
2. The memory module of claim 1, wherein the first outer column is a nearside column and the second outer column is a far-side column.
3. The memory module of claim 1, wherein there are third and fourth outer columns having interchangeable connections.
4. The memory module of claim 1, the memory module further comprising a package selected from the group comprised of: X16, and X4/X8.
5. A memory system, comprising:
a first memory module mounted on a first side of a substrate, the first memory module comprising:
an array of connections arranged in rows and columns such that there are first and second outer columns, and that connections in the first and second outer columns can be interchanged;
a second memory module mounted on a second side of the substrate, comprising:
an array of connections arranged in rows and columns such that there are first and second outer columns, and that connections in the first and second outer columns can be interchanged;
a memory controller to control interchange of signals between first and second outer columns of the memory modules;
signal traces in the substrate, wherein the connection in the first and second outer columns of the first and second memory modules are arranged such that signals routed on the traces have uniform routing lengths.
6. The memory system of claim 5, the substrate further comprising a multi-layered printed circuit board.
7. The memory system of claim 6, signal traces further comprising multiple signal traces in multiple layers of the printed circuit board.
8. The memory system of claim 5, the memory modules being packaged in a package selected from the group comprised of: X16 and X4/X8.
9. A memory device, comprising:
a memory array having an array of memory connections arranged in rows and columns;
a module to receive the memory array;
a connector on the module having an array of connector connections arranged in rows and columns, such that the memory connections and the connector connections can be interchanged.
10. The memory device of claim 9, the module further comprising a dual, in-line memory module.
11. The memory array of claim 10, the module being selected from the group comprised of: a X16 package, and an X4/X8 package.
12. A method of designing a memory device, comprising:
determining an interchangeable set of memory signals and a fixed set of memory signals;
arranging the interchangeable set of memory signals in outer columns of a connection array; and
arranging the fixed set of memory signals in inner columns of a connection array.
13. The method of claim 12, determining an interchangeable set of memory signals further comprising identifying address connections within a row as being interchangeable.
14. The method of claim 12, determining an interchangeable set of memory signals further comprising identifying bank address connections as being interchangeable.
15. The method of claim 12, arranging the interchangeable set of memory signals in outer column further comprising arranging the interchangeable set of memory signals in two outer columns on each side of the connection array.
16. The method of claim 12, arranging the interchangeable set of memory signals in outer column further comprising arranging the interchangeable set of memory signals in one outer column on each side of the connection array.
Description
    BACKGROUND
  • [0001]
    Currently, memory packages, such as dual, in-line memory modules (DIMM) may reside on both sides of a printed circuit board (PCB) or other substrate. This increases memory density for the system. Signals for the memories may route through the substrate, which may have several layers. With memory packages on both sides of the substrate, signal routing and integrity may become an issue.
  • [0002]
    Signals being routed through the substrate may connect to balls or connections to the DIMM on opposite sides of the packages. For examples, signals going to the closest side of the package on the one side of the substrate will generally end up having to go to the farthest side of the package on the other side of the substrate. The DIMM for the other side of the package is turned ‘upside down’ to mount it on the other side, causing the relevant connection to be on the other side of the package from the signal origination.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0003]
    Embodiments of the invention may be best understood by reading the disclosure with reference to the drawings, wherein:
  • [0004]
    FIG. 1 shows a prior art embodiment of a double-sided, dual, in-line memory module mounting.
  • [0005]
    FIG. 2 shows an embodiment of a double-sided, dual, in-line memory module mounting.
  • [0006]
    FIGS. 3 a and 3 b show alternative arrangements of memory packages on a substrate.
  • [0007]
    FIG. 4 shows an embodiment of a memory system using double-sided memory modules.
  • [0008]
    FIGS. 5 a and 5 b show alternative embodiments of stacked memory modules.
  • [0009]
    FIG. 6 shows a connection diagram for an embodiment of a dual, in-line memory module having interchangeability.
  • [0010]
    FIG. 7 shows a connection diagram for an alternative embodiment of a dual, in-line memory module.
  • [0011]
    FIG. 8 shows a connection diagram for another alternative embodiment of a dual, in-line memory module.
  • [0012]
    FIG. 9 shows a block diagram of an embodiment of a method to design dual, in-line memory module.
  • DETAILED DESCRIPTION OF THE EMBODIMENTS
  • [0013]
    FIG. 1 shows a prior art embodiment of a double-sided, dual, in-line memory module (DIMM) mounting on a substrate. Double-sided refers to the fact that the memory modules are mounted on opposite sides of the substrate. The substrate 10 may be a multi-layered PCB, or any other substrate upon which DIMMs are mounted. Memory modules 12 a and 12 b are mounted on opposite sides of the substrate from each other, as are memory modules 14 a and 14 b. The substrate 10 has internally routed signal traces 16 a and 16 b. Stub 18 through via 13 allows the solder ball or other connection from the module 12 a to connect to the first signal trace 16 a.
  • [0014]
    The via 13 is manufactured on a larger pitch than the signal traces to afford extra width, and the use of several vias can limit the number of traces that can be routed through a single layer of the substrate 10. This may force additional layers and extra costs. In addition, to avoid shorting signals into the internal power and ground plane layers of the substrate 10, anti-pads are typically used in the power plane layers, which compromise power delivery to the memories within the modules.
  • [0015]
    Double-data rate memory (DDR) uses both the rising and falling edges of a clock signal to operate the memory, resulting in twice the speed of memories using either the leading or the falling edge of the clock signal. DDR3 is the third version of DDR. In DDR3, as well as other memory types, the command/address bus is a daisy-chained or ‘fly-by’ bus. This type of bus may have problems with signal integrity due to the unequal routing lengths caused by double-sided memory mounting.
  • [0016]
    As shown in FIG. 1, signal 16 a has a first routing length 28 a between the connections 20 and 26. The second routing length is between connection 26 on module 12 b and ball 30 on module 14 a. The second routing length 28 b is far shorter than the first. A similar length difference occurs for signal 16 b, with the first routing length being from connection 22 to connection 24, and the second routing length being from connection 24 on module 12 a to connection 32 on module 14 b. It must be noted that connections 20, 22, 24, 26, 30, 32, 34 and 36, are shown here as solder balls, but could be any type of connection used to provide connection between the integrated circuit die and the substrate.
  • [0017]
    The difference in routing lengths results in non-uniform effective channel impedance. This limits the ability of the devices to receive recognizable signals. Typically, systems are designed to have very regularly and evenly spaced loads and the line is tuned to match the loads. If there is no impedance matching, the signal integrity becomes questionable and higher data rates cannot be supported.
  • [0018]
    In one approach, the prior art has attempted to perform routing in the semiconductor of the die itself. Connections are redefined to be a different signal using logic in the die to ‘mirror’ the signal. Logic required in the data path introduces latency in the path, as well as overhead into the device manufacture.
  • [0019]
    It is possible to interchange the physical connectivity of the various connections at the memory module level, avoiding introduction of logic in the data path, while providing the same benefits as mirroring. An example is shown in FIG. 2.
  • [0020]
    The routing lengths in this embodiment have become uniform. The term ‘uniform’ as used here does not mean that they are exactly the same, although that may be the case. Uniformity, as used here, means that the impedances in the signal paths are closely matched to each other between loads. Routing length 1 is now the length from the connection 20 to the connection 30, and routing length 2 is the length from the connection 30 to the connection for the same signal on the next device, not shown. The loads are now more uniformly spaced, which allows the devices to support higher data rates with good signal integrity.
  • [0021]
    In addition, the configuration shown in FIG. 2 has a reduced number of vias. The interchange of signals from the far side of the bottom-side memory modules 12 b and 14 b have moved to the near side allow the signals to share vias. Reducing the number of vias eases the restrictions on trace spacing, allowing more traces to be placed in a given layer. In turn, this may reduce the number of layers needed in the substrate, reducing costs, as well as mitigating shorts in the power and ground planes.
  • [0022]
    In order for this approach to be practical, there must be some signals that can be interchanged between the two sides of the module. In order to allow better understanding of the definition of interchangeable signals, it is helpful to discuss how memory modules are typically laid out on a substrate. As shown in FIG. 3, a memory controller 38 has a data output of 64 bytes. Each module 40 a-40 h on the substrate 10 is a X8 module; each one can receive 8 bytes of memory.
  • [0023]
    It must be noted that in one embodiment of the invention, the interchangeable signals can be selected such that the footprint of the different types of packages can be optimized. As shown in memory module 40 a, for example, the data lines have been arranged such that is the package is a X4/X8 package, the data lines are either DQ0-3 for a X4 memory, or DQ0-7 for a X8 package. If the package is a X16 package, all of the data lines are present and DQ0-15 are available for interchangeability. Also, while data lines may be interchangeable within a byte ‘lane,’ such as DQ[0:7] and DQ[8:15], the adaptability of the interchangeable signals to different package types is enhance if the interchangeability is limited to be within nibbles, such as DQ[0:3], DQ[4:7], DQ[8:1] and DQ[12:15].
  • [0024]
    Interchangeability actually occurs at the controller 38. The DRAM and the DIMM have no ‘knowledge’ of what is on any data, whether that data is actually for DQ1 or DQ15. Therefore, these signals are interchangeable. Other types of signals have been identified as being interchangeable, as will be discussed further on. It must be noted that while the data out of the controller is 64 bytes, there are also address and rank-based signals that are sent from the controller in a daisy-chained or ‘fly-by’ fashion. The signals are passed along a bus and it is the distance between the relevant connections to this bus for which the routing length is desired to be uniform. The interchanging of the signals transmitted from the connections as shown in FIG. 2 is what provides this uniformity.
  • [0025]
    Interchangeability is possible in most memory layouts. For example, the memory system in FIG. 4 employs double-sided memory substrates. In addition to the modules 40 a-40 h on the side facing the viewer, modules such as 42 a are on the side away from the viewer. Memory modules arranged in such a system are generally addressed using rank-based signals, such as chip select (CS). In this particular embodiment, the address and rank based signals for the two different ranks are shown coming out of the controller. Generally, rank-based signals are not interchangeable.
  • [0026]
    Similarly, interchangeability can be performed using ‘stacked’ memory modules, such as those shown in FIGS. 5 a and 5 b. FIG. 5 a shows an example of a stacked memory arrangement where the connections between the two memory dies 44 a and 44 b are internal and they use a common connection array such as ball 46. In FIG. 5 b, each module 44 a and 44 b have their own external connection array, such as solder balls 46 a and 46 b. Interchangeability can be employed in this arrangement as well.
  • [0027]
    Modules are generally arranged as an array of connections, in rows and columns. As will be discussed with regards to FIGS. 6-8, the arrangement of the connections will be assumed to be in at least four columns, although three columns are possible. This assumption is based upon a typical DRAM layout of 15 or 16 rows of connections by 9 columns. Generally there are no connections in the middle 3 columns, leaving 3 columns on either ‘side’ of the module.
  • [0028]
    In the discussion of interchangeable signals, several different signal abbreviations may be used. These are included with their descriptions in the table below.
    Abbreviation Signal Name Comments
    VSS Core ground Usually tied together
    VSSQ I/O ground at substrate
    VDD Core power Usually tied together
    VDDQ I/O power at substrate
    RFU Reserved for future use
    CLK/CLK# DRAM input clock
    DQ[0:15] Data signals Lower and upper bytes
    (0:7, 8:15)
    DQS/DQS# Strobes for data clock One for upper and
    into the DRAM lower bytes
    DM Data mask signal One for upper and
    lower bytes
    VREFDQ Voltage reference pin
    for data
    CS Chip select
    CKE Clock enable
    ODT On-die termination
    RAS Row address select
    CAS Column address select
    WE Write enable
    RST Reset
    ZQ Impedance calibration pin
    sCS Stacked chip select
    sCKE Stacked clock enable
    sODT Stacked on-die termination
    sZQ Stacked impedance
    calibration pin
    A[0:15] Address
    BA[0:3] Bank address
    VREFCA Voltage reference for
    command/address
  • [0029]
    Interchangeable signals will generally include DQ signals within a byte ‘lane’ such as DQ[0:7] and DQ[8:15]. Bank addresses, BA[0:3] may be interchangeable. It is possible that BA[2:3] are not present, so only BA[0:1] may be interchanged. Address connections within a row, such as A[3:9] are interchangeable. Generally, VDD and VSS connection locations can be moved around to share vias as well, although this is not shown in the example.
  • [0030]
    FIG. 6 shows a general embodiment of a memory module layout to allow for interchangeable signals. As can be seen, the example is a 169 array of connections. The array has been arranged in nine columns, with the outer two columns 51, 52, 58 and 59 on either side being identified as for use by interchangeable signals and the middle two columns 53 and 56 being identified as for use by non-interchangeable signals. The outer two columns on each side may be interchangeable providing four interchangeable columns, or only the outer one column on each side providing only two interchangeable columns.
  • [0031]
    A more specific embodiment of a connection 169 layout is shown in FIG. 7. In this example, VDDQ and VSSQ have had their locations redefined to share vias front to back. Further, A3 and A4, A5 and A6, and A7 and A8 can share vias at the DIMM level. This particular layout has a further advantage that there are only 4 signals per row of the DIMM, allowing better trace separation for the signal traces, further increasing the signal integrity. Reserved for future use (RFU) connections at column 52, rows J and L may be used for sODT, and sCS. Similarly, RFU at column 58, row J could be used for sCKE, and at row D for sZQ.
  • [0032]
    It is possible to get a 159 connection layout with some modifications of these rules. If a 2:1 ration of signal to ground pattern can be achieved, and 2 connections are removed, it is possible to achieve a 159 connection layout with interchangeable connections. An embodiment of this is shown in FIG. 8. In this embodiment, the ODT signal has been removed and the bank address 3, BA3 and address 15, A15, share a connection. The RFU connection at column 52, row L becomes BA0.
  • [0033]
    With these possible layouts in mind, it is helpful to return to FIGS. 1 and 2. Imagine that the connections 20 and 22 correspond to a location in column 1 of a connection array, and connections 24 and 26 correspond to a location in column 9. In FIG. 1, this results in the uneven routing lengths and the extra vias. If the controller were to interchange the signals between columns 1 and 9, moving the signals that had previously been using connection 22 to column 9 and the signals previously using connection 26 to column 1, the result would appear as in FIG. 2. The connections 22 and 26 remain in the same place, the signals that had been routed to those columns are interchanged so that connections 20 and 22, and 24 and 26 can be connected together. The availability of interchangeable signals between the outer columns of the connection array allow for the optimization of the connection layout for double-sided DIMM or other module placement.
  • [0034]
    Further adjustments and variations on the interchangeable signals are of course possible. For example, the interchangeable signals can also be applied to stacked DRAM technology. In addition, variations of the package type can be employed. For example, the X16 package type may be used, as well as the X4/X8 package type.
  • [0035]
    Thus, although there has been described to this point a particular embodiment for a method and apparatus for interchangeable connections in a memory module, it is not intended that such specific references be considered as limitations upon the scope of this invention except in-so-far as set forth in the following claims.
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Classifications
U.S. Classification365/51
International ClassificationG11C5/02, G11C5/00, H05K1/18
Cooperative ClassificationY02P70/611, H05K2203/1572, H05K1/181, H01L23/49816, H05K2201/10159, G11C5/02, H05K2201/10734, H01L2224/16225, H01L2224/16145, H01L2224/16
European ClassificationH05K1/18B, G11C5/02
Legal Events
DateCodeEventDescription
Aug 25, 2004ASAssignment
Owner name: INTEL CORPORATION (A DELAWARE CORPORATION), CALIFO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEDDIGE, MICHAEL W.;BAINS, KULJIT;SPRIETSMA, JOHN T.;REEL/FRAME:015084/0142;SIGNING DATES FROM 20040301 TO 20040302