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Publication numberUS20050196960 A1
Publication typeApplication
Application numberUS 11/113,980
Publication dateSep 8, 2005
Filing dateApr 26, 2005
Priority dateOct 17, 2002
Also published asUS6936528, US20040132268
Publication number11113980, 113980, US 2005/0196960 A1, US 2005/196960 A1, US 20050196960 A1, US 20050196960A1, US 2005196960 A1, US 2005196960A1, US-A1-20050196960, US-A1-2005196960, US2005/0196960A1, US2005/196960A1, US20050196960 A1, US20050196960A1, US2005196960 A1, US2005196960A1
InventorsKyeong-Mo Koo, Ja-hum Ku, Hye-Jeong Park
Original AssigneeKyeong-Mo Koo, Ku Ja-Hum, Hye-Jeong Park
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method of forming metal silicide film and method of manufacturing semiconductor device having metal silicide film
US 20050196960 A1
Abstract
A metal-containing film is formed on a silicon-containing conductive region at a temperature where the metal of the metal-containing film and silicon of the semiconductor substrate react with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the and the semiconductor substrate. The resultant structure is annealed so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form a metal silicide film.
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Claims(19)
1. A method of forming a metal silicide film, comprising:
forming a metal-containing film on a surface of a semiconductor substrate having an insulating region and a silicon-containing conductive region, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the silicon-containing conductive region; and
annealing the resultant structure so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form the metal silicide film.
2. The method of claim 1, further comprising forming a titanium-rich capping film on the metal-containing film prior to the annealing.
3. The method of claim 1, wherein metal-containing film is at least one selected from the group consisting of TaN, NiTa, Ti, TiN, Ta, W, WN, Hf, Nb, Mo, RuO2, Mo2N, Ni, Ir, Pt, Cr, RuO, Mo2N, WNx, NiPt, or a combination thereof.
4. The method of claim 2, wherein the annealing, comprises:
a first annealing at a temperature range of 350 to 650 C.;
removing the titanium-rich capping film; and
a second annealing at a temperature range of 700-900 C.
5. The method of claim 1, wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate; and
etching the semiconductor substrate by radio frequency (RF) sputtering.
6. The method of claim 1, wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate using a hydrogen fluoride (HF) solution diluted with deionized (DI) water;
wet-cleaning the surface of the semiconductor substrate using a mixture solution of ammonium hydroxide, hydrogen peroxide (H2O2), and water; and
wet-cleaning the surface of the semiconductor substrate using a HF solution diluted with DI water.
7. The method of claim 1, wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate using a mixture solution of sulfuric acid and H2O2; and
wet-cleaning the surface of the semiconductor substrate using a HF solution diluted with DI water.
8. The method of claim 1, wherein the metal-containing film is formed at a temperature range of 300-500 C.
9. A method of manufacturing a semiconductor device, said method comprising:
forming an isolation region defining an active region on a semiconductor substrate;
forming on the active region a transistor having source/source regions and a gate;
forming a metal-containing film on a surface of the semiconductor substrate, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the semiconductor substrate react with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the and the semiconductor substrate; and
annealing the resultant structure so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form the metal silicide film.
10. The method of claim 9, further comprising forming a titanium-rich capping film on the metal-containing film.
11. The method of claim 9, wherein forming of the metal-containing film comprises forming the metal-containing film exclusively on a surface of the gate, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the gate to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the gate.
12. The method of claim 9, wherein forming of the metal-containing film comprises forming the metal-containing film exclusively on a surface of the source/drain region, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the source/drain regions to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the source/drain region.
13. The method of claim 9, wherein forming of the metal-containing film comprises forming the metal-containing film on a surface of the source/drain region and the gate, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the source/drain regions and the gate to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the source/drain region and the gate.
14. The method of claim 9, wherein metal-containing film is at least one selected from the group consisting of TaN, NiTa, Ti, TiN, Ta, W, WN, Hf, Nb, Mo, RuO2, Mo2N, Ir, Pt, Cr, RuO, Mo2N, WNx, NiPt, or a combination thereof.
15. The method of claim 10, wherein the annealing, comprises:
a first annealing at a temperature range of 350 to 650 C.;
removing the titanium-rich capping film; and
a second annealing at a temperature range of 700-900 C.
17. The method of claim 9, wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate; and
etching the semiconductor substrate by radio frequency (RF) sputtering.
18. The method of claim 9, wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate using a hydrogen fluoride (HF) solution diluted with deionized (DI) water;
wet-cleaning the surface of the semiconductor substrate using a mixture solution of ammonium hydroxide, hydrogen peroxide (H2O2), and water; and
wet-cleaning the surface of the semiconductor substrate using a HF solution diluted with DI water.
19. The method of claim 9, wherein a pretreatment process is performed prior to the formation of the metal-containing film, and the pretreatment process comprising:
wet-cleaning the surface of the semiconductor substrate using a mixture solution of sulfuric acid and H2O2; and
wet-cleaning the surface of the semiconductor substrate using a HF solution diluted with DI water.
20. The method of claim 9, wherein the metal-containing film is formed at a temperature range of 300-500 C.
Description
    CROSS-REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This is a continuation application of U.S. patent application Ser. No. 10/686,768, filed on Oct. 17, 2003, which is a continuation-in-part of U.S. patent application Ser. No.10/457,449, filed Jun. 10, 2003, now abandoned, the entire contents of which are incorporated herein by reference. In addition, a claim of priority is made to Korean Patent Application Nos. 2002-63567 and 2003-66498, filed Oct. 17, 2002 and Sep. 25, 2003, respectively, the entire contents of which are incorporated herein by reference.
  • BACKGROUND OF THE INVENTION
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention generally relates to the fabrication of semiconductor devices, and more particularly, the present invention relates to a method of forming a metal-containing film and to a method of manufacturing a semiconductor device having a metal silicide film.
  • [0004]
    2. Description of the Related Art
  • [0005]
    As the gate resistance and source/drain contact resistance of a metal oxide semiconductor (MOS) increases, the operation speed of a semiconductor device containing the MOS transistor decreases. Accordingly, silicide films have been widely used to decrease these resistances. Metal silicide films, such as cobalt silicide films, in particular monocobalt disilicide (CoSi2) films, are especially useful in view of their low resistance (16 to 18 μΩ cm), good thermal stability, and reduced sheet resistance (Rs) dependency to size. Cobalt silicide films have been used in static random access memory (SRAM) devices and in logic devices that require high operational speeds.
  • [0006]
    A cobalt silicide film having poor characteristics can result if impurities such as silicon oxide and silicon nitride are present at a surface of a silicon region on which the cobalt silicide film is formed. For this reason, prior to deposition of the cobalt silicide film, a substrate surface is conventionally wet-cleaned and then etched by radio frequency (RF) sputtering. Unfortunately, however, substrate surface defects can result since RF sputter etching using argon ions (Ar+) is a physical etching process. In addition, resputtering occurs during the RF sputter etching which can result in a poorly formed cobalt silicide film, which can create short-circuits between active regions.
  • [0007]
    FIG. 1 is a plan view of a semiconductor device in which a cobalt silicide film has created a short-circuit between active regions. In FIG. 1, reference numeral 3 denotes an active region, reference numeral 4 is a well region boundary, reference numeral 5 denotes a gate, reference numeral 7 denotes a gate spacer, and reference numeral 11 c indicates a cobalt silicide film. As shown, the colbalt silicide film 11 c is defective in that it connects adjacent active regions 3 across the well region boundary 4.
  • [0008]
    FIG. 2 is a diagram to illustrate the occurrence of resputtering during RF sputter etching, and FIG. 3 is a diagram illustrating a poorly formed cobalt silicide film resulting from the resputtering. FIGS. 2 and 3 are sectional views taken along line 11-11′ of FIG. 1.
  • [0009]
    As shown in FIG. 2, during the RF sputter etching 10, an oxide 2 a of a shallow trench device isolation region (STI) 2 and/or a nitride 7 a of a spacer 7 is resputtered onto an active region 3 or a gate 5 of a semiconductor device. Also, silicon 3 a of the active region 3 is resputtered on the spacer 7.
  • [0010]
    As shown in FIG. 3, the resputtered oxide 2 a and nitride 7 a cause a cobalt silicide film 11 a formed on the active region 3 and a cobalt silicide film 11 b formed on the gate 5 to have a nonuniform thickness. Also, the resputtered silicon 3 a causes a cobalt silicide film 11 c to be formed along sidewalls of the spacer 7. This can result in the short-circuiting of active regions 3 as shown in FIG. 1.
  • [0011]
    Meanwhile, referring to FIG. 4, transformation of a cobalt film 11 formed on the front surface of a substrate into a cobalt silicide film mainly takes place at the edges of a gate 5 a pattern and the edges at which the STI 2 and active region 3 are in contact with each other. This phenomenon is called an “edge effect” and is denoted by reference number 13 in FIG. 4. The edge effect causes the thickness of the cobalt silicide film 11 d to increase, which in turn causes loading of the Rs of the silicide film, making it difficult to adjust the Rs value. Furthermore, the edge effect can cause leakage current at the source/drain region 8. These drawbacks are intensified as the critical dimension (CD) of the gate is reduced to less than 100 nm. As shown in FIG. 4, the thickness of a cobalt silicide film 11 e formed at the gate 5 b having a small CD is almost twice as large as that of the cobalt silicide film 11 d formed at the gate 5 a having a larger CD. This creates a limitation in decreasing the aspect ratio of the gate 5 b pattern, which adversely affects the process margin for subsequent processes.
  • SUMMARY OF THE INVENTION
  • [0012]
    The present invention provides a method of forming a metal silicide film having favorable characteristics.
  • [0013]
    An embodiment of the present invention provides a method of forming a silicide film by forming a metal-containing film on a surface of a semiconductor substrate having an insulating region and a silicon-containing conductive region, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the silicon-containing conductive region, and annealing the resultant structure so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form the metal silicide film.
  • [0014]
    Another embodiment of the present invention provides a method of manufacturing a semiconductor device by forming an isolation region defining an active region on a semiconductor substrate, forming on the active region a transistor having source/source regions and a gate, forming a metal-containing film on a surface of the semiconductor substrate, the metal-containing film being formed at a temperature at which metal of the metal-containing film and silicon of the semiconductor substrate with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the and the semiconductor substrate, and annealing the resultant structure so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form the metal silicide film.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0015]
    The above and other aspects of the present invention will become readily apparent from the detailed description that follows, with reference to the accompanying drawings, in which:
  • [0016]
    FIG. 1 is a plan view illustrating a short-circuit between active regions resulting from a conventional method of forming a cobalt silicide film;
  • [0017]
    FIG. 2 is a sectional view illustrating a resputtering that occurs during a conventional method of forming a cobalt silicide;
  • [0018]
    FIG. 3 is a sectional view illustrating a poorly formed cobalt silicide film formed by resputtering;
  • [0019]
    FIG. 4 is a sectional view to illustrate an edge effect resulting from a conventional method of forming a cobalt silicide film, and a loading of the sheet resistance (Rs) of the silicide film caused by the edge effect;
  • [0020]
    FIG. 5 is a flow chart of a method of forming a cobalt silicide film according to one embodiment of the present invention;
  • [0021]
    FIGS. 6A through 6D are sectional views of intermediate structures formed in the steps disclosed in FIG. 5;
  • [0022]
    FIG. 7 is a sectional view to illustrate a diffusion restraint characteristic of an interface film formed in the deposition of a cobalt film at a high temperature;
  • [0023]
    FIGS. 8A and 8B are scanning electron microphotographs (SEMs) of cobalt silicide films formed according to an embodiment of the present invention;
  • [0024]
    FIGS. 9A and 9B are SEMs of control sample cobalt silicide films for comparison with the films of FIGS. 8A and 8B;
  • [0025]
    FIGS. 10A and 10B are graphs showing Rs values of gates having cobalt silicide films according to an embodiment of the present invention and according to a conventional method;
  • [0026]
    FIG. 11A is a graph showing secondary ion-mass spectrometric (SIMS) results after primary rapid thermal annealing (RTA) according to an embodiment of the present invention and according to a conventional method;
  • [0027]
    FIG. 11B is a graph showing SIMS results after a selective wet etching according to an embodiment of the present invention and according to a conventional method;
  • [0028]
    FIG. 12 is a graph showing a leakage current of a test sample which has been pretreated by a wet-clean process only according to the present invention, and a leakage current of a control sample which has been pretreated by a wet-clean process and then etched by radio frequency (RF) sputtering according to a conventional method;
  • [0029]
    FIG. 13A is a transmission electron microphotograph (TEM) of a sample formed after depositing a cobalt film at a high temperature according to an embodiment of the present invention;
  • [0030]
    FIGS. 13B and 13C show selected area diffraction (SAD) patterns of an interface film formed by the high temperature deposition in FIG. 13A; and
  • [0031]
    FIG. 14 is a graph showing leakage current characteristics in the case of depositing a cobalt film at a high temperature according to an embodiment of the present invention and in the case of depositing a cobalt film according to a conventional method.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0032]
    Embodiments of the present invention disclose the deposition of a titanium (Ti) rich film on a previously formed metal-containing film. Ti, which is abundantly present in a capping film, diffuses toward an interface between the metal-containing film and an underlying silicon containing layer, such as a bulk Si film or a (poly)Si film, which assists in the removal of oxides and nitrides at the interface. The removal of oxides and nitrides results in high quality metal silicide film. Further, the present invention further discloses the use of a wet pretreatment process that sufficiently removes a natural oxide film formed at a surface intended for formation of the metal silicide film. Pretreatment by radio frequency (RF) sputter etching may or may not be required. In this regard, as used herein, the phrase “wet cleaning is used/carried out alone” means that a RF sputter etching is omitted in the pretreatment process. Still further, the present invention discloses the formation of a metal film at a high temperature to compensate for the small process window for formation of a metal silicide film resulting from the edge effect.
  • [0033]
    Hereinafter, by way of example, a method of forming a cobalt silicide film on a gate and an active region in a full CMOS (complementary metal oxide semiconductor)-type SRAM (static random access memory) device will be described. However, it is generally understood that the metal-containing film can be selected from TaN, NiTa, Ti, TiN, Ta, W, WN, Hf, Nb, Mo, RuO2, Mo2N, Ni, Ir, Pt, Cr, RuO, Mo2N, WNx, and combination thereof.
  • [0034]
    FIG. 5 is a flow chart of a method of forming a cobalt silicide film according to an embodiment of the present invention. FIGS. 6A through 6D are sectional views of intermediate products resulting from the process steps of FIG. 5.
  • [0035]
    Referring to FIGS. 5 and 6A, first, a transistor (Tr) is formed (step S1). In detail, after forming a shallow trench isolation (STI) region 102 using a conventional process, an N-well 101 and a P-well (not shown) are formed on a p-type Si substrate 100 by ion injection. Then, on the substrate 100, an oxide film is formed to a thickness of 110 to 130 Å and a poly-Si film is formed to a thickness of 1,500 to 2,500 Å, followed by successive patterning, to form a gate 105 and a gate oxide film 104. The gate oxide film 104 may be formed by depositing an oxide such as silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, and lanthanum oxide using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD). The gate 105 made of poly-Si may be formed by depositing poly-Si doped with impurity using low pressure CVD (LPCVD). Poly-Si may be simultaneously deposited with impurity doping, or may be doped with impurity after deposition. Then, ion injection is carried out to form a lightly doped drain (LDD) region. A LDD 106 n for an NMOS transistor is formed by injecting an n-type ion such as As+, and then a LDD 106 p for a PMOS transistor is formed by injecting a p-type ion such as BF2 +. Then, a spacer 107 is formed at a sidewall of the gate 105. The spacer 107 may be a silicon nitride film or may be a laminated structure of a middle temperature oxide (MTO) film and a silicon nitride film. After the formation of the spacer 107, an n+ source/drain region 108 n is formed by injecting an n-type ion such as As+, and a p+ source/drain region 108 p is formed by injecting a p-type ion such as BF2+. Finally, an NMOS source/drain (109 n) and a PMOS source/drain (109 p) are formed.
  • [0036]
    FIGS. 5 and 6B illustrates a pretreatment process (steps S2 and S3′). After the pretreatment process, a Co-containing film 111 is formed (step S3) is formed followed by the formation of a Ti-rich capping film 113 (step S4). In the pretreatment process (steps S2 and S3′), impurities, for example, natural oxide films formed on the source/drain regions 109 n and 109 p and the gate 105, and/or nitride particles remaining from formation of the spacer 107, are removed. For the pretreatment process, a wet cleaning (step S2) may be used alone or in combination with RF sputter etching (step S3′).
  • [0037]
    Impurities such as oxide and nitride may also be generated due to resputtering caused after RF sputter etching. However, as will be described later, these impurities are typically removed by Ti which is abundantly present in the capping film 113.
  • [0038]
    The RF sputter etching can be selectively carried out as required. Various modifications in the wet cleaning may be made according to whether or not the subsequent RF sputter etching is carried out. In a case where the RF sputter etching is carried out, the wet cleaning may be lightly carried out. On the other hand, in a case where the RF sputter etching is omitted, the wet cleaning is carried out so that impurities such as a natural oxide film are completely removed.
  • [0039]
    In a case where the RF sputter etching is omitted, the wet cleaning may be carried out in two processes. The first process for the wet cleaning is divided into three steps: using a hydrogen fluoride (HF) solution diluted with deionized (DI) water (first step); using a mixture solution (also known as SC1 solution) of ammonium hydroxide, hydrogen peroxide (H2O2), and water (second step); and, using a HF solution diluted with DI water. A 100:1 diluted HF solution or a 200:1 diluted HF solution may be used as the diluted HF solution. The first step is carried out for about 10 to 300 seconds, preferably about 150 seconds, the second step is carried out at a temperature of 40 to 90 C., preferably 70 C., for about 1 to 60 minutes, preferably about 30 minutes, and the third step is carried out for about 10 to 300 seconds, preferably about 60 seconds. The second process for the wet cleaning is divided into two steps: using a mixture solution of sulfuric acid and H2O2 (first step) and using a HF solution diluted with DI water (second step). Preferably, the ratio of sulfuric acid to H2O2 is 6 to 1. A 100:1 diluted HF solution or a 200:1 diluted HF solution may be used as the diluted HF solution. The first step is carried out at 120 C. for about 500 to 700 seconds, preferably 600 seconds, and the second step is carried out for 150 to 300 seconds, preferably 250 seconds.
  • [0040]
    On the other hand, in a case where the RF sputter etching is carried out, the steps in the above-described two wet cleaning processes may be carried out for a shorter time. Alternatively, the wet cleaning may be carried out only using a diluted HF solution.
  • [0041]
    Next, the Co-containing film 111 is conformally formed along an exposed stepped surface of the substrate 100 (step S3).
  • [0042]
    The Co-containing film 111 may be a pure Co film made of 100% Co or a Co alloy film. Preferably, the Co alloy film contains 20 or less atomic % of one selected from tantalum (Ta), zirconium (Zr), titanium (Ti), nickel (Ni), hafnium (Hf), tungsten (W), platinum (Pt), palladium (Pd), vanadium (V), niobium (Nb), and mixtures thereof.
  • [0043]
    The Co-containing film 111 is formed by sputtering. The thickness of the Co-containing film 111 is determined according to the critical dimension (CD) or height of the gate 105. For example, if the CD of the gate is 100 nm, it is preferable to form the Co-containing film to a thickness of less than 150 Å.
  • [0044]
    The Co-containing film 111 may be deposited at a temperature higher than room temperature. However, it is preferable to deposit the Co-containing film 111 at a high temperature of 300 to 500 C. When the Co-containing film 111 is deposited at a high temperature, as shown in an enlarged circle of FIG. 6B, Co of the Co-containing film 11 reacts with Si of the source/drain regions 109 n and 109 p and poly-Si of the gate 105, to thereby form an interface film 115 a made of dicobalt monosilicide (Co2Si) or monocobalt monosilicide (CoSi). The interface film 115 a serves to restrain diffusion of Co during a subsequent annealing process. The detailed description thereof will be described later.
  • [0045]
    Next, a Ti-rich capping film 113 is formed on the Co-containing film 111 (step S4). As used herein, the term, “Ti-rich capping film” indicates a film with a Ti/other elements atomic % ratio of more than 1. The Ti-rich capping film may be one selected from the group consisting of a titanium nitride film with a Ti/nitrogen (N) atomic % ratio of more than 1, a titanium tungsten film with a Ti/W atomic % ratio of more than 1, a laminated structure of a pure Ti film and a titanium nitride film with a Ti/N atomic % ratio of more than 1, a laminated structure of a pure Ti film and a titanium nitride film with a Ti/N atomic % ratio of less than 1, a laminated structure of a pure Ti film and a titanium tungsten film with a Ti/W atomic % ratio of more than 1, and a laminated structure of a pure Ti film and a titanium tungsten film with a Ti/W atomic % ratio of less than 1. The Ti-rich capping film 113 may also be a pure Ti film made of 100% Ti.
  • [0046]
    The capping film 113 is also formed by sputtering. For example, in the case of a titanium nitride film with a Ti/N atomic % ratio of more than 1, the capping film 113 with a desired composition ratio can be formed by depositing a Ti target while adjusting the flow rate of a nitrogen gas supplied into a sputtering apparatus. The function of the capping film 113 will be described later.
  • [0047]
    Preferably, the RF sputter etching (step S3′), the formation of the Co-containing film (step S3), and the formation of the Ti-rich capping film (step S4) are formed in situ.
  • [0048]
    Referring to FIGS. 5 and 6C, the resultant structure having the Co-containing film 111 and the Ti-rich capping film 113 are annealed at a low temperature (step S5). The low temperature annealing may be a rapid thermal annealing (RTA) at a temperature range of 350 to 650 C.
  • [0049]
    When the low temperature annealing begins, Ti in the capping film 113 efficiently removes residual impurities on upper surfaces of the source/drain regions 109 n and 109 p, and the gate 105, which are in contact with the Co-containing film 111.
  • [0050]
    The Ti removes impurities such as oxide, nitride, and silicon, which are generated by the RF sputter etching for pretreatment carried out before the formation of the Co-containing film 111.
  • [0051]
    Ti also removes impurities generated on an exposed surface of the substrate 100 during a delay time between the wet cleaning and the formation of the Co-containing film 111 when the RF sputter etching is omitted. Such a delay time is caused because the wet cleaning and the formation of the Co-containing film are not carried out in situ.
  • [0052]
    Therefore, the Ti-rich capping film 113 serves to prevent formation of poor quality cobalt silicide film otherwise caused by impurities generated by the RF sputter etching. In addition, in the case where the wet cleaning pretreatment is used alone to prevent the generation of impurities, even though a surface of the substrate 100 is exposed to air for a long period of time after the wet cleaning, the Ti can remove impurities generated on the surface of the substrate 100 as a result of the exposure. Therefore, a process window for a delay time between the wet cleaning and the formation of the Co-containing film 111 is increased.
  • [0053]
    When Ti efficiently removes impurities, Co of the Co-containing film 111 diffuses toward the source/drain regions 109 n and 109 p and the gate 105 and then reacts with (poly)Si to thereby form a high quality CoSi film 115 b.
  • [0054]
    Meanwhile, the diffusion restraint interface film 115 a made of Co2Si or CoSi formed upon the formation of the Co-containing film 111 at 300 to 500 C. serves to decrease the diffusion speed of the Co, thereby retarding the formation of a cobalt silicide film. That is, referring to FIG. 7, Co2Si or CoSi that constitutes the diffusion restraint interface film 115 a is in a polycrystalline phase. For this reason, Co of the Co-containing film 111 placed on the interface film 115 a can diffuse toward the substrate 100 only through diffusion paths 200, i.e., polycrystalline grain boundaries. The number of diffusion paths 200 in the presence of the interface film 115 a is less than the number of diffusion paths 250 in the absence of the interface film 115 a. For this reason, in the presence of the interface film 115 a, less of the Co reacts with Si. Therefore, Rs loading and an increase in leakage current caused by the edge effect can be inhibited.
  • [0055]
    As a result of the low temperature annealing, Co2Si of the interface film 115 a is transformed into CoSi.
  • [0056]
    Referring to FIGS. 5 and 6D, a wet etching is carried out to selectively remove the capping film 113 and any remaining unreacted Co-containing film 111 by the low temperature annealing (step S6). The wet etching is carried out using a mixture solution of sulfuric acid and ammonium hydroxide or a mixture solution of phosphoric acid, acetic acid, nitric acid, and H2O2.
  • [0057]
    Next, an annealing at a high temperature is carried out (step S7). As a result of the high temperature annealing, the CoSi film 115 b is transformed into a CoSi2 film 115 c having low resistance. The CoSi2 film 115 c is more stable and has a lower resistance, when compared to the CoSi film 115 b. The high temperature annealing may be a rapid thermal anneal (RTA) at a temperature range of 700 to 900 C.
  • [0058]
    Embodiments described with reference to FIGS. 5 through 7 are directed to a self-align silicide process. If required, a silicide blocking film may be formed to protect regions which do not require cobalt silicidation.
  • [0059]
    In a dynamic random access memory (DRAM), a silicide film is formed only on a gate to decrease a gate resistance and to maintain an optimal refresh time. Therefore, a silicide film is not formed on an active region. In the case of a merged DRAM with logic (MDL) device which have recently gained notoriety in terms of high performance and small chip size, in a peripheral circuit and a logic, a silicide film is formed both on an active region and a gate or on a part of the active region and a part of the gate to reduce a contact resistance or a sheet resistance of the gate and source/drain. On the other hand, in a memory cell array, a silicide film is formed only on a gate to maintain an optimal refresh time. In the case of a nonvolatile memory device, a silicide film is formed only on a gate to prevent a resistance increase resulting from a decrease in gate length accompanying an increase in pattern density. In addition, when needed, instead of forming a silicide film on a gate, a silicide film may be formed only on a source/drain region.
  • [0060]
    Therefore, the silicide blocking film is used to expose only regions intended for formation of a silicide film. The formation of the silicide blocking film may be carried out prior to the wet cleaning.
  • [0061]
    Hitherto, the formation of a cobalt silicide film on a source/drain and a gate has been described. However, it is understood that a cobalt silicide film can be formed at any conductive regions made of (poly) Si that require a low resistance.
  • [0062]
    Hereinafter, the present invention will be described in more detail with reference to non-limiting experimental examples.
  • EXPERIMENTAL EXAMPLE 1
  • [0063]
    A six-transistor (6Tr)-SRAM cell was manufactured on a semiconductor wafer substrate according to 110 nm design rules using the following method of forming a cobalt silicide film according to the present invention to prepare a test sample.
  • [0064]
    The front surface of the substrate having a poly-Si gate pattern with a sidewall spacer and a source/drain region (hereinafter, referred to as “underlying structure(s)”) was wet-cleaned using a SC1 solution and then a HF solution. The substrate was etched by RF sputtering using argon (Ar) gas to remove an oxide film to a thickness of 50 Å, a Co film was formed to a thickness of 100 Å by sputtering, and a Ti-rich, titanium nitride capping film was formed to a thickness of 100 Å with N2 gas. The RF sputter etching, the formation of the Co film, and the formation of the titanium nitride capping film were formed in situ. According to a Rutherfold backscattering spectroscopy (RBS) analysis, a Ti/N atomic % ratio in the capping film was 3.33.
  • [0065]
    A primary RTA was carried out at 450 C. for 90 seconds, the capping film and unreacted Co film were removed by a mixture solution of sulfuric acid and H2O2, and then a secondary RTA was carried out at 800 C. for 30 seconds.
  • [0066]
    The scanning electron microphotographs (SEMs) of CoSi2 films obtained are illustrated in FIGS. 8A and 8B. FIG. 8A is a top plan view of a gate and FIG. 8B is a top plan view of an active region exposed by a contact pattern.
  • [0067]
    Meanwhile, a control sample was prepared under the above-described process conditions except that the capping film was formed at an N2 flow rate of 85 sccm. According to a RBS analysis, a Ti/N atomic % ratio in the capping film of the control sample was 0.89.
  • [0068]
    The SEMs of CoSi2 films of the control sample are illustrated in FIGS. 9A and 9B. FIG. 9A is a top plan view of a gate and FIG. 9B is a top plan view of an active region.
  • [0069]
    In comparison between the SEMs of the test sample (FIGS. 8A and 8B) and the SEMs of the control sample (FIGS. 9A and 9B), the CoSi2 films formed by using the Ti-rich capping film according to the present invention exhibited better morphologies than those formed by using the N-rich capping films.
  • EXPERIMENTAL EXAMPLE 2
  • [0070]
    The sheet resistances (Rs) of NMOS gates and PMOS gates in the test sample and the control sample prepared in Experimental Example 1 were measured and the results are illustrated in FIGS. 10A and 10B. FIG. 10A shows the Rs of NMOS gates and FIG. 10B shows the Rs of PMOS gates. In FIGS. 10A and 10B, -◯—represents the test sample and -□—represents the control sample.
  • [0071]
    As shown in FIGS. 10A and 10B, while the test sample exhibited a very low, uniform Rs distribution, the control sample exhibited a very high, nonuniform Rs distribution. This result demonstrates that the Ti-rich capping film efficiently removes impurities such as oxide and nitrogen present in an interface between the Co film and a source/drain region or a gate.
  • EXPERIMENTAL EXAMPLE 3
  • [0072]
    A test sample and a control sample were prepared in the same manner as Experimental Example 1. Secondary ion-mass spectrometric (SIMS) results after primary RTA and after a selective wet etching are respectively shown in FIGS. 11A and 11B.
  • [0073]
    In FIGS. 11A and 11B, -♦—and -▾—represent the test sample and -∘—and -□—represent the control sample. As shown in FIG. 11B, the surface of the test sample (using Ti-rich capping film) had a higher Ti content than that of the control sample (using N-rich capping film), by as much as 102. In FIG. 11B, a region having the depth of 0 μm corresponds to the surface of a Si region before a primary RTA and, at the same time, to an interface of a Co film and a cobalt silicide film before a selective wet etching. Judging from the fact that a Si region is transformed into a cobalt silicide film while Co diffuses toward the Si region and the result of FIG. 11B, it can be seen that a large amount of Ti diffuses toward an interface between a Co film and a source/drain region or a gate region and then efficiently removes impurities at the interface.
  • EXPERIMENTAL EXAMPLE 4
  • [0074]
    A test sample was prepared in the same manner as in the preparation of the test sample in Experimental Example 1 except that a wet cleaning was carried out alone in the pretreatment process, i.e., the pretreatment did not include RF sputter etching. The wet cleaning was carried out by using a 200:1 diluted HF solution for 150 seconds, using a SC1 solution for 30 minutes, and then using a 200:1 diluted HF solution for 90 seconds. After a cobalt silicide film was formed, a p+/n junction leakage current was measured in a PMOS.
  • [0075]
    As a control sample, the front surface of a substrate having underlying structures was wet-cleaned by using a SC1 solution and then a HF solution and etched by RF sputtering in an Ar gas. Then, a Co film was formed to a thickness of 100 Å by sputtering, and an N-rich, titanium nitride capping film was formed to a thickness of 100 Å at N2 flow rate of 85 sccm. Subsequent processes were carried out in the same manner as those of the above test sample. A p+/n junction leakage current was measured in a PMOS.
  • [0076]
    The measured leakage current is shown in FIG. 12. In FIG. 12, -□—represents the test sample and -∘—represents the control sample. The test sample exhibited an enhanced leakage current and a uniform leakage current distribution.
  • EXPERIMENTAL EXAMPLE 5
  • [0077]
    A Co film was deposited to a thickness of 80 Å on a Si substrate at a high temperature of 400 C. and a transmission electron microphotograph (TEM) of the obtained structure is shown in FIG. 1 3A. As shown in FIG. 1 3A, an interface film with a thickness of 20 to 28 Å was observed between the Co film and the Si substrate.
  • [0078]
    In order to determine the type of the formed interface film, the selected area diffraction (SAD) patterns of the interface film were measured and the results are shown in FIGS. 13B and 13C. It was demonstrated that the interface film formed by the high temperature deposition was made of Co2Si and CoSi.
  • EXPERIMENTAL EXAMPLE 6
  • [0079]
    A Si substrate having underlying structures was treated with a SC1 solution and then a HF solution and then etched by RF sputtering with Ar gas. Then, a Co film was deposited to a thickness of 100 Å at 400 C., and a Ti-rich capping film was deposited to a thickness of 100 Å. Then, a primary RTA was carried out at 450 C. for 90 seconds, the capping film and unreacted Co film were removed using a mixture solution of sulfuric acid and H2O2, and then a secondary RTA was carried out at 800 C. for 30 seconds. As a result, a test sample 1 was prepared.
  • [0080]
    A test sample 2 was prepared in the same manner as in the preparation of the test sample 1 except that the primary RTA was carried out for 30 seconds.
  • [0081]
    A control sample 1 was prepared in the same manner as in the preparation of the test sample 1 except that the Co film was deposited at 150 C.
  • [0082]
    A control sample 2 was prepared in the same manner as in the preparation of the test sample 2 except that the Co film was deposited at 150 C.
  • [0083]
    The Rs values for conductive regions of the test samples 1 and 2 and the control samples 1 and 2 are presented in Table 1 below.
    TABLE 1
    Sheet resistance (Rs) (Ω/sq.)
    N-active region N-gate N-gate P-active region P-gate P-gate
    Sample (CD = 0.26 μm) (CD = 0.13 μm) (CD = 0.65 μm) (CD = 0.26 μm) (CD = 0.13 μm) (CD = 0.65 μm)
    Control sample 1 7.8 6.2 8.0 7.8 6.2 8.0
    Control sample 2 8.2 7.0 8.4 7.8 7.0 8.4
    Test sample 1 8.2 7.8 8.2 8.0 7.8 8.2
    Test sample 2 12.2 9.0 8.7 12.0 9.2 8.6

    CD: critical dimension
  • [0084]
    In the control sample 1, the Rs value of the 0.13 μm gate was smaller than that of the 0.65 μm gate. From this result, it can be seen that as the CD of a gate decreases, the thickness of a cobalt silicide film increases. Therefore, it can be anticipated that this phenomenon will be intensified as the CD of a gate reduces to less than 100 nm.
  • [0085]
    In a comparison between the control samples 1 and 2, a variation in the Rs values according to the CD reduced when the duration of the primary RTA was reduced from 90 seconds to 30 seconds. However, the reduction rate was insignificant.
  • [0086]
    In a comparison between the control sample 1 and the test sample 1, it can be seen that when a Co film is deposited at a high temperature (400 C.) according to the present invention, a variation in the Rs values according to the CD significantly decreases, thereby minimizing the loading of the Rs of a silicide film. This result demonstrates that a cobalt silicide interface film generated by a high temperature deposition serves as a diffusion restraint film.
  • [0087]
    In a comparison between the test samples 1 and 2, when the duration of the primary RTA was reduced from 90 seconds to 30 seconds, the Rs value of the 0.13 μm gate was larger than that of the 0.65 μm gate. This result suggests that even though the CD of a gate is reduced to less than 100 nm, the loading of the Rs of a silicide film can be solved by adjusting a deposition temperature and duration of a RTA. That is, this indicates that a method of forming a cobalt silicide film at a high temperature according to the present invention provides a very large process window.
  • EXPERIMENTAL EXAMPLE 7
  • [0088]
    Leakage current characteristics of the test sample 1 and the control sample 1 prepared in Experimental Example 6 was measured and the results are shown in FIG. 14. In FIG. 14, -□—represents the test sample 1 and -∘—represents the control sample 1. The test sample 1 exhibited substantially enhanced leakage current characteristics, relative to the control sample 1. While a cobalt silicide film was formed to a thickness of 300 to 360 Å in an active region and a STI edge region of the test sample 1, a cobalt silicide film was deeply formed to a thickness of 370 to 700 Å in an active region and a STI edge region of the control sample 1.
  • [0089]
    These facts demonstrate that a cobalt silicide interface film formed upon a high temperature Co deposition efficiently restrains diffusion of Co into a Si-containing conductive region.
  • [0090]
    As apparent from the above description, the present invention provides a method of forming a metal silicide film. According to this method, a capping film is formed in the form of a Ti-rich film and a RF sputter etching that generates impurities can be omitted. Therefore, formation of low quality metal silicide film otherwise caused by impurities at an interface between a metal film and a Si-containing conductive region is prevented. Furthermore, a reaction velocity for formation of a metal silicide film can be adjusted by use of an interface film formed upon the formation of a metal film at a high temperature. Therefore, a small process window for formation of a metal silicide film resulting from the edge effect can be efficiently solved.
  • [0091]
    While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5902129 *Apr 7, 1997May 11, 1999Lsi Logic CorporationProcess for forming improved cobalt silicide layer on integrated circuit structure using two capping layers
US5911114 *Mar 21, 1997Jun 8, 1999National Semiconductor CorporationMethod of simultaneous formation of salicide and local interconnects in an integrated circuit structure
US6171959 *Jan 20, 1998Jan 9, 2001Motorola, Inc.Method for making a semiconductor device
US6303503 *Oct 13, 1999Oct 16, 2001National Semiconductor CorporationProcess for the formation of cobalt salicide layers employing a sputter etch surface preparation step
US6329276 *Sep 9, 1999Dec 11, 2001Samsung Electronics Co. Ltd.Method of forming self-aligned silicide in semiconductor device
US6335294 *Apr 22, 1999Jan 1, 2002International Business Machines CorporationWet cleans for cobalt disilicide processing
US6365516 *Jan 14, 2000Apr 2, 2002Advanced Micro Devices, Inc.Advanced cobalt silicidation with in-situ hydrogen plasma clean
US6391767 *Feb 11, 2000May 21, 2002Advanced Micro Devices, Inc.Dual silicide process to reduce gate resistance
US6410429 *Mar 1, 2001Jun 25, 2002Chartered Semiconductor Manufacturing Inc.Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions
US6440851 *Oct 12, 1999Aug 27, 2002International Business Machines CorporationMethod and structure for controlling the interface roughness of cobalt disilicide
US6444578 *Feb 21, 2001Sep 3, 2002International Business Machines CorporationSelf-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices
US6451693 *Oct 5, 2000Sep 17, 2002Advanced Micro Device, Inc.Double silicide formation in polysicon gate without silicide in source/drain extensions
US6551927 *Jun 15, 2001Apr 22, 2003Taiwan Semiconductor Manufacturing CompanyCoSix process to improve junction leakage
US6657224 *Jun 28, 2001Dec 2, 2003Emagin CorporationOrganic light emitting diode devices using thermostable hole-injection and hole-transport compounds
US6797602 *Feb 11, 2002Sep 28, 2004Advanced Micro Devices, Inc.Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts
US6838363 *Mar 28, 2003Jan 4, 2005Advanced Micro Devices, Inc.Circuit element having a metal silicide region thermally stabilized by a barrier diffusion material
US6936528 *Oct 17, 2003Aug 30, 2005Samsung Electronics Co., Ltd.Method of forming cobalt silicide film and method of manufacturing semiconductor device having cobalt silicide film
US20020022366 *Jul 11, 2001Feb 21, 2002International Business Machines CorporationSelf-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk MOSFETS and for shallow Junctions
US20040157429 *Feb 4, 2004Aug 12, 2004Micron Technology, Inc.Process for forming a diffusion barrier material nitride film
US20050280103 *Aug 25, 2005Dec 22, 2005Amberwave Systems CorporationStrained-semiconductor-on-insulator finFET device structures
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7238611 *Apr 13, 2005Jul 3, 2007United Microelectronics Corp.Salicide process
US7378028 *Jun 3, 2004May 27, 2008Seagate Technology LlcMethod for fabricating patterned magnetic recording media
US7682946Mar 23, 2010Applied Materials, Inc.Apparatus and process for plasma-enhanced atomic layer deposition
US7691442Apr 6, 2010Applied Materials, Inc.Ruthenium or cobalt as an underlayer for tungsten film deposition
US7850779Dec 14, 2010Applied Materisals, Inc.Apparatus and process for plasma-enhanced atomic layer deposition
US7867900Sep 29, 2008Jan 11, 2011Applied Materials, Inc.Aluminum contact integration on cobalt silicide junction
US8110489Apr 11, 2007Feb 7, 2012Applied Materials, Inc.Process for forming cobalt-containing materials
US8187970May 29, 2012Applied Materials, Inc.Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US8563424Apr 26, 2012Oct 22, 2013Applied Materials, Inc.Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US8895415May 31, 2013Nov 25, 2014Novellus Systems, Inc.Tensile stressed doped amorphous silicon
US9028924Nov 7, 2012May 12, 2015Novellus Systems, Inc.In-situ deposition of film stacks
US9032906Oct 16, 2007May 19, 2015Applied Materials, Inc.Apparatus and process for plasma-enhanced atomic layer deposition
US9051641Aug 29, 2008Jun 9, 2015Applied Materials, Inc.Cobalt deposition on barrier surfaces
US9117668May 23, 2012Aug 25, 2015Novellus Systems, Inc.PECVD deposition of smooth silicon films
US9165788 *Apr 5, 2013Oct 20, 2015Novellus Systems, Inc.Post-deposition soft annealing
US9209074May 20, 2015Dec 8, 2015Applied Materials, Inc.Cobalt deposition on barrier surfaces
US9388491Jul 19, 2013Jul 12, 2016Novellus Systems, Inc.Method for deposition of conformal films with catalysis assisted low temperature CVD
US20050271819 *Jun 3, 2004Dec 8, 2005Seagate Technology LlcMethod for fabricating patterned magnetic recording media
US20060079087 *Jan 25, 2005Apr 13, 2006Fujitsu LimitedMethod of producing semiconductor device
US20060234485 *Apr 13, 2005Oct 19, 2006Min-Hsian ChenSalicide process
US20090142474 *Aug 22, 2008Jun 4, 2009Srinivas GandikotaRuthenium as an underlayer for tungsten film deposition
US20090269507 *Apr 29, 2008Oct 29, 2009Sang-Ho YuSelective cobalt deposition on copper surfaces
US20130267081 *Apr 5, 2013Oct 10, 2013Keith FoxPost-deposition soft annealing
Classifications
U.S. Classification438/649, 257/E21.438, 257/E21.199
International ClassificationC23C14/02, C23C14/16, H01L21/336, H01L21/28, C23C14/58
Cooperative ClassificationC23C14/5873, C23C14/021, H01L29/665, C23C14/165, H01L21/28052, C23C14/5806
European ClassificationH01L29/66M6T6F3, C23C14/16B, C23C14/58J, H01L21/28E2B2P3, C23C14/02A, C23C14/58B