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Publication numberUS20050212132 A1
Publication typeApplication
Application numberUS 10/810,436
Publication dateSep 29, 2005
Filing dateMar 25, 2004
Priority dateMar 25, 2004
Also published asUS7534653, US20070085206, US20080185710, US20090218679
Publication number10810436, 810436, US 2005/0212132 A1, US 2005/212132 A1, US 20050212132 A1, US 20050212132A1, US 2005212132 A1, US 2005212132A1, US-A1-20050212132, US-A1-2005212132, US2005/0212132A1, US2005/212132A1, US20050212132 A1, US20050212132A1, US2005212132 A1, US2005212132A1
InventorsMin-Chih Hsuan, Kai-Kuang Ho, Kuo-Ming Chen, Kuang-Hui Tang
Original AssigneeMin-Chih Hsuan, Kai-Kuang Ho, Kuo-Ming Chen, Kuang-Hui Tang
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Chip package and process thereof
US 20050212132 A1
Abstract
The chip package and the process thereof are disclosed. In the chip package, a rigid cover is disposed on the active surface of the chip to protect the active surface of the chip and enhance the structural strength of the chip package. Further, if the material of the rigid cover is a thermal conductive material such as Cu or Al alloy, the heat-spread ability of the chip package can be enhanced. If the rigid cover is made of an electrical conductive material and electrically connected to the ground, the electromagnetic interference (EMI) to the chip package can be reduced. It should be noted that the chip packaging process can form a plurality of the terminal pads on the backside of the chip so that the chip package can be connected to the PCB or substrate via these terminal pads.
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Claims(23)
1. A chip package, comprising:
a chip, having an active surface and a plurality of bond pads, said bond pads being on said active surface; and
a rigid cover, on said active surface, said rigid cover exposing said plurality of bond pads above said active surface.
2. The chip package of claim 1, wherein said chip includes a redistribution layer on said active surface to form said plurality of bond pads.
3. The chip package of claim 1, wherein said rigid cover is adhered to said active surface.
4. The chip package of claim 1, wherein said rigid cover having a periphery adhered to said active surface.
5. The chip package of claim 1, wherein the material of said rigid cover includes a conducting material, an insulating material, or a transparent material.
6. The chip package of claim 1, further comprising a plurality of contacts on said plurality of bond pads respectively, the heights of said contacts relative to said active surface are larger than the height of said rigid cover relative to said active surface.
7. The chip package of claim 1, wherein said plurality of bond pads is disposed on the circumference of said active surface.
8. The chip package of claim 7, wherein said active surface is a rectangle, and said plurality of bond pads are disposed on one side outside of said rectangle.
9. The chip package of claim 7, wherein said chip has a backside relative to said active surface and a plurality of connecting lines, each of said plurality of connecting lines having an end connected to one of said plurality of bond pads, said plurality of connecting lines extending to said backside via a lateral side of said chip and forming a plurality of terminal pads on said backside respectively.
10. The chip package of claim 9, wherein said plurality of terminal pads is disposed on the circumference of said backside.
11. The chip package of claim 9, wherein said plurality of terminal pads is disposed on said backside of said chip as an area array.
12. The chip package of claim 9, wherein said lateral side of said chip includes a concave surface and portions of said connecting lines are on said concave surface respectively.
13. The chip package of claim 9, further comprising a plurality of contacts on said terminal pads respectively.
14. The chip package of claim 1, wherein said plurality of bond pads are disposed on said active surface as an area array, said rigid cover having a plurality of openings to expose said bond pads respectively.
15. A chip packaging process, comprising:
providing a wafer, said wafer having an active surface and a backside corresponding to said active surface, said wafer having a first chip area and a second chip area adjacent to said first chip area, said wafer having a plurality of first and second bond pads on said active surface in said first and second chip areas respectively;
forming a plurality of through holes on said wafer, said plurality of through holes passing through said wafer and connecting said active surface and said backside, said through holes being arranged between said first chip area and said second chip area;
forming a plurality of first and second connecting lines on said wafer, each of said plurality of first connecting lines having a first end through one of said plurality of through holes electrically connected to one of said plurality of first bond pads, each of said plurality of first connecting lines having a second end extending to said backside of said first chip area to form one first terminal pad on said backside of said first chip area, each of said plurality of second connecting lines having a first end through one of said plurality of through holes electrically connected to one of said plurality of second bond pads, each of said plurality of second connecting lines having a second end extending to said backside of said second chip area to form one second terminal pad on said backside of said second chip area, portions of said first connecting lines in said through holes being connected to portions of said second connecting lines in said through holes respectively;
disposing a first rigid cover and a second rigid cover on said active surface of said first chip area and said active surface of said second chip area respectively;
sawing said wafer along an area between said first and second chip areas and sawing said portions of said first connecting lines in said through holes and said portions of said plurality of second connecting lines in said through holes; and
separating said first chip area and said second chip area from said wafer, said first chip area and said first rigid cover being a first chip package, said second chip area and said second rigid cover being a second chip package.
16. The process of claim 15, before said step of separating said first chip area and said second chip area from said wafer, further comprising forming a plurality of contacts on said first and second terminal pads.
17. The process of claim 15, wherein said first rigid cover is adhered to said active surface.
18. The process of claim 15, wherein the periphery of said first rigid cover is adhered to said active surface.
19. The process of claim 15, wherein the material of said first rigid cover includes a conducting material, an insulating material, or a transparent material.
20. The process of claim 15, wherein said plurality of first terminal pads are disposed on the circumference of said backside of said first chip area.
21. The process of claim 15, said plurality of first terminal pads are disposed on said backside of said first chip area as an area array.
22. The process of claim 15, wherein forming said portions of said plurality of first connecting lines in said plurality of through holes are performed by electroplating.
23. The process of claim 15, wherein said first and second rigid covers are structural connected, said step of sawing said wafer further comprising sawing said structural connection of said first and second rigid covers to separate said first and second rigid covers.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention generally relates to a chip package and a process thereof, and more particularly to a chip package having a rigid cover on the active surface of the chip and a process thereof.

2. Description of Related Art

In the semiconductor industry, integrated circuit (IC) manufacturing includes 3 steps—design, process, and packaging. Chips are manufactured by the steps of making wafer, designing the circuit, making the mask, sawing the wafer and so on. Each chip is electrically connected to the external circuit via the bond pads on the chip. Then the insulating material is optionally used to package the chip. The purposes of packaging are to protect the chip from moisture, heat and noise, and to provide the electrical connection between the chip and the external circuit such as printed circuit board (PCB) or other carriers.

As the IC packaging technology advances, the package is getting smaller. Among the IC packaging types, chip scale package (CSP) is one of the package technologies that the length of the package is smaller than 1.2 times of the length of the chip inside the package, or (the chip area/package area) is smaller than 80% while the pitch of the pins of the package is smaller than 1 mm. Based on the material and the structures, CSP includes rigid interposer type, flex interposer type, custom lead frame type, wafer level type and so on.

Unlike the packaging technology for single chip, the wafer level package focuses on packaging wafer in order to simplify the chip packaging process. Hence, after the integrated circuits have been manufactured on the wafer, the whole wafer can be packaged. Then the wafer sawing can be performed to form a plurality of chips from the wafer.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a chip package having a better structural strength, thermal conductive efficiency, and anti-electromagnetic interference ability.

Another object of the present invention is to provide a chip packaging process using wafer level package technology in order to provide a better structural strength, thermal conductive efficiency, and anti-electromagnetic interference ability.

The present invention provides a chip package, comprising: a chip having an active surface and a plurality of bond pads, the bond pads being on the active surface; and a rigid cover on the active surface, the rigid cover exposing the bond pads above the active surface.

In a preferred embodiment, the chip includes a Re-Distribution Layer (RDL) on the active surface to form the bond pads.

In a preferred embodiment, the rigid cover is adhered to the active surface. The rigid cover can have a periphery thereof adhered to the active surface. The rigid cover includes a conducting material, an insulating material, or a transparent material.

In a preferred embodiment, the chip package further comprises a plurality of contacts on the bond pads respectively, and the contacts' heights relative to the active surface are larger than the rigid cover's height relative to the active surface.

In a preferred embodiment, the bond pads can be disposed on the circumference of the active surface. The bond pads are disposed on the active surface as an area array, and the rigid cover has a plurality of openings to expose the bond pads respectively. When the active surface is a rectangle, the bond pads are disposed on a one outside of the rectangle. The chip has a backside relative to the active surface and a plurality of connecting lines, each connecting lines having an end connected to one of the bond pads, the connecting lines extending to the backside via a lateral side of the chip and forming a plurality of terminal pads on the backside respectively.

In a preferred embodiment, the terminal pads are disposed around the circumference of the backside of the chip. The terminal pads can also be disposed on the backside of the chip as an area array. Further, the chip package can comprise a plurality of contacts on the plurality of terminal pads respectively.

The present invention provides a chip packaging process, comprising: providing a wafer, the wafer having an active surface and a backside corresponding to the active surface, the wafer having a first chip area and a second chip area adjacent to the first chip area, the wafer having a plurality of first and second bond pads on the active surface in the first and second chip areas respectively; forming a plurality of through holes on the wafer, the plurality of through holes passing through the wafer and connecting the active surface and the backside, the through holes being arranged between the first chip area and the second chip area; forming a plurality of first and second connecting lines on the wafer, each of the plurality of first connecting lines having a first end through one of the through holes electrically connected to one of first bond pads, each of the first connecting lines having a second end extending to the backside of the first chip area to form one first terminal pad on the backside of the first chip area, each of the second connecting lines having a first end passing through one of the through holes electrically connected to one of second bond pads, each of the second connecting lines having a second end extending to the backside of the second chip area to form one second terminal pad on the backside of the second chip area, a portion of the first connecting lines in the through holes being connected to a portion of the second connecting lines in the through holes respectively; disposing a first rigid cover and a second rigid cover on the active surface of the first chip area and the active surface of the second chip area respectively; sawing the wafer along an area between the first and second chip areas and sawing the portions of the plurality of first connecting lines in the through holes and the portions of the second connecting lines in the through holes respectively; and separating the first chip area and the second chip area from the wafer, the first chip area of the wafer and the first rigid cover being a first chip package, the second chip area of the wafer and the second rigid cover being a second chip package.

In a preferred embodiment, before the step of separating the first chip area and the second chip area from the wafer, the process further comprises forming a plurality of contacts on the first and second terminal pads. The first rigid cover can be adhered to the active surface. The first rigid cover can have a periphery thereof adhered to the active surface. The first rigid cover is made of a conducting material, an insulating material, or a transparent material.

In a preferred embodiment, the first terminal pads can be disposed around the circumference of the backside of the first chip area. The first terminal pads can also be disposed on the backside of the first chip area as an area array. Forming the portions of the plurality of first connecting lines respectively in the plurality of through holes can be performed by electroplating. Besides, the first and second rigid covers are optionally structural connected with each other such that the process of sawing the wafer further comprises sawing the structural connection of the first and second rigid covers to separate the first and second rigid covers.

According to the chip package and the process thereof, a rigid cover is disposed on the active surface of the chip to protect the active surface of the chip and enhance the structural strength of the chip package. Further, if the material of the rigid cover is a thermal conductive material such as Cu or Al alloy, the heat-spread ability of the chip package can be enhanced. If the rigid cover is made of an electrical conductive material and electrically connected to the ground of the chip package, the electromagnetic interference (EMI) to the chip package can be reduced. It should be noted that the chip packaging process could form a plurality of the terminal pads on the backside of the chip so that the chip package can be connected to the PCB or substrate via these terminal pads.

The above is a brief description of some deficiencies in the prior art and advantages of the present invention. Other features, advantages and embodiments of the invention will be apparent to those skilled in the art from the following description, accompanying drawings and appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a top view of the first chip package in accordance with the first embodiment of the present invention.

FIG. 1B is a cross-sectional view of the first chip package of FIG. 1A along I-I′ line.

FIG. 1C is a cross-sectional view of the first chip package of FIG. 1A connected to a printed circuit board.

FIG. 2A is a top view of the second chip package in accordance with the first embodiment of the present invention.

FIG. 2B is a cross-sectional view of the second chip package of FIG. 2A along II-II′ line.

FIG. 2C is a cross-sectional view of the second chip package of FIG. 2A connected to a printed circuit board.

FIGS. 3A-3F show top views of the progression steps of the chip packaging process in accordance with the second embodiment of the present invention.

FIGS. 4A-4F show cross-sectional views of the chip packaging process of FIGS. 3A-3F along III-III′ line.

FIG. 5 is a cross-sectional view of the chip package of FIG. 3F connected to a printed circuit board.

FIG. 6 is a cross-sectional view of another chip package connected to a printed circuit board in accordance with a second embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1A is a top view of the first chip package in accordance with the first embodiment of the present invention. FIG. 1B is a cross-sectional view of the first chip package of FIG. 1A along I-I′ line. Referring to FIGS. 1A and 1B, the chip package 100 includes a chip 110, a rigid cover 120, and an adhesive layer 130. The chip 110 is one of a plurality of unsawed chips of the wafer (not shown). The chip 110 has a rectangular shape having an active surface 112 and a plurality of bond pads 114. The bond pads 114 are disposed on the circumference of the active surface 112. The periphery of the rigid cover 120 is adhered to the active surface 112 via the adhesive layer 130. The bond pads 114 are disposed outside the periphery of the rigid cover 120.

FIG. 1C is a cross-sectional view of the first chip package of FIG. 1A connected to a printed circuit board. Referring to FIGS. 1A, 1B, and IC, a plurality of contacts 116 such as conductive bumps are disposed on the bond pads respectively. The heights of the contacts 116 relative to the active surface 112 are larger than the height of the rigid cover 120 relative to the active surface 112 so that the chip package 100 can be connected to the PCB 140 via the contacts 116. The PCB 140 has a plurality of contact pads 142. The bond pads 114 of the chip package 100 are electrically connected to the contact pads 142 of the PCB 140 via the contacts 116. Further, one can control the heights of the contacts 116 relative to the active surface 112 or the height of the rigid cover 120 relative to the active surface 112 to optionally make the rigid cover 120 contact or not contact the PCB 140. For thermal dissipation or electric characteristic consideration, the cover 120 can be structurally or electrically connected to the PCB 140. In FIGS. 1A-1C, the bond pads 114 are not limited to be disposed around the circumference of the active surface 112. The bond pads can also be disposed on one side or two sides (adjacent or opposite) of the active surface.

FIG. 2A is a top view of the second chip package in accordance with the first embodiment of the present invention. FIG. 2B is a cross-sectional view of the second chip package of FIG. 2A along II-II′ line. Referring to FIGS. 2A and 2B, the chip 210 of the second chip package 200 has a plurality of bond pads 214 disposed as an area array on the active surface 212. The active surface 212 of the chip 210 has a redistribution layer (not shown), which can rearrange the bond pads 214 around the circumference of the active surface 212 with an area array. Further, the rigid cover 220 is adhered to the active surface 212 via the adhesive layer 230. The rigid cover 220 has a plurality of openings 222 corresponding to the bond pads 214 and exposing the bond pads 214.

FIG. 2C is a cross-sectional view of the second chip package of FIG. 2A connected to a printed circuit board. A plurality of contacts 216 is disposed on the bond pads 214 respectively. The heights of the contacts 216 relative to the active surface 212 is larger than the height of the rigid cover 220 relative to the active surface 212 so that the chip package 200 can be connected to the PCB 240 via the contacts 116. The PCB 240 has a plurality of contact pads 242. The bond pads 214 of the chip package 200 are electrically connected to the contact pads 242 of the PCB 240 via the contacts 216.

In the above first and second chip packages, the rigid covers completely cover the wafers. A plurality of contacts such as conductive bumps, is disposed on the bond pads respectively. Then the wafer is sawed to obtain independent chip packages. It should be noted that although the contacts can be formed before sawing the wafer, one may also choose to form the contacts on the contact pads of the PCB. Then the chip package can be connected to the PCB via these contacts.

The second embodiment uses a plurality of connecting lines to extend the bond pads to the backside of the chip and to form the terminal pads on the backside of the chip.

FIGS. 3A-3F show top views of the progression steps of the chip packaging process in accordance with the second embodiment of the present invention. FIGS. 4A-4F show the cross-sectional views of the chip packaging process of FIGS. 3A-3F along III-III′ line. Referring to FIGS. 3A and 4A, a wafer 302 is provided. The wafer 302 has an active surface 312 and a backside 316 corresponding to the active surface 312. The wafer 302 has a first chip area 310 a and a second chip area 310 b adjacent to the first chip area 310 a. The wafer 302 has a plurality of first and second bond pads 314 a and 314 b on the active surface 312 in the first and second chip areas 310 a and 310 b respectively.

Referring to FIGS. 3B and 4B, a plurality of through holes 318 are formed on the wafer 302. The through holes 318 are through the wafer 302 by laser drilling or mechanical drilling and connect the active surface 312 and the backside 316. The through holes 318 are arranged between the first chip area 310 a and the second chip area 310 b.

Referring to FIGS. 3C and 4C, a plurality of first and second connecting lines 322 a and 322 b are formed on the wafer 302 by electroplating. Each of the first connecting lines 322 a has a first end through one of the through holes 318 electrically connected to one of the first bond pads 314 a. Each of the first connecting lines 322 a has a second end extended to the backside 306 of the first chip area 310 a to form one first terminal pad 324 a on the backside 306 of the first chip area 310 a. Each of the second connecting lines 322 b has a first end through one of the through holes 318 electrically connected to one of the second bond pads 314 b. Each of the second connecting lines 322 b has a second end extended to the backside 306 of the second chip area 310 b to form one second terminal pad 324 b on the backside 306 of the second chip area 310 b. It should be noted that because the first and second connecting lines 322 a and 322 b are formed on the wafer 302 by electroplating, portions of the first connecting lines 322 a in the through holes 318 may be connected to portions of the second connecting lines 322 b in the through holes 318 respectively.

Referring to FIGS. 3D and 4D, a first rigid cover 320 a and a second rigid cover 320 b are disposed on the active surface 312 of the first chip area 310 a and the active surface 312 of the second chip area 310 b via the adhesive layers 330 respectively. For thermal dissipation or electric characteristic consideration, the first and second rigid covers 320 a and 320 b can be a conducting material, an insulating material, and a transparent material. Further, the chip packaging process can be a wafer level packaging process. Hence, the first and second rigid covers 320 a and 320 b can be a single structure. That is, the first and second rigid covers 320 a and 320 b can be structurally connected via a connecting bar 320 c or other connecting structures. Therefore, only a single action is required to dispose the first and second rigid covers 320 a and 320 b on the active surface 312.

Referring to FIGS. 3E and 4E, the wafer 302 is sawed along an area between the first and second chip areas 310 a and 310 b by mechanical or laser sawing. The portions of the first connecting lines 322 a in the through holes 318 and the portions of the second connecting lines 322 b in the through holes 318 are also sawed. Hence, the lateral side of the chip 310 has a plurality of concave surfaces 318 a (i.e., a half of the through holes 318). The portions of the first connecting lines 322 a in the through holes 318 and the portions of the second connecting lines 322 b in the through holes 318 are disposed on the concave surfaces 318 a to electrically connect the bond pads 314 and the terminal pads 324. Further, when the first and second rigid covers 320 a and 320 b is a single structure, the connecting bars 320 c will be sawed to separate the first and second rigid covers 320 a and 320 b.

Referring to FIGS. 3F and 4F, the first chip area 310 a and the second chip area 310 b are separated from the wafer 302 by mechanical or laser sawing. Hence, the first chip area 310 a and the first rigid cover 32 a become a first chip package 300 a, the second chip area 310 b and the second rigid cover 320 b become a second chip package 300 b.

FIG. 5 is a cross-sectional view of the chip package of FIG. 3F connected to a printed circuit board. The chip package 300 includes a chip 310, a rigid cover 320, and an adhesive layer 330. The chip 300 has a rectangular shape and an active surface 312 and a plurality of bond pads 314. The bond pads 314 are disposed on the circumference of the active surface 312. A plurality of connecting lines 322 extend the bond pads 314 to the backside 316 of the chip 310 to form a plurality of the terminal pads 324. The terminal pads 324 can be connected to the contact pads 342 of the PCB 340 via a pre-solder, ACP or ACF (not shown).

FIG. 6 is the cross-sectional view of another chip package connected to a printed circuit board in accordance with the second embodiment of the present invention. Compared to FIG. 5, the chip 310 of the second chip package 300 has a plurality of terminal pads 324 disposed as an area array on backside 316 of the chip 310. These terminal pads 324 can be connected to the contact pads 342 of the PCB 340 via the contacts 350 such as conductive bumps.

The second embodiment uses a plurality of connecting lines to extend the bond pads to the backside of the chip and to form the terminal pads on the backside of the chip. Hence, when the chip is connected to the PCB, the active surface of the chip can be exposed. When the rigid cover is a transparent material, the chip package in the second embodiment can be applied in optical-electronic devices such as CMOS image sensor (CIS) and solar cell, or bio-chip.

In brief, the chip package and the process thereof dispose a rigid cover on the active surface of the chip to protect the active surface of the chip and enhance the structural strength of the chip package. Further, if the material of the rigid cover is a thermally conductive material such as Cu or Al alloy, the heat-spread ability of the chip package can be enhanced. If the rigid cover is made of an electrical conductive material and electrically connected to the ground of the chip package, the electromagnetic interference (EMI) to the chip package can be reduced. If the rigid cover is a transparent material, the chip package can be applied in optic-electric or bio devices. In addition, the chip packaging process can form a plurality of the terminal pads on the backside of the chip so that the chip package can be connected to the PCB or substrate via these terminal pads.

The above description provides a full and complete description of the preferred embodiments of the present invention. Various modifications, alternate construction, and equivalent may be made by those skilled in the art without changing the scope or spirit of the invention. Accordingly, the above description and illustrations should not be construed as limiting the scope of the invention which is defined by the following claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7649250 *Nov 14, 2007Jan 19, 2010Samsung Electronics Co., Ltd.Semiconductor package
US7952459Sep 10, 2007May 31, 2011Enpirion, Inc.Micromagnetic device and method of forming the same
US8048708Jun 25, 2008Nov 1, 2011Micron Technology, Inc.Method and apparatus providing an imager module with a permanent carrier
US8339802 *Feb 26, 2009Dec 25, 2012Enpirion, Inc.Module having a stacked magnetic device and semiconductor device and method of forming the same
US8501535Jan 31, 2011Aug 6, 2013Stats Chippac Ltd.Integrated circuit package system with dual side connection and method for manufacturing thereof
US8680634Apr 29, 2011Mar 25, 2014Micron Technology, Inc.Method and apparatus providing an imager module with a permanent carrier
US20130001756 *Sep 13, 2012Jan 3, 2013Cyntec Co., Ltd.Three-dimensional package structure
DE102009036033A1 *Aug 4, 2009Feb 17, 2011Austriamicrosystems AgInterlayer connection for semiconductor wafers, has base wafer with connection pad and cover wafer arranged on base wafer, where cover wafer has continuous opening over connection pad
DE102009036033A8 *Aug 4, 2009Jun 1, 2011Austriamicrosystems AgDurchkontaktierung für Halbleiterwafer und Herstellungsverfahren
DE102009036033B4 *Aug 4, 2009Nov 15, 2012Austriamicrosystems AgDurchkontaktierung für Halbleiterwafer und Herstellungsverfahren
WO2013056936A1Sep 18, 2012Apr 25, 2013Ams AgMethod for producing thin semiconductor components
Classifications
U.S. Classification257/738, 257/E23.02, 257/E23.181, 257/E23.114, 257/E23.061
International ClassificationH01L23/48, H01L23/498, H01L23/552, H01L23/31, H01L23/04, H01L23/485
Cooperative ClassificationH01L23/481, H01L2924/01082, H01L2924/15311, H01L24/02, H01L23/49805, H01L2224/0401, H01L2224/16, H01L23/3114, H01L2924/014, H01L2924/01075, H01L2924/16195, H01L2924/01013, H01L21/481, H01L23/04, H01L2924/16235, H01L27/14618, H01L2924/14, H01L21/4846, H01L23/552, H01L2924/01029, H01L2924/01033
European ClassificationH01L24/02, H01L21/48B3, H01L21/48C4, H01L23/48J, H01L23/498A, H01L23/31H1, H01L23/04, H01L23/552
Legal Events
DateCodeEventDescription
Mar 25, 2004ASAssignment
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSUAN, MIN-CHIH;HO, KAI-KUANG;CHEN, KUO-MING;AND OTHERS;REEL/FRAME:015158/0631
Effective date: 20040312