|Publication number||US20050229132 A1|
|Application number||US 10/810,294|
|Publication date||Oct 13, 2005|
|Filing date||Mar 26, 2004|
|Priority date||Mar 26, 2004|
|Also published as||US7200832|
|Publication number||10810294, 810294, US 2005/0229132 A1, US 2005/229132 A1, US 20050229132 A1, US 20050229132A1, US 2005229132 A1, US 2005229132A1, US-A1-20050229132, US-A1-2005229132, US2005/0229132A1, US2005/229132A1, US20050229132 A1, US20050229132A1, US2005229132 A1, US2005229132A1|
|Inventors||Derrick Butt, Bruce Cochrane, Hui Seto, William Lau, Thomas McCarthy|
|Original Assignee||Lsi Logic Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Referenced by (12), Classifications (4), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to semiconductor integrated circuits and, more particularly, to hard macro cells that can be instantiated in an integrated circuit design for driving a physical layer interface.
Physical layer (PHY) interface devices are used on integrated circuits for communicating with external devices, such as other integrated circuits, typically through a data bus or a set of signal wires. The physical layer device is typically configured to implement a desired communication protocol or specification that has been established for the particular interface. For example, the Peripheral Component Interconnect (PCI) bus specification is an industry standard specification for high-performance input-output (IO) interconnections for transferring data between a CPU and its peripherals. As versions of these standards change over time to achieve greater performance, the demands on the physical layer interface device become more stringent.
Currently, “PCI-X 2.0 bus” is the newest high-speed version of the conventional PCI bus specification, which supports signaling speeds up to 533 mega-transfers per second. For example, the specification can support signaling speeds of 66, 133, 266 and 533 mega-transfers per second.
The timing requirements for a PCI-X 2.0 PHY interface are challenging. The transmitter in the interface uses source-synchronous technology, which transmits the data with a corresponding clock strobe signal to the receiver for compensating for most of the signal propagation delays between the two devices. This interface enables synchronous data transfer between two devices at a single data rate (SDR) or a double data rate (DDR). For SDR transfers, the transmitter transfers data on each successive rising edge of the clock strobe signal. For DDR transfers, the transmitter transfers data on each successive rising and falling edge of the clock strobe signal. DDR transfers therefore transmit two data words per clock cycle.
With these higher transfer speeds, the skew between the data and the clock strobe signal becomes crucial. For example, in the PCI-X 2.0 266 MTS specification the maximum skew between the data and the clock strobe signals at the output pins of the transmitter is 900 picoseconds (ps), whereas the maximum skew at the receiver is 610 ps. In addition, the maximum output delay (transition time) of signals of the transmitter is 3.5 nanoseconds (ns). This output delay must be met at the outputs of the transmitter given the input delays to the transmitter, uncertainties on the input clock signals to the transmitter and propagation delay through the logical paths of the transmitter. Therefore, timing closure for such a physical layer interface can be difficult and time consuming.
In an effort to meet these timing requirements, integrated circuit designers have manually placed the logic components of the physical layer interface close to the IO buffers of the integrated circuit. The designers have also manually routed the IO signals such that they are on the same routing layers as one another and have the same lengths and routing patterns to ensure the signals have minimum skew.
After placement and routing, estimates of the chip-level parasitic capacitances are extracted, and the delay timing is calculated and validated. If the timing requirements are not met, the placement and routing will need to be modified. The validation process is iterated until the timing requirements are met. Therefore, heavy human intervention is used for the manual placement and routing that are involved to meet high performance interface timing requirements, such as those associated with the PCI-X 2.0 specification. This work is non-repetitive since it is unique to each integrated circuit design. This work is thus a time consuming process due to the manual and iterative steps involved.
Improved physical layer interface devices are therefore desired, which simplify the placement and routing of the interface such that timing closure for the interface can be met in an efficient manner.
One embodiment of the present invention is directed to a macro cell for an integrated circuit design having an input-output (IO) region with a plurality of IO buffer cells physically dispersed with other cells in IO slots along an interface portion of the IO region. The macro cell includes a plurality of macro cell IO signal slots that are physically dispersed so as to substantially align with the IO buffer cells in the interface portion. The macro cell also includes an interface definition having a plurality of source-synchronous interface IO signal nets including a multiple-bit data bus and a first clock strobe net. Signals on the data bus have a desired phase alignment with respect to signals on the first clock strobe net. The nets are routed to corresponding ones of the plurality of macro cell signal slots. The macro cell is adapted to be instantiated as a unit in the integrated circuit design.
Another embodiment of the present invention is directed to a macro cell for instantiation in an integrated circuit design. The macro cell includes a physical layer interface definition and a plurality of macro cell IO slots. The physical layer interface definition includes a multiple-bit data bus and a first clock strobe net. Signals on the data bus have a desired phase alignment with respect to signals on the clock strobe net. The macro cell IO slots are electrically coupled to respective bits in the multiple-bit data bus and the first clock strobe net and are physically dispersed from one another in a spacing pattern that is defined for at least one integrated circuit package type. The macro cell is adapted to be instantiated in the integrated circuit design as a unit.
Another embodiment of the present invention is directed to an integrated circuit layout definition, which includes an input-output (IO) region and a macro cell instantiated in the layout definition. The IO region includes an interface portion and a plurality of IO buffer cells physically dispersed with other cells in IO slots along the interface portion. The macro cell includes a plurality of macro cell IO signal slots that are physically dispersed so as to substantially align with corresponding ones of the IO buffer cells in the interface portion, and includes an interface definition having a plurality of source-synchronous interface IO signal nets, which are routed to corresponding ones of the plurality of macro cell signal slots and include a multiple-bit data bus and a clock strobe net. Signals on the data bus have a desired phase alignment with respect to signals on the clock strobe net.
Semiconductor integrated circuits are traditionally designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnect to perform a logical function. For example, with standard cell technology, the schematic diagram or HDL specification is synthesized into standard cells of a specific cell library. Each cell corresponds to a logical function unit, which is implemented by one or more transistors that are optimized for the cell. The cells in the cell library are defined by cell definitions. Each cell library definition includes a cell layout definition and cell characteristics. The cell layout definition includes a predetermined layout pattern for the transistors in the cell, geometry data for the cell's transistors and cell routing data.
These cells can correspond to low-level functions, such as logical “AND”, “OR”, “NOR gates or higher-level functions such as a phase-locked loops, memories or central processing units (CPUs). The higher-level cells are referred to as “macro cells”. A macro cell can include fully custom logic, one or more lower-level cells and/or one or more higher-level cells. A hard macro cell includes a predefined layout pattern of pre-placed logical components within the cell, geometry data for these pre-placed components and routing data for routing the interconnections between the components. A hard macro cell can be selected from a cell library or other database and instantiated as a single unit within the overall layout pattern of a semiconductor integrated circuit design.
In one embodiment of the present invention, a physical layer (PHY) interface device is implemented as a hard macro cell, wherein the internal timing paths are manually constructed and balanced to meet tight signal skew requirements. The PHY interface hard macro cell can be instantiated as a single unit one or more times near the IO buffers or IO region of the integrated circuit to form an PHY interface having any number of bits. This significantly simplifies the routing of signals to and from the IO buffers and eliminates any manual placement or routing within the macro cell by the integrated circuit designer at the time of instantiation.
As described in more detail below, the IO slots of the PHY interface macro cell are physically dispersed to match the IO buffer slot width and pitch of the integrated circuit on which the macro cell is instantiated. This allows substantially straight alignment of IO signals between the macro cell and the IO buffers, which enables simplified routing of the IO signals and their related control signals, between the macro cell and the IO buffers. The IO slot width and pitch can vary depending on technology with which the integrated circuit is fabricated and the type of package in which the integrated circuit is mounted. In one embodiment, the IO slots of the macro cell are physically dispersed to substantially match the slot widths and pad pitches of multiple integrated circuit packages.
PLL 12 generates clock signals for controlling transmit and receive functions within transceiver 16. Controller 14 communicates with macro cells 18 over internal buses 24. Internal buses 24 carry transmit data “Tx DATA” and receive data “Rx DATA” to and from PHY macro cells 18. In one embodiment, each bus 24 has 32 transmit data bits and 32 receive data bits. However, any other number of bits can be used in alternative embodiments. In addition, controller 14 provides frame and control bits (not shown in
PHY macro cells 18 buffer transmit and receive data, generate the appropriate clock strobe signals for transmit operations, and resynchronize received data to a local clock domain. Transmit and receive data is passed between PHY macro cells 18 and interface IO buffers 20 over data buses 30. In one embodiment, each data bus 30 includes a 16-bit transmit data bus, a 16-bit receive data bus and related control signals. Each transmit and receive data word is accompanied by one or more clock strobe signals 32.
In one embodiment, each PHY macro cell 18 is configured to support single data rate (SDR) and double data rate (DDR) transfer operations. To support SDR transfer operations, each PHY macro cell 18 includes a set of registers used to register-out the data signals. For DDR operations, two sets of registers are used to register the data signals, and a double-rated clock is used to multiplex the data signals to interface IO buffers 20. These internal timing paths can be manually constructed and balanced by the designer of the macro cell prior to instantiation within an integrated circuit design to meet tight signal skew requirements.
By implementing each PHY interface block as a macro cell, the integrated circuit designer can simply instantiate one or more of the macro cells in their design without needing to place and route the internal logic components. The slot width and pitch between the IO slots of IO buffers 20 are typically determined by the type of package in which the integrated circuit is mounted. The IO slots within each PHY macro cell 18 are physically dispersed to substantially match the IO slot width and pitch of interface IO buffers 20. This allows substantially straight alignment of the signals routed across buses 30 and 32. Once the PHY macro cells 18 have been instantiated, these signals can be quickly and easily routed to IO buffers 20 with minimal skew between the signals. In one embodiment, the IO slots of each PHY macro cell 18 are physically dispersed to match the pad pitch of a generic ASIC flip-chip package.
The PHY macro cell is not design-specific, but can be reused in other interface designs with the same semiconductor technology. It can also be repeatedly used to implement a wide bus. The PHY macro cell significantly reduces the manual work that is involved during basic implementation and improves design turn-around time. For example, PHY macro cells 18 can be used in a drag-and-drop fashion, and can be seen as “black boxes” in any ASIC design phase.
Transmit section 50 includes backwardly-compatible PCI/PCI-X control block 60, PCI-X 2.0 transmit control block 61, clock distribution block 62, 8-bit data paths 63 and 64 and clock strobe path 65. Clock distribution block 62 receives a PLL clock from PLL circuit 12 (shown in
Receive section 52 includes clock generation block 70, clock distribution block 71, common clock receive control block 72, data capture register block 73, data deserializer block 74 and data resynchronizing block 75. Clock generation block 70 generates receive clock signals based on the clock strobe signals received on input 57 for capturing received data in block 73. Data deserializer 74 de-multiplexes the received data, and resynchronizing circuit 75 resynchronizes the received data to an on-chip clock domain.
Transmit section 50 includes IO driver state control circuit section 90, multiplexing and DDR generation section 91, and strobe generation section 92. IO driver state control section 90 controls the states (enable and termination states) of the transmit and receive IO buffers on a bit-by-bit basis. Inputs 101 are used to enable IO buffers for the 16 transmit bits, 16 receive bits and the corresponding ECC bits in the IO buffer region of the integrated circuit (IO interface buffers 20 in
Input 103 selects between a PCI and a PCI-X mode of operation. Inputs 104 and 105 receive the 32 bits of transmit data and the corresponding eight bits of ECC. Input 106 selects between the SDR and DDR transmit modes. Inputs 107 and 108 are used for resetting the interface. Inputs 109 and 110 are used to control the SDR and the DDR clock strobe generation section 92. Input 111 receives a “1×” frequency clock and input 112 receives a “2×” frequency clock, which has a frequency that is twice the frequency of the 1× frequency clock. Input 113 is used for controlling scan testing of transmit section 50.
Outputs 120 and 122 are coupled to the state control inputs of interface IO buffers 20 (shown in
On the core side of receiver section 52, the receiver section includes a plurality of control inputs 144-151, which are coupled to controller 14, shown in
Receiver section 52 further includes outputs 160-166, which are provided to controller 14 shown in
As mentioned above, the IO slots of the PHY macro cell are physically dispersed to match the IO slot pitch of the IO region of the integrated circuit. The IO slot pitch is often determined by the type of package in which the integrated circuit will be mounted. Also, the type of data bus to which the interface will be connected may have timing, power and other requirements that can effect the spacing and arrangement of the data and clock strobe bits within the IO region. In one embodiment of the present invention, these factors are taken into consideration when arranging the layout of the IO slots in the PHY macro cell such that instantiation of the PHY macro cell will result in substantial alignment of the data and clock strobe bits.
A. Package Types
In one embodiment of the present invention, the IO slots of the PHY macro cell are physically dispersed to match the IO pad pitch of three different types of integrated circuit packages, which are commercially available from LSI Logic Corporation of Milpitas, Calif. These packages include:
1. High Performance Enhanced Plastic Ball Grid Array (HP-EPBGA) Package;
2. Four Layer Flip Chip Plastic Ball Grid Array (FPBGA-4L); and
3. Six Layer High Performance Flip Chip Plastic Ball Grid Array (FPBGA-HP).
However, the PHY macro cell can be arranged to match the pad pitch of any other integrated circuit package type. The HP-EPBGA has an IO slot width (pad pitch) of 50.02 um, the FPBGA-4L has an IO slot width of 56.7 um, and the FPBGA-HP has an IO slot width of 50.4 um. In one embodiment, the PHY macro cell is optimized for an IO slot width of 50.4 um, which aligns with the FPBGA-HP package. Although with this spacing, the IO slots of the PHY macro cell will not align exactly with the 50.02 um slot width of the HP-EPBGA package or the 56.7 um slot width of the FPBGA-4L flip chip package. However, the pin outs are sufficiently aligned so as to allow for minimal routing complexity between the PHY macro cell and the IO buffers of the package.
Examples of the slots alignments for each of these package types are shown in more detail below with reference to
B. Performance Criteria
For each of these package types, the IO region of the integrated circuit is arranged to satisfy certain performance criteria for the desired bus, such as the bus described in the PCI-X 2.0 specification, for example. The sections below discuss some of these performance criteria for the different package types and illustrate how these criteria affect the spacing of data bus bits in the IO region.
C. Decoupling Capacitance
Every IO bit should have an adequate decoupling capacitance from the various power supply buses to ground. In one example, the integrated circuit has three power supply buses within the IO region, which can be named VDDIO1533PCIX2, VDDIO33PCIX2, and VREF15. The VDDIO1533PCIX2 power supply bus can be biased at either 1.5 volts or 3.3 volts, for example. The VDDIO33PCIX2 power supply bus is biased at 3.3 volts, for example. The VREF15 power supply bus is biased at a 1.5 volt reference voltage, for example.
In order to provide sufficient power supply decoupling capacitances, decoupling capacitance (DCAP) cells are placed in selected IO slots within the IO region (IO interface buffers 20 in
The same DCAP cell is used for filling IO slots in each of the package types. In one embodiment, the width of the DCAP cell is the same as a PCI-X 2.0 IO slot width of 50.02 um. The number of DCAP cells varies depending on the package used.
The following summarizes the ratio of DCAP cells to IO bits in the data section only with respect to the PHY macro cell for the three package types:
In addition, any unused IO slots in the IO region can be filed with DCAP cells. Again, these values are provided as examples only.
D. Power Cuts
A power cut is a conductive segment coupled to or forming part of a power supply rail. In one embodiment of the present invention a power cut is routed between the control section and the data section of the IO interface buffers for a 32-bit and a 64-bit PCI-X 2.0 interface. However, a power cut is not routed between adjacent PHY macro cells for a 64-bit interface.
E. Electro Static Discharge Protection
For the HP-EPBGA and the FPBGA-4L IO interface buffers, a single custom ESD protection cell (labeled “DVDD” in
In one embodiment, the placement requirements for the ESD DVDD cells are summarized as follows:
1. A spacing of less than or equal to [16*Weff] is desired between two neighboring DVDD cells, wherein Weff is the slot width of the IO buffers for the particular package.
To provide adequate ESD protection and sufficient ESD margin, a Weff of 50.02 um will be assumed for the placement requirements defined above. However, the placement requirement defined in (4) shown above will assume Weff is 61.58 um. The following table summarizes the placement preferences in terms of [Weff].
TABLE 1 Maximum # of IO Slots for Spacing Requirement HP 6Layer Spacing HP- 4 Layer FC FC Rqmt EPBGA (Slot 9 mil (Slot 8 mil (Slot Weff = Width = Width = Width = Requirement 50.02 um) 50.02 um) 56.7 um 50.4 um) #1 800.32 um 15 13 14 #2 400.16 um 7 6 7 #3 330 um 6 5 6 #4 958.28 um 18 16 18 Weff = 61.58 um
F. Example of Power Requirements
The following section summarizes examples of power requirements for the DATA and CONTROL sections of the PCI-X 2.0 Interface IO buffers. The term “Power Pins” assumes that power is supplied by the respective Power Supply Rail that is routed along the buffers in the IO region, while “Power Cell” refers to an IO slot that receives power routed through signal connections.
F.1 Data Section Power
F.2 Control Section
(with Package Plane)
The VDDIO33PCIX2 supply is powered on-chip through signal pins. The VDDIO33PCIX2 and VDDIO1533PCIX2 power rings are shorted together within a special PCIX2VDDIO1533 Power Cell designed for the Control Section.
(with no Package Plane)
F.2 BZ (High Impedance) Control Section
(with Package Plane)
(with no Package Plane
For the HP-EPBGA package, the IO region of the integrated circuit has an IO slot width of 50.02 um in one embodiment of the present invention. Decoupling capacitor cells are placed within the IO buffer ring to provide the most efficient decoupling of the IO signals. Each DCAP cell utilizes a 50.02 um slot width within the buffer ring and provides effectively 115 pF of decoupling capacitance per cell. For the PCI-X 2.0 interface used in this example, the 3-pad row implementation of the HP-EPBGA package is used.
Tables 2 and 3 summarize an example of the number of slots used and the total IO slot width for the following cases: a single PHY macro cell (16-bit interface), a pair of PHY macro cells (32-bit interface)and four PHY macro cells (a 64-bit interface).
TABLE 2 Number of IO Slots (Width = 50.02 um) Hard Macro HP-EPBGA (3PAD ROW) 16 Bits 32 Bit Bus 64 Bit Bus Signals (includes data, 22 44 88 ECC, mode select, address and STROBE) A/D DECAPS 18 40 80 ESD 3 12 20 A/D 3.3 V Bias 2 6 12 A/D VREF15 1 2 4 Control/Frame x 13 13 Control/Frame 3.3 V x 6 6 Bias C/F DECAPS x 9 9 B/Z Reference x 7 7 Total [um] 46 139 239 TABLE 3
Total PCI-X 2.0 Interface
HP-EPBGA (3 Pad Row)
32 Bit Bus
64 Bit Bus
data ECC, mode
select, address and
A/D & Control/Frame
3.3 V Bias
Control/Frame 3.3 V
PHY macro cell has a plurality of IO slots 501 arranged in a column. Similarly, IO region 500 has a plurality of IO slots 502, which are also arranged in a column and are dedicated for PHY macro cell 18. PHY macro cell 18 is placed near IO slots 502 such that slots 501 substantially align with IO slots 502.
The width of each IO slot 501 in PHY macro cell 18 is 50.4 um, as shown by arrow 504, according to one embodiment of the present invention. Unused IO slots are cross-hatched, and used IO slots are labeled generically as “BIT #0” to “BIT #21”. The IO slots labeled BIT #0 to BIT #9 are used for locating contact pins for the least significant eight bits of data and two corresponding bits of ECC that are transmitted to or received from corresponding slots 502 in IO region 500. Each IO slot defines the contact pin locations for all signals associated with one bit of data. For example, the IO slot labeled BIT #0 defines the contact pin locations for the least significant transmit data bit (122 in
Similarly, the IO slots labeled BIT #12 to BIT #21 are used for locating contact pins for the most significant eight bits of data and two corresponding bits of ECC that are transmitted to or received from corresponding slots 502 in IO region 500. The label “AD[x8]” refers to 8 bits of address and data, and the labels “Cat1_Sig”, “Cat1_Sig”, “Cat1_Sig”, and “Cat1_Sig” refer to ECC bits.
The IO slots labeled BIT #12 to BIT #21 are used for locating contact pins for the two clock strobe signals and their corresponding enable signals. The labels “C/BE[A]#” and “C/BE[A]#” refer to the two clock strobe signals and their enables (such as clock strobe output 123, the corresponding enable and termination control bits 121 and the received clock strobe input 141 (shown in
Since IO region 500 is designed for an HP-EPBGA package, each IO slot 502 has a slot width of 50.02 um, for example, as shown by arrow 520. A variety of different types of cells are placed in IO slots 502. These types are identified in legend 521.
A first set the IO slots 502 are used for placing IO buffer cells 522 for buffering transmit and/or receive signals transferred over the interface bus 22 (shown in
Another set of the IO slots 502 is used for placing power supply decoupling capacitance cells 524. The decoupling capacitor cells 524 are coupled between corresponding power supply rails on the integrated circuit and the ground rail for reducing fluctuations in the power supply voltages caused by device switching in the interface buffer region. The decoupling capacitance cells are physically dispersed among the IO buffer cells 522 at a spacing that is selected for the particular technology in which the integrated circuit is fabricated and the package on which the integrated circuit is mounted, as discussed above.
Another set of IO slots 502 is used for placing electrostatic discharge (ESD) protection cells 526 (labeled DVDD). The ESD cells 526 are also physically dispersed among the IO buffer cells 522 according to the spacing discussed above, for example.
Another set of IO slots 502 is used for placing power cells 528. In one example, power cells 528 are used for receiving a 3.3 volt IO power supply voltage and driving corresponding power supply rails on the integrated circuit. However, any other voltage level can be used. A further set of IO slots 502 is used for placing a reference voltage input cell 530 (labeled VREF15) for receiving an input reference voltage of 1.5 volts, for example.
As discussed above, the decoupling capacitance cells 524, ESD protection cells 526, power cells 528 and voltage reference cells 530 are dispersed among the IO buffer cells 522. This causes the IO buffer cells 522 to be physically dispersed along the interface portion of the IO region 500. In other words, not all of the IO buffer cells 522 for a given data bus are located adjacent to one another within IO region 500.
The corresponding IO slots in macro cell 18 are physically dispersed within macro cell 18 to align substantially with the IO buffer cells 522 in IO region 500. This significantly simplifies the routing of signals (shown by arrow 540) on the integrated circuit between macro cell 18 and the IO buffers 522. Macro cell 18 can therefore be placed near IO region 500 and instantiated repeatedly to create a bus of any suitable width without causing difficulties in routing or unsatisfactory skew between signals in the interface. Skew between the data signals and clock strobe signals can be more tightly controlled. This significantly reduces the manual work that is involved during integrated circuit design and implementation and improves design turn-around-time.
For a 32-bit PCI-X 2.0 interface, two PHY macro cells 18 are used, which are labeled HARDMACRO#0 and HARDMACRO#l. PHY macro cells 18 are separated by power supply rails 600. In addition, a set of interface control signals, high impedance reference cells and ESD cells 602 and 604 are placed between the PHY macro cells 18.
H. IO Slot Alignment for the FPBGA-4L Package
For the FPBGA-4L package, the IO region of the integrated circuit has an IO slot width of 56.7 um.
Again, decoupling capacitor cells are placed within the IO region to provide decoupling of the IO signals from fluctuations in the power supply rails. Each decoupling capacitance cell consumes a slot width 50.02 um and provides effectively 115 pF of decoupling capacitance per cell.
Tables 4 and 5 summarize the number of slots and total width for the cases of a single PHY macro cell (16-bit PCI-X 2.0 interface), twp PHY macro cells (a 32-bit PCI-X 2.0 interface), and four PHY macro cells (a 64-bit PCI-X 2.0 interface).
TABLE 4 Number of I/O Slots (Width = 56.7 um) 4-Layer Flip Hard Chip (9 mil) Macro 32 Bit Bus 64 Bit Bus Signals (includes 22 44 88 data, ECC, mode select, address and STROBE A/D DECAPS 13 32 64 ESD 3 12 20 A/D 3.3 V Bias 2 6 12 A/D VREF15 1 2 4 Control/Frame x 13 13 Control/Frame x 6 6 3.3 V Bias C/F DECAPS x 9 9 BZ Reference x 7 7 Total [um] 41 131 223 TABLE 5
Total PCI-X 2.0
Interface Width (um)
4-Layer Flip Chip (9 mil)
32 Bit Bus
64 Bit Bus
data, ECC, mode
select, address and
A/D & Control/Frame
3.3 V Bias
Control/Frame 3.3 V
Again, the above values and signals are provided as examples only.
In this example, IO slots 502 have a width 700 of 56.7 um. Although slot width 700 is greater than that of the slot width 504 in PHY macro cell 18, the 22 bits of signal slots in PHY macro cell 18 substantially align with the corresponding IO buffer cells in IO slots 522, as shown by arrows 706. Again, the IO buffer cells 522 are physically dispersed in region 500 to satisfy a particular set of design rules. The corresponding signal slots in macro cell 18 are also physically dispersed to substantiality align with the physical disbursement in IO region 500.
Since the IO buffer cells 522 for the PCI-X 2.0 interface consume only 50.02 um, as shown by arrow 702, the remaining area 704 can be used for decoupling capacitances. Additional decoupling capacitance cells can be placed in these areas.
I. IO Slot Alignment for the FPBGA-HP
The slot width in the IO region for the 8 mil, 6-layer high performance flip chip package is 50.4 um. Again, decoupling capacitor cells are placed in selected IO slots to provide capacitive decoupling of the IO signals. Each decoupling capacitor cell has a width of 50.02 um and provides effectively 115 pF of decoupling capacitance. The following tables summarize the number of slots and the total width for the cases of a single PHY macro cell (16-bit PCI-X 2.0 interface), twp PHY macro cells (a 32-bit PCI-X 2.0 interface), and four PHY macro cells (a 64-bit PCI-X 2.0 interface).
TABLE 6 Number of I/O Slots (Width = 50.4 um) 6 Layer HP Flip-Chip (8 mil) Hard Macro 32 Bit Bus 64 Bit Bus Signals (includes data, 22 44 88 ECC, mode select, address and STROBE) A/D DECAPS 17 40 80 ESD 3 12 20 A/D 3.3 V Bias 2 6 12 A/D VREF15 1 2 4 Control/Frame x 13 13 Control/Frame 3.3 V Bias x 6 6 C/F DECAPS x 9 9 BZ Reference x 7 7 Total [um] 45 139 239 TABLE 7
Interface Width (um)
6 Layer HP Flip-Chip (8 mil)
32 Bit Bus
64 Bit Bus
data, ECC, mode
select, address and
A/D & Control/Frame
3.3 V Bias
Control/Frame 3.3 V
As shown by arrows 900 and 902, the decoupling capacitor cells and the IO buffers cells use only 50.02 um of the 50.4 um slot width.
J. PHY Macro Cell IO Slot Contact Layout
Slot 501-1 illustrates the layout of each “data” slot (address, data and ECC). Slot 501-1 can correspond to one of the slots labeled BITS #0-#9 and BITS #12-#21 in
In one embodiment, each instance of the transmit data section and the receive data section in PHY macro cell 18 has identical placement and routing, excluding scan chains. Pins 1101-1105 in slot 501-1 are electrically coupled to the corresponding IO signal nets shown in
IO slot 501-2 corresponds to the first clock strobe signal (labeled BIT #10 in
Similarly, IO slot 501-4 corresponds to the second clock strobe signal and includes a clock strobe transmit section “SSTROBE” and a clock strobe receive section “RX_CONTROL” having pins 1111-1115. In one embodiment, IO slots 501-2 and 501-4 have identical placement and routing to one another, excluding any scan chains. Also, the placement and routing can match the placement and routing in the data I/O slots, such as slot 501-1.
Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. For example, the present invention can be used with any interface or bus, and is not limited to PCI-type buses. The specific slot widths and IO signals are also provided as examples only. The terms “input-output” or “IO” can refer to bi-directional input-output signals or pins, unidirectional input signals or pins, or unidirectional output signals or pins, for example.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5036473 *||Oct 4, 1989||Jul 30, 1991||Mentor Graphics Corporation||Method of using electronically reconfigurable logic circuits|
|US6449760 *||Nov 30, 2000||Sep 10, 2002||Lsi Logic Corporation||Pin placement method for integrated circuits|
|US6734046 *||Oct 3, 2002||May 11, 2004||Reshape, Inc.||Method of customizing and using maps in generating the padring layout design|
|US6763028 *||Jan 10, 2001||Jul 13, 2004||Fujitsu Limited||Transceiver apparatus|
|US6823501 *||Oct 3, 2002||Nov 23, 2004||Reshape, Inc.||Method of generating the padring layout design using automation|
|US6894530 *||Apr 28, 2003||May 17, 2005||Lattice Semiconductor Corporation||Programmable and fixed logic circuitry for high-speed interfaces|
|US6903575 *||Apr 28, 2003||Jun 7, 2005||Lattice Semiconductor Corporation||Scalable device architecture for high-speed interfaces|
|US6941536 *||Sep 6, 2001||Sep 6, 2005||Hitachi, Ltd.||Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip|
|US6970966 *||Mar 7, 2002||Nov 29, 2005||Italtel S.P.A.||System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol|
|US20030236939 *||May 16, 2003||Dec 25, 2003||Bendik Kleveland||High-speed chip-to-chip communication interface|
|US20050097493 *||Oct 29, 2003||May 5, 2005||Lsi Logic Corporation||Gate reuse methodology for diffused cell-based IP blocks in platform-based silicon products|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7231625 *||Sep 28, 2004||Jun 12, 2007||Lsi Corporation||Method and apparatus for use of hidden decoupling capacitors in an integrated circuit design|
|US7269679 *||Jun 14, 2005||Sep 11, 2007||Advanced Micro Devices, Inc.||PCI-X error correcting code (ECC) pin sharing configuration|
|US7379837 *||Jul 21, 2006||May 27, 2008||Qlogic, Corporation||Method and system for testing integrated circuits|
|US7669086||Aug 2, 2006||Feb 23, 2010||International Business Machines Corporation||Systems and methods for providing collision detection in a memory system|
|US7685392||Nov 28, 2005||Mar 23, 2010||International Business Machines Corporation||Providing indeterminate read data latency in a memory system|
|US7721140||Jan 2, 2007||May 18, 2010||International Business Machines Corporation||Systems and methods for improving serviceability of a memory system|
|US7729153||Apr 2, 2008||Jun 1, 2010||International Business Machines Corporation||276-pin buffered memory module with enhanced fault tolerance|
|US7765368||Jul 5, 2007||Jul 27, 2010||International Business Machines Corporation||System, method and storage medium for providing a serialized memory interface with a bus repeater|
|US7870459||Oct 23, 2006||Jan 11, 2011||International Business Machines Corporation||High density high reliability memory module with power gating and a fault tolerant address and command bus|
|US7979821 *||May 9, 2008||Jul 12, 2011||Renesas Electronics Corporation||Method of verifying semiconductor integrated circuit and design program|
|US8139697 *||Jan 29, 2008||Mar 20, 2012||United Microelectronics Corp.||Sampling method and data recovery circuit using the same|
|US20090190703 *||Jul 30, 2009||United Microelectronics Corp.||Sampling method and data recovery circuit using the same|
|Jul 23, 2004||AS||Assignment|
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