US 20050230263 A1
A method of forming a copper interconnect, comprising forming an opening in a dielectric layer disposed on a substrate, forming a barrier layer over the opening, forming a seed layer over the metal layer, and forming a copper-noble metal alloy layer by electroplating and/or electroless deposition on the seed layer. The copper-noble metal alloy improves the electrical characteristics and reliability of the copper interconnect.
24. A copper interconnect, comprising:
a dielectric layer having an opening;
a barrier layer on the opening; and
a copper alloy layer on the barrier layer wherein the copper alloy layer substantially comprises copper and a noble metal.
25. The method of
26. The copper interconnect of
27. The copper interconnect of
28. The copper interconnect of
29. The copper interconnect of
The present invention relates to the field of microelectronic device processing, and more particularly to a method of forming a copper interconnect structure utilizing electroplating and/or electroless techniques and structures formed thereby.
Transistors, as is well known in the art, are the building blocks of all integrated circuits. Modern integrated circuits interconnect literally millions of densely configured transistors that perform a wide variety of functions. To achieve such a dramatic increase in the density of circuit components has required microelectronic manufacturers to scale down the physical dimensions of the circuit elements, as well as to utilize multiple levels of interconnection structures used to connect the circuit elements into functional circuitry.
One such interconnection process is known as the damascene process (
The utilization of copper metal in a damascene structure has many advantages, for example its lower electrical resistance as compared with previously used metals, such as aluminum. One technique for depositing copper in a damascene structure is by electroless deposition, which is attractive because of its lower cost and high quality of deposition. In electroless plating, metal deposition occurs by a chemical reduction reaction in an aqueous solution which contains a reducing agent, wherein no external power supply is needed. However, electroless deposition requires the activation of a nonconductive surface, for example by providing a seed layer, in order to electrolessly deposit the metal.
However, there are problems associated with the use of copper as an interconnect metal in a damascene structure. One such problem is that copper diffuses or drifts easily into the dielectric layers 202, 202′ (referring again to
Another problem associated with copper metallization is that copper is readily oxidized, especially during subsequent processing steps. The oxidized copper degrades the electrical and mechanical properties of the copper interconnect. Accordingly, an hermetic encapsulating layer is generally employed in order to provide corrosion resistance for the copper layer, such encapsulating materials may include silicon carbide (SiC) and silicon nitride (SiN). This encapsulating layer may also serve as an etch stop, which prevents over-etching of the copper layer during subsequent processing steps. However, this encapsulating layer can also increase the effective dielectric constant of the copper interconnect structure.
Yet another problem encountered with copper metallization is the electromigration of copper atoms at high current densities, which can result in voids in the metal interconnect structure. One method of reducing the amount of electromigration is to alloy the copper metal with aluminum, tin, indium or silicon; however, this may increase the copper resistance significantly.
Accordingly, there is a need for an improved copper interconnect fabrication process and structure that increases copper corrosion resistance and/or oxidation resistance, increases electromigration resistance, and/or decreases the effective dielectric constant of the copper interconnect structure.
While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
A method for making a copper interconnect structure is described. That method comprises forming an opening in a dielectric layer disposed on a substrate, forming a barrier layer over the opening, forming a seed layer over the metal layer, and forming a copper-noble metal alloy layer by electroplating and/or electroless deposition on the seed layer, wherein the copper-noble metal alloy layer improves the electrical characteristics and reliability of the copper interconnect structure. Either an etch stop layer or a cladding layer may then be formed on the copper alloy layer.
In an embodiment of the method of the present invention, as illustrated by
The dielectric layer 104 is formed on the substrate 102. Those skilled in the art will appreciate that the dielectric layer 104 may also be formed from a variety of materials, thicknesses or multiple layers of material. By way of illustration and not limitation, the dielectric layer 104 may include silicon dioxide (preferred), organic materials or inorganic materials. Although a few examples of materials that may be used to form the dielectric layer 104 are described here, that layer may be made from other materials that serve to separate and insulate the different metal layers.
The dielectric layer 104 may be formed on the substrate 102 using a conventional deposition method, e.g., a chemical vapor deposition (“CVD”), a low pressure CVD (“LPCVD”), a physical vapor deposition (“PVD”), or an atomic layer deposition (“ALD”). Preferably, a CVD process is used. In such a process, a metal oxide precursor (e.g., a metal chloride) and steam may be fed at selected flow rates into a CVD reactor, which is then operated at a selected temperature and pressure to generate an atomically smooth interface between the substrate 102 and the dielectric layer 104. The CVD reactor should be operated long enough to form the dielectric layer 104 with the desired thickness. In most applications, the dielectric layer 104 is about one micron thick, and more preferably between about 6,000 angstroms and about 8,000 angstroms thick.
The dielectric layer 104 may have at least one opening 105 formed in it (
Following the formation of the opening 105, a barrier layer 108 is deposited onto the opening 105 (
A seed layer 110 may then be optionally formed on the barrier layer 108 (
In a preferred embodiment, the copper deposition process may be performed using a conventional copper electroplating process, which is well known in the art, in which a single or dual damascene structure is filled with copper by using a direct current (DC) electroplating process (see
In a currently preferred embodiment, the electroplating solution may comprise copper ions, sulfuric acid, chloride ions, additives (such as suppressors i.e. polyethylene glycol, and anti-supressors i.e. di-sulfide), noble metal ions, noble metals and complexing agents (such as thiosulfate and peroxodisulfate). Although a few examples of materials that may comprise the electroplating solution are described here, that solution may comprise other materials that serve to deposit noble metal alloys of copper onto a surface, such as the barrier layer 108 or the seed layer 110 (
Alternatively, the deposition of copper may be performed using an electroless deposition process, which includes any autocatalytic (i.e. no external power supply is applied) deposition of a film through the interaction of a metal salt and a chemical reducing agent. First, as is known in the art, preparing or treating a surface, such as the barrier layer 108, is necessary in order to produce an activated surface, i.e. a surface that is susceptible to the electroless deposition process. Methods for providing the activation of a surface for electroless deposition may include contact displacement, in which the surface is dipped or sprayed with a copper containing contact displacement solution, or the utilization of a seed layer, such as the seed layer 110. During the electroless deposition, the seed layer 110 (see
Next, after the activated surface (the seed layer 110 in the current embodiment of the present invention) for electroless deposition has been provided, the activated surface is exposed to the electroless deposition solution, by methods including immersing the activated surface in an electroless deposition solution or spraying the electroless deposition solution onto the activated surface. Finally, a metal, such as the copper alloy layer 112 of the present invention (see
The copper alloy layer 112 may comprise the following alloys: copper silver, copper palladium, copper platinum, copper rhodium, copper ruthenium, copper gold, copper iridium and copper osmium. The percentage of noble metal in the alloy is about four percent atomic weight, most preferably between about 0.1 and 4 percent atomic weight. The incorporation of the noble metals in the copper alloy layer 112 increases copper corrosion resistance since the copper alloy layer 112 is less prone to oxidize than pure copper due to the un-reactive nature of the noble metal. The copper alloy layer 112 is also more electromigration resistant than pure copper because the low solubility of the noble metals facilitates the stuffing of the grain boundaries of the copper alloy layer 112 by the noble metals, as well as stuffing the interfaces the copper layer 112 makes with the barrier layer 108 and an etch stop layer 114 (which may be deposited in a later step, see
It is to be appreciated that multiple layers of metallization may be deposited on top of the copper interconnect structure 113, according to the method of the present invention, as shown in
In another embodiment, cladding layers 116, 116′ can be electrolessly deposited over the copper alloy layers 112, 112′ instead of the etch stop layers 114, 114′ (
As described above, the use of an electrolessly deposited noble metal-copper alloy metallization structure increases copper corrosion resistance and oxidation resistance, increases electromigration resistance, and decreases the effective dielectric constant of the copper interconnect structure. Thus the reliability and speed of the microelectronic device are greatly enhanced. It is understood that the present invention includes both single and dual damascene structures, as well as multilevel metallization structures.
Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims. In addition, it is appreciated that the fabrication of a multiple metal layer structure atop a substrate, such as a silicon substrate, to manufacture a silicon device is well known in the art. Therefore, it is appreciated that the Figures provided herein illustrate only portions of an exemplary microelectronic device that pertains to the practice of the present invention. Thus the present invention is not limited to the structures described herein.