US 20050242423 A1
The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.
21. A high-density circuit module comprising:
a first CSP having a planar surface rising from which are contacts, the contacts rising from the planar surface by a height D1;
a second CSP disposed above the first CSP in stacked disposition;
a first form standard disposed, in substantial part, above the first CSP;
flex circuitry connecting the first and second CSPs;
at least one metallic bond attaching the flex circuitry and the first form standard; and
module contacts, the module contacts extending from the flex circuit by a height Dm, where Dm is greater than D1.
22. The high-density circuit module of
23. The high-density circuit module of
24. The high-density circuit module of
25. The high-density circuit module of
26. A high-density circuit module comprising:
a first CSP;
a second CSP stacked above the first CSP;
a first form standard associated with the first CSP;
a second form standard associated with the second CSP; and
flex circuitry connecting the first and second CSPs, the flex circuitry being attached to the first form standard and comprising at least two conductive layers.
27. The high-density circuit module of
28. The high-density module of
29. The high-density module of
30. The high-density module of
This application is a continuation-in-part of U.S. patent application Ser. No. 10/453,398, filed Jun. 3, 2003, which is a continuation-in-part of U.S. patent application Ser. No. 10/005,581, filed Oct. 26, 2001, now U.S. Pat. No. 6,576,992 and a continuation-in-part of PCT App. No. PCT/US03/29000, filed Sep. 15, 2003.
U.S. patent application Ser. No. 10/453,398, filed Jun. 3, 2003, is hereby incorporated by reference.
PCT Pat. App. No. PCT/US03/29000, filed Sep. 15, 2003, is hereby incorporated by reference.
The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits in chip-scale packages.
A variety of techniques are used to stack packaged integrated circuits. Some methods require special packages, while other techniques stack conventional packages.
The predominant package configuration employed during the past decade has encapsulated an integrated circuit (IC) in a plastic surround typically having a rectangular configuration. The enveloped integrated circuit is connected to the application environment through leads emergent from the edge periphery of the plastic encapsulation. Such “leaded packages” have been the constituent elements most commonly employed by techniques for stacking packaged integrated circuits.
Leaded packages play an important role in electronics, but efforts to miniaturize electronic components and assemblies have driven development of technologies that preserve circuit board surface area. Because leaded packages have leads emergent from peripheral sides of the package, leaded packages occupy more than a minimal amount of circuit board surface area. Consequently, alternatives to leaded packages known as chip scale packaging or “CSP” have recently gained market share.
CSP refers generally to packages that provide connection to an integrated circuit through a set of contacts (often embodied as “bumps” or “balls”) arrayed across a major surface of the package. Instead of leads emergent from a peripheral side of the package, contacts are placed on a major surface and typically emerge from the planar bottom surface of the package. The absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking.
A variety of previous techniques for stacking CSPs typically present complex structural arrangements and thermal or high frequency performance issues. For example, thermal performance is a characteristic of importance in CSP stacks.
What is needed, therefore, is a technique and system for stacking CSPs that provides a thermally efficient, reliable structure that performs well at higher frequencies but does not add excessive height to the stack yet allows production at reasonable cost with readily understood and managed materials and methods.
The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. Although the present invention is applied most frequently to chip scale packages that contain one die, it may be employed with chip scale packages that include more than one integrated circuit die. Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers.
In the present invention, at least one form standard is employed to provide a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material, a metal, for example, such as copper would be preferred, to improve thermal performance.
In constructing modules in accordance with some preferred modes of the invention, CSP contacts are reduced in height to create lower profile modules. With some of the preferred methods of the present invention, the compressed contacts mix with solder paste and set beneficially as lower diameter contacts. This creates low profile embodiments of the modules of the present invention.
The term CSP should be broadly considered in the context of this application. Collectively, these will be known herein as chip scale packaged integrated circuits (CSPs) and preferred embodiments will be described in terms of CSPs, but the particular configurations used in the explanatory figures are not, however, to be construed as limiting. For example, the elevation views are depicted with CSPs of a particular profile known to those in the art, but it should be understood that the figures are exemplary only. The invention may be employed to advantage in the wide range of CSP configurations available in the art where an array of connective elements is available from at least one major surface. The invention is advantageously employed with CSPs that contain memory circuits, but may be employed to advantage with logic and computing circuits where added capacity without commensurate PWB or other board surface area consumption is desired.
Typical CSPs, such as, for example, ball-grid-array (“BGA”), micro-ball-grid array, and fine-pitch ball grid array (“FBGA”) packages have an array of connective contacts embodied, for example, as leads, bumps, solder balls, or balls that extend from lower surface 22 of a plastic casing in any of several patterns and pitches. An external portion of the connective contacts is often finished with a ball of solder. Shown in
A first form standard 34 is shown disposed adjacent to upper surface 20 of CSP 18. A second form standard is also shown associated with CSP 16. Form standard 34 may be fixed to upper surface 20 of the respective CSP with an adhesive 36 which preferably is thermally conductive. Form standard 34 may also, in alternative embodiments, merely lay on upper surface 20 or be separated from upper surface 20 by an air gap or medium such as a thermal slug or non-thermal layer. A form standard may be employed on each CSP in module 10 for heat extraction enhancement as shown in the depiction of
Form standard 34 is, in a preferred embodiment, devised from copper to create, as shown in the depicted preferred embodiment of
In one preferred embodiment, portions of flex circuits 30 and 32 are fixed to form standard 34 by bonds 35 which are, in some preferred modes, metallurgical bonds created by placing on form standard 34, a first metal layer such as tin, for example, which, when melted, combines with a second metal that was placed on the flex circuitry or is part of the flex circuitry (such as the gold plating on a conductive layer of the flex) to form a higher melting point intermetallic bond that will not remelt during subsequent reflow operations as will be described further.
Although those of skill will recognize that the Figs. are not drawn to scale, the contacts 28 of CSPs 16 and 18 have been shown to have (although need not exhibit in every embodiment) a limited height above the lower surface 22 of the corresponding CSP.
With reference to
As further depicted in
As shown in this embodiment, contacts 28 of CSP 18 have height Dc which is less than height D1 shown in earlier
With a thicker glue line between flex and form standard 34, upon reflowing, the solder in contacts 28 mixes with solder paste 41 and reaches to span the space between CSP 18 and the flex circuitry which is now a fixed distance away from CSP 18. This results in a larger vertical dimension for contact 28 than is necessary due to the higher glue line and, consequently, a module 10 with a taller profile. The higher glue line was created by not reducing the contact diameters before attachment of the flex circuitry to the form standard 34 (or the form standard part of combination 37). With the preferred methods of the present invention, however, upon reflow, the compressed contacts 28 mix with solder paste 41 and set beneficially as lower diameter contacts 28. The resulting unit combining combination 37 with flex circuitry may then be employed to create low profile embodiment of module 10.
A variety of methods may be used to provide the localized heating appropriate to implement the metallic bonding described here including localized heat application with which many in the art are familiar as well as ultrasonic bonding methods where the patterns in the flex circuitry are not exposed to the vibration inherent in such methods and the metals chosen to implement the bonds have melting points within the range achieved by the ultrasonic method.
The creation of intermetallic bonds may also be employed to bond combination 37 to flex circuitry along other sites where form standard 34 and flex circuitry are adjacent such as, for example, on sites or continuously along the top side of form standard where typically glue is otherwise applied to further fasten flex circuitry to form standard 34. The intermetallic bonding described here may be employed alone or with other methods such as the contact compression techniques described herein to create instances of module 10 that present a low profile.
In a preferred embodiment, flex circuits 30 and 32 are multi-layer flexible circuit structures that have at least two conductive layers. Other embodiments may, however, employ flex circuitry, either as one circuit or two flex circuits to connect a pair of CSPs, that have only a single conductive layer and may exhibit the variety of simple construction parameters that are known to those of skill in the art with such features as covercoats on one, both or neither side.
Preferably, the conductive layers are metal such as alloy 110 and as those of skill will know, often have conductive areas plated with gold. The use of plural conductive layers provides advantages and the creation of a distributed capacitance across module 10 intended to reduce noise or bounce effects that can, particularly at higher frequencies, degrade signal integrity, as those of skill in the art will recognize. Module 10 of
Although the present invention has been described in detail, it will be apparent to those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.