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Publication numberUS20050243827 A1
Publication typeApplication
Application numberUS 11/151,271
Publication dateNov 3, 2005
Filing dateJun 14, 2005
Priority dateFeb 14, 2001
Also published asCN1504035A, CN1613041A, CN100367730C, US7290162, US7818541, US7856543, US7917727, US8127112, US8200686, US20020159466, US20020161926, US20030041163, US20040114609, US20040130367, US20050242976, US20070217453, US20070220232, US20110083000, WO2002065259A1, WO2002065700A2, WO2002065700A3
Publication number11151271, 151271, US 2005/0243827 A1, US 2005/243827 A1, US 20050243827 A1, US 20050243827A1, US 2005243827 A1, US 2005243827A1, US-A1-20050243827, US-A1-2005243827, US2005/0243827A1, US2005/243827A1, US20050243827 A1, US20050243827A1, US2005243827 A1, US2005243827A1
InventorsJohn Rhoades
Original AssigneeJohn Rhoades
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Lookup engine
US 20050243827 A1
Abstract
A look up engine 200 comprising a storage means 212 a, 212 b for storing a plurality of entries, each entry comprising a value and an associated key value, such that, in operation, a look up is carried out by outputing a value which is associated with the stored key value which matches an input key value. The look up engine 200 comprises a plurality of look up state machines 206 a, 206 b, 206 c, 206 d connected in parallel to enable multiple look ups to be carried out concurrently. Each entry comprises an associated skip value, if the skipped bits of the input key value and the associated skip value mismatches, an error message is output to indicate lookup failure. The entries may be stored in a trie format which is constructed by identifying overlapping ranges between the plurality of entries; splitting the identified overlapping ranges; storing the plurality of entries within a trie structure.
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Claims(8)
1-25. (canceled)
26. A look up engine comprising at least one storage means for storing a plurality of entries, each entry comprises a key value, an associated value and a skip value, such that, in operation a look up is carried out by outputting a value which is associated with the stored key value which matches an input key value, the input key comprising a plurality of bits, if the skipped bits of the input key value and the associated skip value mismatches, an error message is output to indicate lookup failure.
27. A look up engine according to claim 26, wherein the error message further comprising additional data including indication of the type of error.
28. A look up engine according to claim 26, wherein multiple look ups are carried out concurrently.
29. A method for looking up a value, each value having a key value and a skip value associated therewith, the method comprising the steps of:
receiving a key value comprising a plurality of bits;
comparing the input key value with a plurality of stored key values;
comparing the skip value associated with the value corresponding to the input key value with the skipped bits of the input key value;
outputting the value associated with the stored key value that matches the input key value if the skip value matches the skipped bits of the input key value, and outputting an error message to indicate look up failure if the skip value does not match the skipped bits of the input key.
30. A method according to claim 29, wherein the output error message comprises additional data including an indication of the type of error.
31. A method according to claim 29, wherein multiple look ups are carried out concurrently.
32-36. (canceled)
Description
    TECHNICAL FIELD
  • [0001]
    The present invention relates to a look up engine for use in computer systems. In particular, but not exclusively, it relates to look-up engine for use in routing tables, flow tables and access control lists.
  • BACKGROUND OF THE INVENTION
  • [0002]
    One area in which look up tables are extensively used are in routing tables for use by a router. A router is a switching device which receives a packet, and based on destination information contained within the data packet, routes the packet to its destination.
  • [0003]
    Each packet contains a header field and data field. The header field contains control information associated with the routing of the packet including source and destination information. On receiving a packet, a router identifies the key in the header field. The key contains the information that is used to look up the route for the received packet.
  • [0004]
    The look up table includes a plurality of entries having a route destination associated with a “key”. After a key for a packet has been determined, the router performs the look-up in the look up table for the matching entry and hence the destination associated with the key and routes the packet accordingly. A given key may typically match a large number of routes in the look up table.
  • [0005]
    Traditional routing processes using a conventional look up table are very time consuming. One known method to speed up this look up process is to cache the most recent or often performed matches.
  • [0006]
    Furthermore it is difficult to update conventional look up tables to change routing information.
  • [0007]
    One solution to this is to provide a look up table in which the entries are stored in a special format, known as a “trie”. A trie is a multi-way tree structure used for organising data to optimise lookup performance. The data is organized as a set of linked nodes, in a tree structure. Each trie node contains a power-of-two number of entries. Each entry is either empty or contains the lookup result. If the entry is empty, it will point to another trie node and the look up process is repeated. If the entry contains the look up value, this value is returned and the look up process is effectively terminated.
  • [0008]
    A particular form of such a trie is a level-compressed trie (LC-trie) data structure also known as a “Patricia” tree (Practical Alogorithm to Retrieve Information Coded In Alphanumeric).
  • [0009]
    A traditional trie uses every part (bit or characters) of the key. in turn, to determine which subtree to select. However, a Patricia tree nominates (by storing its position in the node) which element of the key will next be used to determine the branching. This removes the need for any nodes with just one descendent and consequently the Patricia tree utilises less memory than that required by a traditional trie. However, Patricia trees are fairly expensive to generate, so a table which utilises such a format is best used in applications for which lookup speed is more important than update speed. However, with increasing complexity of routers and hence the increased size of such look tables, it has become inceasingly important to increase the speed of look up and the accuracy of lookup.
  • SUMMARY OF THE INVENTION
  • [0010]
    The object of the present invention is to provide a look up engine and look up process which provides fast and accurate look up.
  • [0011]
    This is achieved in accordance with a first aspect of the present invention by providing a look up table comprising a plurality of parallel look up state machine which can provide concurrent look ups. Each look up state machine accesses storage means, preferably comprising a plurality of parallel, independent memory banks, in which the look up table may be constructed on the basis of a trie, more preferably a Patricia tree structure. Such a look up table provides increased performance by doing multiple parallel lookups to multiple memory banks in parallel. The returned value may be a final value or reference to another table.
  • [0012]
    The object of the invention is also achieved in accordance with a second aspect of the present invention by providing each trie entry with a skip value field. This enables the ability to avoid false hits, avoiding a memory access to check if a table hit is real. Conventional tries return false hits. During the lookup process, the skip value field is compared to the skipped key bits, and a lookup failure is signalled if they do not match. In the traditional implementation of LC-tries, skip values are not stored in the trie entries, which gives rise to false hits in the table. The possibility of false hits means that hits have to be confirmed by performing an additional memory reference to the full table. The provision of a skip value field for each entry eliminates the need for this extra memory reference, at the expense of somewhat larger entries. The look up engine in accordance with the first aspect may incorporate the feature of the second aspect. If the feature of the second aspect is not incorporated, then it can be appreciated that the false hits may be returned but the memory required for the look up table or tables would be reduced. Further, it can be appreciated that further processing would be required to detect such false hits.
  • [0013]
    Key lengths, for example, can be up to 128 bits and values can be up to 41 bits. The table lookup engine has some internal memory for table storage, and it can also use memory external to the table lookup engine block.
  • [0014]
    The object of the invention is also achieved in accordance with a third aspect of the present invention by providing a table lookup engine which deals with longest prefix matching by pre-processing the entries to split overlapping ranges. The conventional method is to maintain a “history stack” in the trie hardware for this. In pre-processing the entries in this way, the hardware is simplified.
  • [0015]
    In the event of multiple tables which may be used for different protocols, then these could be stored as separate tables and which table to be search is chosen by the value of the input key. Alternatively, the tables may be combined in the same tree so the first look up (and therefore the first bits of the input key value) is which way to branch to get at the appropriate sub-table.
  • [0016]
    Multiple logical tables can be supported simultaneously by prep ending the keys with a table selector.
  • [0017]
    The table lookup engine according to the present invention is capable of returning the number of bits that did match in the case of a table miss.
  • [0018]
    Parallel lookups can be further accelerated by pre-processing the tables, such that lookups that require more memory accesses have their entries preferentially placed in fast, on-chip RAM.
  • [0019]
    Further, in accordance with a preferred embodiment, the lookup table or tables is constructed in software giving a high degree of flexibility, for example, the length of the key value can be fixed or of variable length, the tree depth is programmable and the size of the tree and performance can be optimised. It is simply to design the look up with or without the facility of minimising false hits. Of course, it can be appreciated that a table which has false hits would be smaller in size, but would require further processing of the result to detect false hits. The software utilised by the present invention pre-processes the data into the trie structure which enables different performance trade-offs and types of lookups/return values possible with the same simple hardware.
  • BRIEF DESCRIPTION OF DRAWINGS
  • [0020]
    FIG. 1 is a schematic block diagram of the LC-trie data structure of the look up table according to an embodiment of the present invention; and
  • [0021]
    FIG. 2 is a schematic block diagram of the table look up engine according to the embodiment of the present invention.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • [0022]
    With reference to FIG. 1, the trie structure of a look up table according to an embodiment of the present invention will be described. The look up table comprises a plurality of entries 110 a-110 d, 120 a-120 h. Each entry comprises a look up value and an associated key value. The entries are arranged within the look up table in a plurality of hierarchal nodes, for example a first level 110 and a second level 120. Although only two levels are illustrated here, it can be appreciated that any number of levels may be supported.
  • [0023]
    A key 100 is input into the look up table. A predetermined number of the leading bits of the input key 100 are used to index into the first level 110 of the hierarchy of nodes. This is done by adding the value of these bits to the base address of the node. In the example shown in FIG. 1, the leading bits 101 of the input key 100 point to an entry 110 b of the first level of nodes 110. The entry 110 b contains a skip count and a skip value. The skip count causes the look up process to skip a predetermined number of bits 102 in the input key 100. The skip value indicates the number of bits 103 to be used to index into the next level 120 of nodes. As in the previous level the look up is carried out by adding the value of these bits 103 to the base address of the node 120. This points to a particular entry 120 f. This entry 120 f contains the final value. The value is returned and the look up process is terminated.
  • [0024]
    In this example, two memory accesses were used to do the lookup, one in trie level 110 and the other in trie level 120. In practice, real tables contain many more nodes and levels than shown in this example. For instance, a typical forwarding table, in accordance with a preferred embodiment of the present invention, with 100,000 entries might contain 6 levels and 200,000 nodes.
  • [0025]
    In the preferred embodiment, the size of each entry within the nodes is fixed at 8 bytes and is independent of the size of the key. This enables the internal memory width to be set to 8 bytes so that it is useful as ordinary memory when used in a bypass mode. A typical format of a node entry may be as shown in Table I.
    TABLE I
    field bits usage
    bcnt 4 number of key bits used to index next
    node
    scnt 4 number of key bits to skip
    sbits 15 value to check against key when skipping
    bindx 22 location of next node
  • [0026]
    If, for example, all the bits of bcnt is set to one, the remaining bits in the entry represent a value (either an actual value or the special value for lookup failure). This means that values can contain up to 60 bits. It also means that 1<=bcnt<=14, so the maximum node size is 214 entries. If any one of the bits of bcnt is not set to one, the entry represents a pointer to another node.
  • [0027]
    The depth of a trie depends primarily on the number of entries in the table and the distribution of the keys. For a given table size, if the keys tend to vary mostly in their most significant bits, the depth of the trie will be smaller than if they tend to vary mostly in their least significant bits. A branch of the trie terminates in a value entry when the bits that were used to reach that entry determine a unique key. That is to say, when there does not exist two different keys with the same leading bits.
  • [0028]
    The nodes of a trie can contain many empty entries. Empty entries occur when not all possible values of the bit field used to index a node exist in the keys that are associated with that node. For such routing tables about half the nodes are empty. Since, in the preferred embodiment, the size of a node entry is 8 bytes, such tables will consume about 16 bytes of memory per table entry.
  • [0029]
    Each trie entry in the look up table, according to the embodiment of the present invention, includes a skip value field. During the lookup process, the skip value field is compared to the skipped key bits, and a lookup failure is signalled if they do not match.
  • [0030]
    The table lookup engine comprises at least one interface unit. The interface unit comprises an initiator and target interfaces to connect to a bus system of a processing system. The initiator comprises a control and status interface for initialization, configuration and statistics collection, which is in the peripheral virtual component interface (PVCI) address space. There is a lookup interface for receiving keys and sending results of lookups, which is in the advanced virtual component interface (AVCI) address space. There is a third memory interface that makes the internal memory of the table lookup engine available as ordinary memory, which is in the AVCI address space. All these interface units can be used concurrently. It is possible to make use of the memory interface while the table lookup engine is busy doing lookups. Indeed, this is how the tables in the table lookup engine are updated without disrupting lookups in progress. The table lookup engine can be configured to use external (to the block) memory which can be accessed by the bus, in addition to or instead of its internal memory.
  • [0031]
    There are several internal registers that can be read or written. The control interface provides the following functions. Note that the key and value sizes are not configurable via this interface. The application that generates the tables determines how many key bits will actually be used. In the preferred embodiment, the processing system supports key sizes of 32, 64 or 128 bits, but internally the table lookup engine expands shorter keys to 128 bits, by appending extra lower-significance bits. The table lookup engine always returns 64 bit values, but it is up to the application how many of these bits to use.
    TABLE II
    Reset
    Field Bits Value Function
    Reset 0 0 When set (reset = 1), perform a complete
    reset of the table lookup engine blocks
    Enable 1 0 When set (Enable = 1), enable the table
    lookup engine
    CountersOn 2 0 When set (CountersOn = 1), enable
    updating of the counters
  • [0032]
    TABLE III
    Reset
    Field Bits Value Function
    ResetStatus 0 0 Indicates whether the table lookup
    engine is busy resetting or not
    EnableStatus 1 0 Indicates the enable state of the
    table lookup engine
    CountersOnStatus 2 0 Indicates whether updating the
    counters mode is enabled
  • [0033]
    TABLE IV
    Reset
    Field Bits Value Function
    IntMemoryStart 31:0 note Start location of internal memory in
    bytes
    IntMemorySize 31:0 note Size of internal memory in bytes
  • [0034]
    Note: After reset, these registers contain the start and size of the entire internal memory. The application can change these if it wishes to reserve some portion of the memory for non-table lookup engine purposes.
    TABLE V
    Reset
    Field Bits Value Function
    ExtMemoryStart 31:0 0 Start location of internal memory in
    bytes
    ExtMemorySize 31:0 0 Size of internal memory in bytes
  • [0035]
    TABLE VI
    Reset
    Field Bits Value Function
    NumLookups 31:0 0 Number of lookups
    NumIntMem- 31:0 0 Number of internal memory reads
    Reads
    NumExtMem- 31:0 0 Number of external memory reads
    Reads
    NumIntBank- 31:0 0 Number of reads by internal memory bank
    ReadsN (N registers, where N is number of
    banks)
    NumExtBank- 31:0 0 Number of reads by external memory bank
    ReadsN (M registers, where M is number of
    banks)
  • [0036]
    The table lookup engine internal memory accoridng to the embodiment of the present invention is organised as two equal size, independent banks. The size of these banks is a synthesis parameter. They are organised as a configurable number of entries with a width of 8 bytes. The maximum number of entries that can be configured for a bank is 131072, which implies a maximum total memory size of 2 megabytes. Clients can use the table lookup engine internal memory in the same way as ordinary memory, bypassing the lookup state machines. The address for a memory access selects one or more entries (depending on the details of the bus transaction) for reading or writing.
  • [0037]
    The protocol for a lookup is an AVCI write transaction to address TLEKeyAddr. Multiple keys can be submitted for lookup in a single write transaction. The table lookup engine responds by sending back an AVCI read response to the source interface containing the values.
  • [0038]
    The table lookup engine has a key input FIFO with at least 128 slots, so it can accept at least that many keys without blocking the bus.
  • [0039]
    Lookups that succeed return the value stored in the table. Lookups that fail (the key is not in the table) return a special “missing value” containing a bit pattern specified by the user. It is feasible to construct the tables in such a way that a lookup failure returns additional information, for example, the number of bits of the key that do match in the table. This assists the processing system in evaluating the cause of the failure.
  • [0040]
    The table lookup engine does not internally support longest prefix matching, but that effect can still be achieved by constructing the tables in the proper way. The idea is to split the overlapping address ranges into disjoint pieces.
  • [0041]
    Lookup values may not necessarily be returned in the order of the keys. The transaction tagging mechanism of AVCI is used to assist client blocks in coping with ordering changes.
  • [0042]
    Multiple client blocks can submit lookup requests simultaneously. If this causes the input FIFO to fill up, the bus lane between the requestor block and the table lookup engine will block temporarily. The table lookup engine keeps track internally of the source port of the requester for each lookup, so the result values will be sent to the correct place. This may to return the result to the requester or elsewhere.
  • [0043]
    The contents of the memory being used by the table lookup engine can be updated while lookups are in progress. The actual updates are done via the memory interface. A software protocol is adopted to guarantee table consistency.
  • [0044]
    The table lookup engine 200, as shown in FIG. 2, comprises an input FIFE buffer 202 connected to the input of a distributor 204. the output of the distributor is connected in parallel to a plurality of lookup state machines 206 a, 206 b, 206 c, 206 d. Each lookup state machine 206 a, 206 b, 206 c, 206 d has access to a storage means. The storage means comprises a memory arbiter 208 and a plurality of parallel independent memory banks 212 a, 212 b. Each lookup state machine 206 a, 206 b, 206 c, 206 d is connected to the input of a collector 210. The output of the collector 210 is connected to an output FIFO buffer 214.
  • [0045]
    The table lookup engine uses a number of lookup state machines (LSM) 206 a, 206 b, 206 c, 206 d operating concurrently to perform lookups. Incoming keys from the bus are held in an input FIFO 202. These are distributed to the lookup state machines 206 a, 206 b, 206 c, 206 d by a distributor block 204. Values coming from the state machines are merged by a collector block 210 and fed to an output FIFO 214. From here the values are sent out on the bus to the requester.
  • [0046]
    The entries of the input FIFO 202 each contain a key, a tag and a source port identifier. This FIFO 202 has at least 128 slots, so two clients can each send 64 keys concurrently without blocking the bus lane. Even if the FIFO 202 fills, the bus will only block momentarily.
  • [0047]
    The distributor block 204 watches the lookup state machines 206 a, 206 b, 206 c, 206 d and sends a key to any one that is available to do a new lookup. A priority encoder may be used to choose the first ready state machine.
  • [0048]
    The lookup state machines 206 a, 206 b, 206 c, 206 d do the lookup using a fixed algorithm. They treat all keys as 128 bits and all values as 60 bits internally. These sizes were chosen somewhat arbitrarily. It would be possible to extend the maximum key size to 256 bits. The main impact on the table lookup engine would be an increase in the size of the input FIFO 202 and LSMs 206 a, 206 b, 206 c, 206 d. It would be possible to increase the maximum size of the result. The main impact would be that trie entries would be larger than 8 bytes, increasing the overall table lookup engine memory required for a given size table. Shorter keys are easily extended by adding zero-valued least significant bits. Memory read requests are sent to the memory arbiter block 208. The number of memory requests needed to satisfy a given lookup is variable, which is why the table lookup engine may return out-of-order results.
  • [0049]
    The collector block 210 serialises values from the lookup state machines 206 a, 206 b, 206 c, 206 d into the output FIFO 214. A priority encoder may be used to take the first available value.
  • [0050]
    The memory arbiter block 208 forwards memory read requests from the state machines 206 a, 206 b, 206 c, 206 d to the appropriate memory block 212 a, 212 b. This might be to an internal memory bank or an external memory accessed via the bus. The table lookup engine has an FBI initiator block for performing external memory reads. If the block using the table lookup engine and the external memory are on the same side of the table lookup engine, there will be bus contention. Avoiding this requires a bus layout constraint: the table lookup engine must sit between the main processing units and the external memory, and the table lookup engine initiator interface must be closest to the memory target interface. Whether or not a memory read request goes to off-chip memory is determined by the external memory configuration registers.
  • [0051]
    The output FIFO 214 contains result values waiting to be sent to the requester block. Each slot holds a value, a tag and a port identifier. if the table lookup engine received more than one concurrent batch of keys from different blocks, the results are intermingled in this FIFO 214. The results are sent to the correct clients in the order they enter the output FIFO 214, and it is up to the clients to use the tag to properly associate keys and values.
    Lookup algorithm
      ValueType lookup(const lcsnode* trie, KeyType key)
      {
        // toplgwd is size of level 0 node
        int idx = key.topbits(toplgwd);
        key = key<<toplgwd;
        lcsnode nd = trie[idx]; // current entry
        while (nd.bcnt != 15) {
          unsigned int cksbits =
      key.topbits(nd.scnt);
          key = key<<nd.scnt;
          if (cksbits != nd.sbits) return
      missingValue;
          int nidx = key.topbits(nd.bcnt);
          key = key<<nd.bcnt;
          idx = nd.bindx+nidx;
          nd = trie[idx];
        }
        return
      concatenate(nd.scnt,nd.sbits,nd.bindx);
      }
  • [0052]
    The table lookup engine according to the embodiment of the present invention can achieve a peak performance of about 300 million lookups/second. This level of performance is based on the table lookup engine internal memory system being able to sustain a memory cycle rate of 800 million reads/second. This is achieved by using two banks of memory operating at 400 million reads/second with pipelining reads. The latency of the internal memory system needs to be of the order of 4-8 cycles. The number of state machines is chosen to saturate the memory interface. That is to say, there are enough state machines so that one of them is doing a memory access on nearly every cycle, for example 24 LSMs. Higher memory latencies can be tolerated by increasing the number of lookup state machines, but the practical limit is about 32 state machines.
  • [0053]
    The table lookup engine state machine lookup algorithm is fixed and fairly simple, to attain performance. The way that the table lookup engine achieves great flexibility in applications is in the software that constructs the LC-trie data structure. With this flexibility comes a cost, of course. It is expensive to generate the trie structure. The idea for using the table lookup engine is that some general purpose processor—for example in the control plane—preconstructs the trie data and places it in memory that is accessible by the bus, perhaps an external SRAM block. An onboard embedded processing unit is notified that a table update is ready and it does the actual update in the table lookup engine memory. The table lookup engine state machines consider the memory it uses to be big-endian. When constructing trie structures the correct type of endianness needs to be employed. In this way the table lookup engine can provide longest prefix matching. When constructing the trie from the routing table, overlapping ranges can be identified and split. This preprocessing step is not very expensive and does not significantly increase the trie size for typical routing tables. It also allows multiple concurrent tables to exist. This is achieved by prepending a small table identifier to the key. With eight tables, this would require three bits per key.
  • [0054]
    The table lookup engine according to the present invention can return the number of matching bits. The lookup engine returns whatever bits it finds in the last trie entry it fetched. Further, on a lookup failure that entry is uniquely determined by the lookup algorithm; it is the entry that would have contained the value had the missing key been present. The program that generates the trie structure could fill in all empty trie entries with the number of matching bits required to reach that trie entry. These return values could be flagged some way to distinguish them from lookup table hits by the generator program. Then the table lookup engine would return the number of matching bits on a lookup failure.
  • [0055]
    The table lookup engine according to the present invention also enables concurrent lookups and updates. One way to achieve this would be to have two versions of the table in table lookup engine memory simultaneously, and switch between them with a single write to a table lookup engine configuration register. Then lookups in progress will find either a value from the old version of the table or a value from the new version of the table. The embedded processing unit achieves this by first placing the new level 1-n nodes in the table lookup engine memory, then overwriting the level 0 node entry that points to the new nodes.
  • [0056]
    The table lookup engine according to the present invention also allows very large results to be produced. If a value for a given key needs to be more than 60 bits, an auxiliary table can be placed in the table lookup engine memory—actually any available memory—and an index into the auxiliary table placed in the table lookup engine value. The auxiliary table would then be read using normal memory indexing. This is purely a software solution, and has no implications to the table lookup engine internal operation.
  • [0057]
    Although a preferred embodiment of the method and apparatus of the present invention has been illustrated in the accompanying drawings and described in the forgoing detailed description, it will be understood that the invention is not limited to the embodiment disclosed, but is capable of numerous variations, modifications without departing from the scope of the invention as set out in the following claims.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4755986 *Sep 11, 1986Jul 5, 1988Nec CorporationPacket switching system
US4850027 *Feb 5, 1988Jul 18, 1989International Business Machines CorporationConfigurable parallel pipeline image processing system
US4860191 *Aug 8, 1986Aug 22, 1989Nec CorporationCoprocessor with dataflow circuitry controlling sequencing to execution unit of data received in tokens from master processor
US4876641 *Jul 31, 1987Oct 24, 1989Active Memory Technology Ltd.Vlsi data processor containing an array of ICs, each of which is comprised primarily of an array of processing
US4899216 *Aug 26, 1987Feb 6, 1990Fuji Photo Film Co., Ltd.Method of and apparatus for processing an image with gradation correction of video signal
US4922487 *Dec 16, 1988May 1, 1990Alcatel N.V.Packet-switching facilities
US5021947 *Jan 30, 1990Jun 4, 1991Hughes Aircraft CompanyData-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and data processing
US5021950 *Dec 12, 1985Jun 4, 1991Kabushiki Kaisha ToshibaMultiprocessor system with standby function
US5121198 *Jun 28, 1990Jun 9, 1992Eastman Kodak CompanyMethod of setting the contrast of a color video picture in a computer controlled photographic film analyzing system
US5122679 *Oct 13, 1989Jun 16, 1992Hitachi, Ltd.Integrated logic circuit with clock skew adjusters
US5155484 *Sep 13, 1991Oct 13, 1992Salient Software, Inc.Fast data compressor with direct lookup table indexing into history buffer
US5218709 *Dec 28, 1989Jun 8, 1993The United States Of America As Represented By The Administrator Of The National Aeronautics And Space AdministrationSpecial purpose parallel computer architecture for real-time control and simulation in robotic applications
US5224100 *May 9, 1991Jun 29, 1993David Sarnoff Research Center, Inc.Routing technique for a hierarchical interprocessor-communication network between massively-parallel processors
US5325493 *Mar 30, 1993Jun 28, 1994Hewlett-Packard CompanySystem for distributing command/data packets tagged by their unit identifier for parallel processing by a ready processing unit and recombination
US5327159 *Sep 3, 1993Jul 5, 1994Texas Instruments IncorporatedPacked bus selection of multiple pixel depths in palette devices, systems and methods
US5398262 *Feb 22, 1993Mar 14, 1995Intel CorporationSkew-free clock signal distribution network in a microprocessor of a computer system
US5404550 *Jul 25, 1991Apr 4, 1995Tandem Computers IncorporatedMethod and apparatus for executing tasks by following a linked list of memory packets
US5418970 *Feb 22, 1990May 23, 1995Massachusetts Institute Of TechnologyParallel processing system with processor array with processing elements addressing associated memories using host supplied address value and base register content
US5420858 *May 5, 1993May 30, 1995Synoptics Communications, Inc.Method and apparatus for communications from a non-ATM communication medium to an ATM communication medium
US5428812 *Jun 24, 1994Jun 27, 1995Sharp Kabushiki KaishaData driven processors system for adaptively configuring width of the destination field based on the number of detected information processors
US5440550 *Jul 1, 1992Aug 8, 1995Telstra Corporation LimitedHigh speed switching architecture
US5463732 *May 13, 1994Oct 31, 1995David Sarnoff Research Center, Inc.Method and apparatus for accessing a distributed data buffer
US5524223 *Jun 12, 1995Jun 4, 1996Motorola, Inc.Instruction accelerator for processing loop instructions with address generator using multiple stored increment values
US5603028 *Jan 31, 1995Feb 11, 1997Mitsubishi Denki Kabushiki KaishaMethod and apparatus for data distribution
US5612956 *Dec 15, 1995Mar 18, 1997General Instrument Corporation Of DelawareReformatting of variable rate data for fixed rate communication
US5625836 *Jun 2, 1995Apr 29, 1997International Business Machines CorporationSIMD/MIMD processing memory element (PME)
US5640551 *Apr 14, 1993Jun 17, 1997Apple Computer, Inc.Efficient high speed trie search process
US5651099 *Jan 26, 1995Jul 22, 1997Hewlett-Packard CompanyUse of a genetic algorithm to optimize memory space
US5659781 *Jun 29, 1994Aug 19, 1997Larson; Noble G.Bidirectional systolic ring network
US5682480 *Aug 14, 1995Oct 28, 1997Hitachi, Ltd.Parallel computer system for performing barrier synchronization by transferring the synchronization packet through a path which bypasses the packet buffer in response to an interrupt
US5689677 *Jun 5, 1995Nov 18, 1997Macmillan; David C.Circuit for enhancing performance of a computer for personal use
US5708836 *Jun 7, 1995Jan 13, 1998International Business Machines CorporationSIMD/MIMD inter-processor communication
US5713037 *Jun 7, 1995Jan 27, 1998International Business Machines CorporationSlide bus communication functions for SIMD/MIMD array processor
US5717943 *Jun 5, 1995Feb 10, 1998International Business Machines CorporationAdvanced parallel array processor (APAP)
US5717944 *Jun 7, 1995Feb 10, 1998International Business Machines CorporationAutonomous SIMD/MIMD processor memory elements
US5752067 *Jun 7, 1995May 12, 1998International Business Machines CorporationFully scalable parallel processing system having asynchronous SIMD processing
US5754584 *Jun 7, 1995May 19, 1998Omnipoint CorporationNon-coherent spread-spectrum continuous-phase modulation communication system
US5754871 *Jun 7, 1995May 19, 1998International Business Machines CorporationParallel processing system having asynchronous SIMD processing
US5761523 *Jun 7, 1995Jun 2, 1998International Business Machines CorporationParallel processing system having asynchronous SIMD processing and data parallel coding
US5768275 *Apr 15, 1996Jun 16, 1998Brooktree CorporationController for ATM segmentation and reassembly
US5778241 *Apr 10, 1996Jul 7, 1998Rockwell International CorporationSpace vector data path
US5781549 *Feb 23, 1996Jul 14, 1998Allied Telesyn International Corp.Method and apparatus for switching data packets in a data network
US5781772 *May 15, 1995Jul 14, 1998Digital Equipment CorporationCompressed prefix matching database searching
US5822606 *Feb 16, 1996Oct 13, 1998Morton; Steven G.DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word
US5822779 *Mar 21, 1997Oct 13, 1998National Semiconductor CorporationMicroprocessor-based data processing apparatus that commences a next overlapping cycle when a ready signal is detected not to be active
US5828870 *Jun 30, 1997Oct 27, 1998Adaptec, Inc.Method and apparatus for controlling clock skew in an integrated circuit
US5828885 *Aug 16, 1996Oct 27, 1998Microsoft CorporationMethod and system for merging files having a parallel format
US5872993 *Dec 1, 1997Feb 16, 1999Advanced Micro Devices, Inc.Communications system with multiple, simultaneous accesses to a memory
US5918061 *Nov 10, 1997Jun 29, 1999Intel CorporationEnhanced power managing unit (PMU) in a multiprocessor chip
US5923660 *Jan 28, 1997Jul 13, 1999Galileo Technologies Ltd.Switching ethernet controller
US5963746 *Jun 6, 1995Oct 5, 1999International Business Machines CorporationFully distributed processing memory element
US5969559 *Jun 9, 1997Oct 19, 1999Schwartz; David M.Method and apparatus for using a power grid for clock distribution in semiconductor integrated circuits
US6014659 *Jun 7, 1995Jan 11, 2000Cabletron Systems, Inc.Compressed prefix matching database searching
US6035193 *Jun 28, 1996Mar 7, 2000At&T Wireless Services Inc.Telephone system having land-line-supported private base station switchable into cellular network
US6047304 *Jul 29, 1997Apr 4, 2000Nortel Networks CorporationMethod and apparatus for performing lane arithmetic to perform network processing
US6052592 *Jan 28, 1997Apr 18, 2000Motorola, Inc.Call routing system for a wireless data device
US6052769 *Mar 31, 1998Apr 18, 2000Intel CorporationMethod and apparatus for moving select non-contiguous bytes of packed data in a single instruction
US6081523 *Dec 5, 1997Jun 27, 2000Advanced Micro Devices, Inc.Arrangement for transmitting packet data segments from a media access controller across multiple physical links
US6088355 *Oct 11, 1996Jul 11, 2000C-Cube Microsystems, Inc.Processing system with pointer-based ATM segmentation and reassembly
US6094715 *Jun 7, 1995Jul 25, 2000International Business Machine CorporationSIMD/MIMD processing synchronization
US6101176 *Mar 12, 1997Aug 8, 2000Nokia Mobile PhonesMethod and apparatus for operating an indoor CDMA telecommunications system
US6115802 *Mar 3, 1998Sep 5, 2000Sun Mircrosystems, Inc.Efficient hash table for use in multi-threaded environments
US6131102 *Jun 15, 1998Oct 10, 2000Microsoft CorporationMethod and system for cost computation of spelling suggestions and automatic replacement
US6208619 *Mar 26, 1998Mar 27, 2001Kabushiki Kaisha ToshibaPacket data flow control method and device
US6218861 *Jul 8, 1998Apr 17, 2001Kabushiki Kaisha ToshibaFunctional block and semiconductor integrated circuit architected by a plurality of functional blocks in combination
US6219796 *Dec 15, 1998Apr 17, 2001Texas Instruments IncorporatedPower reduction for processors by software control of functional units
US6240524 *Jun 8, 1998May 29, 2001Nec CorporationSemiconductor integrated circuit
US6301603 *Feb 17, 1998Oct 9, 2001Euphonics IncorporatedScalable audio processing on a heterogeneous processor array
US6366584 *Feb 6, 1999Apr 2, 2002Triton Network Systems, Inc.Commercial network based on point to point radios
US6389018 *Feb 16, 1996May 14, 2002International Business Machines CorporationParallel on-the-fly processing of fixed length cells
US6393026 *Sep 17, 1998May 21, 2002Nortel Networks LimitedData packet processing system and method for a router
US6605001 *Apr 20, 2000Aug 12, 2003Elia Rocco TarantinoDice game in which categories are filled and scores awarded
US6631419 *Sep 22, 1999Oct 7, 2003Juniper Networks, Inc.Method and apparatus for high-speed longest prefix and masked prefix table search
US6631422 *Aug 26, 1999Oct 7, 2003International Business Machines CorporationNetwork adapter utilizing a hashing function for distributing packets to multiple processors for parallel processing
US6704794 *Mar 3, 2000Mar 9, 2004Nokia Intelligent Edge Routers Inc.Cell reassembly for packet based networks
US6735219 *Sep 17, 1999May 11, 2004International Business Machines CorporationPacket-processing apparatus and packet switch adapter for the processing of variable-length packets and a method thereof
US6907001 *Mar 5, 1999Jun 14, 2005Hitachi, Ltd.Packet switch for switching variable length packets in the form of ATM cells
US6922716 *Jul 13, 2001Jul 26, 2005Motorola, Inc.Method and apparatus for vector processing
US7016367 *Jan 2, 2001Mar 21, 2006Juniper Networks, Inc.Systems and methods for allocating bandwidth for processing of packets
US7290162 *Feb 14, 2002Oct 30, 2007Clearspeed Solutions LimitedClock distribution system
US7317730 *Oct 11, 2002Jan 8, 2008Greenfield Networks, Inc.Queueing architecture and load balancing for parallel packet processing in communication networks
US7349389 *May 22, 2003Mar 25, 2008Infineon Technologies AgUnit and method for distributing and processing data packets
US7382782 *Apr 12, 2002Jun 3, 2008Juniper Networks, Inc.Packet spraying for load balancing across multiple packet processors
US7656799 *Jul 28, 2004Feb 2, 2010Citrix Systems, Inc.Flow control system architecture
US7751402 *Oct 10, 2003Jul 6, 2010Intel CorporationMethod and apparatus for gigabit packet assignment for multithreaded packet processing
US7782782 *Apr 24, 2008Aug 24, 2010Juniper Networks, Inc.Packet spraying for load balancing across multiple packet processors
US20010018732 *Jan 18, 2001Aug 30, 2001Junji NakagoshiParallel processor and parallel processing method
US20020003795 *Aug 4, 1998Jan 10, 2002Rasoul Mirzazadeh OskouyIn-line packet processing
US20020075882 *Jun 15, 2001Jun 20, 2002Marc DonisMultiple priority buffering in a computer network
US20020122424 *Feb 19, 2002Sep 5, 2002Kenichi KawaraiInput line interface device and packet communication device
US20030004921 *Jun 28, 2001Jan 2, 2003Schroeder Jacob J.Parallel lookups that keep order
US20030074388 *Oct 12, 2001Apr 17, 2003Duc PhamLoad balanced scalable network gateway processor architecture
US20030093613 *Aug 9, 2002May 15, 2003David ShermanCompressed ternary mask system and method
US20030140212 *Mar 5, 2002Jul 24, 2003Yosef SteinSingle instruction multiple data array cell
US20040017807 *Jul 29, 2002Jan 29, 2004Dorr Martin L.On chip network that maximizes interconnect utilization between processing elements
US20050027793 *Aug 31, 2004Feb 3, 2005Hass David T.Advanced processor with mechanism for packet distribution at high line rate
US20100086233 *Sep 23, 2009Apr 8, 2010Canon Kabushiki KaishaInformation processing apparatus, control method for the same, and computer program
US20100165991 *Dec 30, 2008Jul 1, 2010Veal Bryan ESIMD processing of network packets
US20110013519 *Jul 14, 2009Jan 20, 2011Chang Joseph YParallel Packet Processor with Session Active Checker
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7584286 *Jun 28, 2006Sep 1, 2009Intel CorporationFlexible and extensible receive side scaling
US8150981Aug 28, 2009Apr 3, 2012Intel CorporationFlexible and extensible receive side scaling
US8170019 *May 1, 2012Broadcom CorporationCPU transmission of unmodified packets
US8874767Apr 3, 2012Oct 28, 2014Intel CorporationEnqueuing received network packets based, at least in part, on at least one programmable mask
US20060114895 *Mar 28, 2005Jun 1, 2006Broadcom CorporationCPU transmission of unmodified packets
US20080005352 *Jun 28, 2006Jan 3, 2008Goglin Stephen DFlexible and extensible receive side scaling
US20100061377 *Aug 28, 2009Mar 11, 2010Intel CorporationFlexible and extensible receive side scaling
Classifications
U.S. Classification370/392
International ClassificationG06F1/10, G06F17/50, G06F13/36, H04L12/28, H04L12/54, H04L12/747, H04L12/701
Cooperative ClassificationH04L45/00, H04L12/56, Y10S707/99936, H04L45/742, G06F15/8007, G06F17/505, G06F1/10
European ClassificationH04L12/56, H04L45/742, G06F17/50D2, H04L45/00, G06F15/80A, G06F1/10
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