US 20050250289 A1
An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28 c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28 c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44 c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33). MOS transistors (70, 80) including the diffusion barrier (28) are also disclosed.
14. An integrated circuit comprising at least a first bipolar transistor, comprising
a first buried collector region substantially free of carbon;
an epitaxially-grown silicon-containing layer, substantially free of carbon, overlying the first buried collector region;
a diffusion barrier layer comprised of a carbon-bearing substance disposed near an interface between the first buried collector region and the silicon-containing layer;
a first base layer, substantially free of carbon, at a surface of the silicon-containing layer overlying the first buried collector region; and
a first emitter, substantially free of carbon, at a surface of the first base layer overlying the first buried collector region.
15. The integrated circuit of
a collector contact extending from a surface of the integrated circuit toward the first buried collector region;
wherein the diffusion barrier is located at selected locations of the interface between the first buried collector region and the silicon-containing layer, the selected locations including locations underlying the first emitter and not including locations between the first buried collector region and the collector contact.
16. The integrated circuit of
and wherein the first base layer is of a second conductivity type;
and further comprising a second bipolar transistor, the second bipolar transistor comprising:
a second buried collector region of the second conductivity type, underlying the epitaxially-grown silicon-containing layer;
a diffusion barrier comprised of a carbon-bearing substance disposed near an interface between the second buried collector region and the silicon-containing layer;
a second base layer, of the first conductivity type, at a surface of the silicon-containing layer overlying the second buried collector region; and
a second emitter, of the second conductivity type, disposed at a surface of the second base layer overlying the second buried collector region.
17. The integrated circuit of
and wherein the second buried collector region comprises a region of the semiconductor layer that is doped with arsenic.
18. The integrated circuit of
and wherein the first base layer is of a second conductivity type;
and further comprising a second bipolar transistor, the second bipolar transistor comprising:
a second buried collector region of the first conductivity type, underlying the epitaxially-grown silicon-containing layer;
a second base layer, of the second conductivity type, at a surface of the silicon-containing layer overlying the second buried collector region; and
a second emitter, of the first conductivity type, disposed at a surface of the second base layer overlying the second buried collector region;
wherein the diffusion barrier is located at selected locations of the interface between the first buried collector region and the silicon-containing layer, the selected locations including locations underlying the first emitter and not including locations between the second buried collector region and the second emitter.
19. The integrated circuit of
a buried insulator layer disposed under the semiconductor layer.
20. The integrated circuit of
an MOS transistor within another portion of the epitaxially-grown silicon-containing layer at a location over a second buried collector region, wherein the diffusion barrier is disposed near an interface between the second buried collector region and the silicon-containing layer, the MOS transistor comprising:
a source region, disposed at a surface of the silicon-containing layer;
a drain region, disposed at a surface of the silicon-containing layer; and
a gate electrode, insulatively disposed over the surface of the silicon-containing region at a location between the source and drain regions.
21. A metal-oxide-semiconductor transistor, comprising:
a source region, disposed at a surface of a semiconducting portion of a substrate;
a drain region, disposed at the surface of the semiconducting portion;
a gate electrode, insulatively disposed over the surface of the semiconducting portion at a channel location between the source and drain regions.
a carbon-containing layer disposed in the semiconducting portion below the channel location; and
a heavily-doped region disposed in the semiconducting portion below the carbon-containing layer.
22. The transistor of
a well region, disposed in the semiconducting portion below the heavily-doped region.
23. The transistor of
24. The transistor of
25. The transistor of
a lightly-doped well region disposed in the semiconducting portion between the carbon-containing layer and the surface of the semiconducting portion.
This invention is in the field of semiconductor integrated circuits, and is more specifically directed to the formation of buried doped layers in bipolar transistors in such circuits.
Modern bipolar integrated circuits now typically use vertical bipolar transistors as their active elements. These transistors are vertical in the sense that the active base and emitter regions overlie the collector region, with collector-emitter current traveling through the base in substantially a vertical orientation relative to the plane of the surface of the integrated circuit at which the transistor resides. To provide a robust breakdown voltage, the portion of the collector region adjacent the base is relatively lightly doped. This region is often referred to as the “subcollector”. These lightly-doped subcollectors are relatively resistive, however. Therefore, many modern bipolar structures reduce the effective collector resistance by providing a heavily-doped buried collector layer underlying the subcollector. This buried collector layer provides a relatively low resistance path for collector current between the active region of the transistor and a collector contact located away from the base and emitter. Because the collector current need only travel a short distance through the lightly-doped subcollector, before reaching the buried collector layer, the overall collector resistance is minimized, while still providing a high breakdown voltage because of the lightly-doped subcollector.
This construction results in a significant dopant concentration gradient at the interface between the buried collector regions and the much more lightly-doped overlying subcollector. This gradient does not itself present a problem in the stability of the device. However, because this interface must be created relatively early in the manufacturing process, subsequent high temperature processes provide the opportunity for dopant to diffuse from the buried collector region into the more lightly-doped subcollector. A particularly troublesome high temperature process is the epitaxial formation of the subcollector itself, which exposes the wafer to high temperatures for a relatively long period of time. This updiffusion of dopant from the buried collector can cause significant limitations in the performance and precision of modern bipolar circuits.
Buried collector region 6 is a heavily doped (p-type, in this example) portion of thin film silicon layer 6; portions 6′ of this layer away from transistor 10 p are relatively lightly doped, or intrinsic silicon. Buried collector region 6 provides a low resistance path between collector contact C and the active collector region. Accordingly, collector-emitter current is conducted vertically through epitaxial layer 8 from buried collector region 6 to emitter 15, as illustrated in
However, as shown in
The effect of diffusion from buried collector regions into the device subcollector becomes particularly dramatic in complementary bipolar structures, which by definition include both NPN and PNP bipolar devices, and their respective n-type and p-type buried collector layers.
Typical dopant species for n-type and p-type buried layers 6 n, 6 p are arsenic and boron, respectively. These species differ in diffusion rate by a factor of ten, however, with boron diffusing much faster than arsenic under equivalent conditions. This difference in diffusion rate is evident from
In addition to the loss of control over the buried layer-subcollector interface, undesired diffusion from heavily-doped buried layers can also contaminate structures away from the buried layers, due to auto-doping during epitaxial growth. An example of such undesired diffusion is illustrated in
The sensitivity of complementary bipolar devices to differences in diffusion from the n-type and p-type buried layers is conventionally addressed by constraining the thermal budget for subsequent processing, thus limiting the diffusion from these layers and thus limiting the resulting diffusion. These constraints have resulted in very complex processing that is not only costly, but also typically results in the inability to maximize the performance of the NPN and PNP devices in a symmetric manner (i.e., without sacrificing the performance of one for the performance of the other).
Besides impacting device performance, as noted above, diffusion from the buried collector layers also impacts the breakdown voltage of the individual devices. In the complementary bipolar arrangement, in order to optimize symmetric breakdown behavior for the NPN and PNP devices, the significant difference in diffusion rates necessitates a tradeoff between device breakdown for one of the transistor types (PNP) versus collector resistance of the other transistor types (NPN). In addition, the asymmetric diffusion of the dopant species also creates mismatching of the device characteristics of NPN and PNP devices in a complementary circuit; such mismatches are especially undesirable, considering that the matching of device characteristics is a primary reason for realizing a circuit in complementary bipolar technology in the first place. In addition, the tight constraint on thermal budget because of the rapid diffusion of boron from the buried collectors of the PNP devices also increases the likelihood of mismatch among the PNP devices themselves, as these devices can become quite sensitive to the processing conditions that fall within the thermal budget constraints. These and other device sensitivities are also exacerbated as the physical device sizes continue to scale toward ever decreasing dimensions.
It is therefore an object of the present invention to provide an integrated circuit and method of fabrication that reduces diffusion of dopant from buried doped layers, such as buried collector layers in bipolar transistors.
It is a further object of the present invention to provide such an integrated circuit and method that is especially well-suited for complementary bipolar technology.
It is a further object of the present invention to provide such an integrated circuit and method that retards the diffusion of one dopant species while enhancing the diffusion of a different dopant species, for example to provide a symmetric emitter profile for complementary devices.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
The present invention may be implemented by way of an integrated circuit and method that incorporates carbon into the buried doped layers. The carbon may be incorporated as elemental carbon, or alternatively by the compound SiGeC. Various methods of applying the carbon may be used.
The present invention will now be described in connection with its preferred embodiments. These exemplary embodiments are directed to the fabrication of bipolar junction transistors in a silicon-on-insulator (SOI) structure. It will be appreciated by those skilled in the art having reference to this specification that the present invention may be used to form either p-n-p or n-p-n transistors, or both as may be used in a complementary bipolar or BiCMOS technology, as well as used in other alternative structures and methods of fabricating such structures. In addition, while this invention is particularly beneficial as applied to SOI structures, it is also contemplated that this invention may be utilized in bulk integrated circuit devices as well, where no buried insulator layer is present. Furthermore, while these embodiments are silicon or SiGe NPN and PNP bipolar transistors, it is contemplated that the present invention will be equally applicable to emerging bipolar technologies such as SiGeC (silicon-germanium-carbon) and SiC bipolar technologies It is therefore to be understood that these and other alternatives to the embodiments described below are contemplated to be within the scope of the invention as claimed.
Referring first to
The formation of the structure of buried insulator layer 24 underlying thin film silicon layer 26 may be accomplished by any one of a number of technologies. These technologies include the wafer bonding approach, in which two single-crystal silicon wafers are bonded to one another on either side of a silicon oxide layer, to result in single-crystal layers on either side of the insulator layer. According to another approach, referred to in the art as SIMOX, a single crystal silicon wafer is implanted with oxygen ions, so that a high concentration of oxygen is present at a selected depth within the wafer. The oxygen is thermally reacted with the silicon to form a buried oxide layer about the depth of implantation. These and other conventional techniques for fabricating an SOI structure are suitable for use in connection with this invention.
For the construction of PNP transistor 30 according to the preferred embodiment of the invention, a p-type buried collector region is next formed. Referring now to
To form the active portions of eventual PNP transistor 30, epitaxial silicon is then grown over silicon thin film layer 26, 26′. According to a first preferred embodiment of the invention, this epitaxial growth begins with the epitaxial formation of diffusion barrier 28 c, as will now be described relative to
Following the formation of diffusion barrier 28 c, epitaxial growth of silicon continues in the absence of the diffusion-retarding dopant, until epitaxial silicon layer 28, including both diffusion barrier 28 c and silicon layer 28 e, is present over silicon thin-film layer 26, 26′ at the desired thickness.
Upon completion of epitaxial layer 28, isolation structures may now be formed to separate the individual devices from one another. In this embodiment of the invention, as shown in
The remainder of PNP transistor 30, according to this first preferred embodiment of the invention, is now completed in the conventional manner, resulting in the structure of
In the active region of PNP transistor 30, intrinsic base region 32 is an n-type doped silicon or n-type silicon-germanium epitaxial layer disposed at the surface of collector region 10. Extrinsic base structures 34 are heavily doped n-type silicon regions surrounding intrinsic base region 32, with silicide-clad ohmic contacts at portions of their surface. Extrinsic emitter 36 is disposed at the surface of intrinsic base region 32 between extrinsic base structures 34. Extrinsic emitter 36 is a heavily doped p-type polysilicon structure, which serves as a source of p-type dopant that diffuses into intrinsic base region 32 to form the emitter of the device. The surface of extrinsic emitter 36 is also preferably silicide-clad.
Transistor 30 in this embodiment of the invention provides external collector, base, and emitter connections by way of tungsten contact plugs 42 c, 42 b, 42 e, respectively, each of which extend through overlying insulator layer 41 to corresponding metal conductors 44 c, 44 b, 44 e, respectively. Conductors 44 c, 44 b, 44 e route connections to the collector, base, and emitter, respectively, to and from other devices in the same integrated circuit as transistor 30.
According to this first preferred embodiment of the invention, the provision of diffusion barrier 28 c tends to confine the boron dopant of buried collector 26′ within the combination of buried collector region 26′ and diffusion barrier 28 c, inhibiting its diffusion into the overlying epitaxial layer that forms subcollector 28 e of PNP transistor 30. As noted above, the boron dopant within buried collector region 26′ will tend to diffuse during the high temperature steps of the formation of subcollector 28 e, the anneal to diffuse emitter dopant from emitter electrode 36 into base layer 32, and the like. According to this invention, however, it is believed that the carbon dopant in diffusion barrier 28 c reduces the number of interstitial locations that would otherwise be used by boron diffusing upward from buried collector region 26′. The boron dopant thus remains within diffusion barrier 28 c instead of diffusing upward into the more lightly-doped subcollector 28 e.
By controlling and limiting the diffusion from buried collector region 26′ via diffusion barrier 28 c, the subsequent high temperature processes can be optimized without the additional thermal budget constraint that would otherwise be present if updiffusion from buried collector 26′ were of concern. In addition, the thickness of the epitaxial layer forming subcollector 28 e can be more closely optimized for device speed and breakdown performance, because of the improved control of the location of the interface between the more lightly-doped subcollector 28 e and buried collector region 26′. The matching of similar transistors across the integrated circuit and among integrated circuits on the same wafer, which is particularly important in analog applications, is also contemplated to be facilitated by this invention, because any thermal variations across the wafer provide much less effect on the devices themselves.
This first preferred embodiment of the invention may also be used to advantage in complementary bipolar integrated circuits, as will now be described relative to
As shown in
Following the formation of this epitaxial layer, the construction of transistors 30 p, 30 n proceeds in much the manner as described above relative to
Transistors 30 p, 30 n of
Additional benefits are provided by the present invention when applied to complementary bipolar structures such as shown in
Various alternatives to this embodiment of the invention are also contemplated. One such alternative is the addition of a germanium buffer layer over the buried collector regions 26′, in addition to the carbon-bearing diffusion barriers 28 e. This germanium layer, which may be formed by the epitaxial deposition of SiGe, is contemplated to improve the quality of the epitaxial silicon formed thereover, and is also contemplated to further retard the diffusion of dopant into the epitaxial silicon.
Another alternative to this embodiment of the invention is based on the diffusion enhancing effect that carbon species have on arsenic dopant. It is known in the art that boron diffuses much more readily in silicon than does arsenic. However, while the carbon species is known to retard the diffusion of boron, carbon is known to enhance the diffusion of arsenic, and also antimony (also an n-type dopant). This enhancement is believed to be due to the creation of additional substitutional locations caused by the carbon as a dopant. According to this alternative realization, the carbon-bearing species is included in the epitaxial growth of silicon over a p-type buried layer doped with boron, and an n-type buried layer doped with arsenic. It is contemplated, according to this alternative, that the carbon source can be controlled during epitaxy to provide a carbon concentration that retards the diffusion of boron and enhances the diffusion of arsenic to such an extent that the resulting dopant concentration gradient of the two conductivity types is substantially equal. In this way, matching of the construction and characteristics of the complementary bipolar devices is contemplated to be facilitated according to this invention.
As is evident according to the description of these embodiments of the invention, the carbon-bearing diffusion barrier layer is formed in a blanket manner, by the epitaxial deposition of carbon-bearing silicon or silicon-germanium. Further adjustment and control of the diffusion of dopant from buried layers can be attained, according to the present invention, by forming the diffusion barrier layers only in selected regions, as will now be described in connection with additional alternative preferred embodiments of the invention.
Referring now to
Mask layer 52 is formed over the surface of silicon thin film layer 26 as shown in
Accordingly, as shown in
The diffusion barrier species to be implanted, according to this embodiment of the invention, is preferably a carbon-bearing species. Elemental carbon itself may be implanted, or alternatively a carbon-bearing material such as SiGeC may be implanted. The energy and dose of the carbon-bearing implant is selected, according to conventional implant design techniques and depending upon the species being implanted; in either case, however, the energy may be kept relatively low because the bulk of the implanted carbon-bearing material preferably resides at the upper surface of buried collector layer 26′, to prevent updiffusion of the dopant.
After the implant of the carbon-bearing species, construction of PNP transistor 50 p continues in similar manner as described above relative to
As shown in
According to this embodiment of the invention, therefore, the selective masked implant of the diffusion-retarding carbon-bearing species allows selection of those locations at which updfiffusion from the underlying buried layer is to be inhibited, and those locations at which such updiffusion is to be permitted. As shown in
The selective masking of the carbon-bearing implant can also be used to advantage in complementary bipolar structures, in particular to improve the matching of dopant diffusion between the transistors of different conductivity types.
Transistors 50 p, 50 n therefore have respective buried collector regions 26′p, 26′n, that consist of heavily doped portions of a silicon thin-film layer, each providing a low resistance path to the respective collector contacts 44 c. In this embodiment of the invention, buried collector region 26′n is heavily-doped with phosphorous or antimony, while buried collector region 26′p is boron-doped, as described above. As in the previously described examples, the doping of buried collector regions 26′ is performed by respective masked ion implant processes and subsequent anneals. The updiffusion of dopant from buried collector regions 26′n, 26′p is inhibited, at locations underlying the eventual emitter region, by way of a masked ion implant of a carbon-bearing species, as described above relative to
In this complementary bipolar realization, therefore, selective masked carbon-bearing species ion implantation provides good matching of the PNP and NPN devices to one another, without the differences that arise in conventional complementary devices due to the differential updiffusion of dopant from buried collector layers depending upon the dopant species. This matching is accomplished in this embodiment of the invention because the updiffusion in these “safe” areas facilitates the formation of collector contacts to the buried collector layers.
The concept of the masked implant of the carbon-bearing species may also be used to advantage in the formation of transistors of different electrical and performance characteristics, as will now be described relative to another alternative embodiment of the invention, relative to
As shown in
As shown in
The selective inhibition of dopant diffusion near the active emitter regions provide a differential performance characteristic for transistors 60HV, 60LV in this embodiment of the invention, even where transistors 60HV, 60LV are otherwise similarly constructed. Subcollector 68 of transistor 60HV is relatively thick, because of the carbon-bearing species implant that inhibits diffusion, and yields a high breakdown voltage for this device, rendering it suitable for use in high bias voltage applications. This high breakdown voltage comes at a cost of relatively high collector series resistance, however, because of the distance that current must travel through thick subcollector 68. Even in transistor 60HV, however, the masking of implant from portions of buried collector region 26′ at which collector sinker structure 33 is to be formed facilitates the making of a good, low resistance, collector contact away from the active region of the device.
On the other hand, because heavily doped regions 65 are formed by the updiffusion of dopant from buried collector region 26′ in transistor 60LV, the distance between the active region of the device and heavily doped region 65 (i.e., the thickness of its subcollector) is much shorter. Accordingly, transistor 60LV has a lower breakdown voltage than does transistor 60HV; however, this shorter distance of the current path before reaching heavily doped region 65 yields a lower series collector resistance for transistor 60LV. Transistor 60LV is therefore more suitable for high performance and high speed applications in which the bias voltages can be kept low.
According to each of the embodiments of this invention, as described above, numerous advantages are provided. The ability to control the diffusion of dopant from heavily doped buried layers, such as buried collectors in bipolar devices, provided by this invention permits improved control in the determination of the operating characteristics of these devices, and improved matching of device characteristics, especially in the complementary bipolar context. Pressure on the thermal budget arising from the problem of diffusion from buried layers is also relieved. Selective application of the diffusion retardant permits further control in the relative diffusion of dopant from buried layers also permits design flexibility in the fabrication of different transistors in the same integrated circuit, both in the context of complementary bipolar devices and also in the context of transistors having different tradeoffs between breakdown voltage and collector resistance.
It is also contemplated that the present invention may also be of benefit when applied to metal-oxide-semiconductor (MOS) transistors, either in a purely MOS integrated circuit, or in an integrated circuit that includes both bipolar and MOS devices (such as BiCMOS or CBiCMOS devices).
It is contemplated that many of the elements of transistor 70 may be made simultaneously with elements of bipolar transistor 20 described above. For example, plugs 42 in both transistors may be formed simultaneously. Emitter electrode 35 and gate electrode 75 may also be formed from the same polysilicon layer, with the difference that emitter electrode 35 is in contact with base layer 32 while gate electrode 75 is insulated from the underlying silicon. Additionally, p-well 28 e is effectively the same silicon layer as subcollector 28 e in bipolar transistor 20, and therefore is similarly doped and formed by way of epitaxy.
According to this embodiment of the invention, p-type buried collector region 26′ also resides under n-channel MOS transistor 70. While, in this MOS case, no transistor current is intended to be conducted by buried region 26′, the presence of a conductive ground plane beneath the channel region of an MOS device has been found to be beneficial. Such a ground plan ensures the proper body node bias, by providing a low-resistance body contact to a location that is directly in contact with the body node under the channel region. In addition, the ground plane provided by buried region 26′ also effects good shielding of the MOS device from noise generated elsewhere in the integrated circuit.
Also in this embodiment of the invention, diffusion barrier 28 c is present in transistor 70, overlying buried region 26′. Diffusion barrier 28 c is formed in the same manner, and at the same time, as for any bipolar devices in the same integrated circuit with transistor 70, either by way of a carbon-bearing source during epitaxy of p-well 28 e, or by way of a blanket or masked ion implantation. The presence of the carbon in diffusion barrier 28 c confines the dopant of buried region 26′, which in this case is boron, from updiffusing toward the channel of transistor 70. As a result, buried region 26′ serves as a conductive ground plane, and can be placed at a controlled depth below source and drain regions 26′. The tradeoff between leakage current and breakdown voltage, on the one hand, and proximity of buried region 26′ to the channel, on the other hand, can therefore be closely controlled according to this embodiment of the invention.
According to another embodiment of the invention, which is specifically directed to MOS transistors, the carbon-bearing diffusion barrier layer can be placed extremely close to the active regions of the device, as will now be described relative to transistor 80 of
Transistor 80 is an n-channel transistor, in which gate electrode 75 and the overlying connections thereto, and to the source and drain, are identical to that in the case of transistor 70 described above. According to this embodiment of the invention, however, transistor 80 is formed at a surface of p-well 86, which is a lightly-doped p-type region; p-well 86 may be an implanted diffused region of a bulk silicon wafer, a region in a silicon-on-insulator (SOI) device as described above, or further in the alternative may simply be the substrate on which the entire integrated circuit is formed. Super steep retrograde well 88 overlies p-well 86, in a manner that is confined between isolation structures 20. According to this embodiment of the invention, retrograde well 88 is also a p-type region, but has a super-steep retrograde dopant profile, in which the dopant concentration in well 88 increases steeply with increasing depth into the wafer. As is known in the art, retrograde wells such as well 88 are useful in improving electrical isolation among transistors in the same substrate.
According to this embodiment of the invention, diffusion barrier 85 is disposed at the surface of retrograde well 88. Diffusion barrier 85 is formed in the manner described above, either by way of including a carbon source during epitaxial growth of silicon or by way of a blanket or masked ion implantation. In this example, diffusion barrier 85 is extremely close to the surface of the structure, and in fact is within the region at which the source and drain junctions would otherwise extend so that the source and drain regions actually abut diffusion barrier 85 as shown in
According to these additional embodiments of the invention relative to MOS transistors, the benefits of diffusion barriers in the underlying single-crystal silicon include improved process control, and less pressure on thermal budget, as achieved with the bipolar transistors described above. In some cases, the present invention can result in improved device performance, as well.
While the present invention has been described according to its preferred embodiments, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives obtaining the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as subsequently claimed herein.