|Publication number||US20050259692 A1|
|Application number||US 10/849,692|
|Publication date||Nov 24, 2005|
|Filing date||May 19, 2004|
|Priority date||May 19, 2004|
|Also published as||US8305871, US20090103572, WO2005117325A2, WO2005117325A3|
|Publication number||10849692, 849692, US 2005/0259692 A1, US 2005/259692 A1, US 20050259692 A1, US 20050259692A1, US 2005259692 A1, US 2005259692A1, US-A1-20050259692, US-A1-2005259692, US2005/0259692A1, US2005/259692A1, US20050259692 A1, US20050259692A1, US2005259692 A1, US2005259692A1|
|Original Assignee||Zerbe Jared L|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (14), Referenced by (13), Classifications (4), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to the field of communications, and more particularly to noise abatement for high speed electronic signaling within and between integrated circuit devices.
Integrated circuits 125 communicate internally at very high speeds, tens of gigabits per second in some examples. The communication channels extending between integrated circuits 125 are comparatively slow, and consequently limit system speed performance. A considerable effort has been made to address this performance limitation.
System 100 of
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements.
Various embodiments of the present invention maybe employed to reduce the impact of crosstalk. Communication circuits in accordance with some embodiments adjust the timing of transitions of transmitted “aggressor” data to reduce, from the perspective of potential victim receivers, the effects of crosstalk. This adjustment of the transition timing moves the noise artifacts on the coupled victim channel away from sensitive regions in the victim data, and consequently reduces the effects of crosstalk on the victim data.
Some embodiments reduce the effects of crosstalk by introducing static timing offsets to one or a plurality of aggressor transmitters, one or a plurality of victim transmitters, or some combination of aggressor and victim transmitters. Other embodiments dynamically alter the relative timing of aggressor and victim transmitters.
Some high-performance communication systems employ receivers that capture data and the associated timing from the incoming data stream. Because such receivers recover the timing from the incoming signal, the receivers do not need a reference clock signal having a phase that is fixed in relation to the phase of the incoming signal. Communication systems in accordance with some embodiments can take advantage of this phase insensitivity by adjusting the phase of transmitted aggressor data to minimize the impact of crosstalk on data on potential victim channels. Adjusting the phase, as used herein, means adjusting the timing of the clock signal that times the transmission of data, and consequently adjusting the timing of the transmitted data transitions relative to potential victim data.
Transceiver 205 includes N-1 additional transmitters, though only the Nth transmitter 223 is shown. Transmitter 223, with an associated phase-adjust circuit 225, drives a respective second transmit signal TXDN to a corresponding receiver 233 of transceiver 210 via channel 215. The last communication channel 216 transmits data TXDM in the reverse direction, from a transmitter 235 with associated phase-adjust circuit 240 to a receiver 226 and associated phase tracking circuit 249. In an alternative embodiment, communication system 200 may comprise only one of the two links made up of the 223/215/233 link and the 235/216/226 link. In other alternative embodiments, communication system 200 may comprise one or more links in each direction.
Transmitter 218 and receiver 230 perceive different phases of system clock SysClk due to different propagation delays between the system clock source and the separate transceivers. This phase error does not pose a problem, however, as the receivers do not use the system clock to capture data, but instead use the system clock as a frequency reference and use standard clock and data recovery “CDR” techniques to generate local receive clock LRC1. An example of conventional receive circuitry that extracts timing and data from serial data is described below in connection with
The phase-adjust circuits associated with each transmitter alter the phase of the transmit clocks, and consequently the transmitted data, to reduce the impact of crosstalk. For illustrative purposes, channel 212 is assumed to be an aggressor channel that induces undesirable crosstalk into victim channels 215 and 216. Additional aggressor channels might also be included, and their separate or combined effects can exacerbate crosstalk problems. Additional aggressor channels are omitted here for ease of illustration.
System 200 addresses two distinct forms of crosstalk. The first, commonly referred to as “far-end crosstalk” (FEXT), is characterized by the crosstalk source being received at the same destination as the victim, and is illustrated by arrow 236. Signals switching on channel 212 cross-couple to channel 215 and are consequently perceived, at least in part, by receiver 233. The second form of crosstalk, commonly referred to as “near-end crosstalk” (NEXT), is characterized by the crosstalk source originating at the same location as the victim receiver, and is illustrated by an arrow 241. In that case, signals switching on channel 212 may cross-couple to channel 216 and may consequently be perceived, at least in part, by receiver 226.
The appropriate phase offsets can be established once or periodically, at power-up for example. An overall system approach can identify victim links by monitoring receiver bit-error rates. In one embodiment, one or more victim links are identified by determining which links have relatively high bit error rates. Links physically located near the victim link are identified and referred to as “likely aggressor links.” Likely aggressors can then be phase adjusted in the manner described above to minimize the bit-error rates of the victim receivers. Such an approach might focus on reducing the bit-error rate of the most noise-sensitive channels, or might attempt to minimize the bit-error rate for the entire system. Alternatively, collections of neighboring or related communication channels can be optimized in groups, as where the speed performance of a system depends heavily on a particular one or a subset of the communication channels. In another embodiment, a multi-variable optimization routine may be used to improve overall system performance. In one such embodiment, one or more victim links are identified by determining which links have relatively high bit error rates. The overall bit error rate of the system may also be determined. A number of likely aggressor links are identified, for example by physical proximity, and the timing of the data transmitted on these links is adjusted. The bit error rates of the individual victim channel, the overall system, or both are then recalculated. These steps are repeated until an optimal or acceptable per-channel or system-wide bit error rate is obtained.
The techniques described above in connection with the mesochronous system 200 of
The systems of
Receive section 407 is of a well-known type, and is thus not described in detail. In brief, receive section 407 includes a phase detector 425 and a sampler 411, each of which samples received data from channel 403. Phase detector 425 provides an output signal to a receiver phase controller 413, which controls the sample timing of the received signal via a phase mixer 415 that derives edge and data clocks EdClk and DaCLk by combining selected ones of a plurality of differently phased reference clocks from PLL 409. Sampler 411, thus properly timed, samples the incoming data and provides the resulting sampled data to a deserializer 422 for conversion to parallel input data InData.
Transmit section 405 is largely conventional, but is modified in accordance with one embodiment to allow for one-time, periodic, or continuous variation in the timing of the transmit clock TxClk. Transmit section 405 conventionally includes a resynchronizer 420 that re-times parallel transmit data TxData timed to a local clock LClk to transmit clock TxClk. The resulting re-timed parallel data TxDr is then fed to a serializer 423. Serial transmit data TxDs from serializer 423 is then conveyed to a transmitter 426 for transmission over channel 402. In one embodiment, resynchronizer 420 is of a type described in U.S. patent application Ser. No. 10/282,531 entitled “Method and Apparatus for Fail-Safe Resynchronization with Minimum Latency,” which is incorporated herein by reference.
In addition to the foregoing conventional components, transmit section 405 includes a transmit phase mixer 430 controlled by transmit phase-control circuitry 435. Phase-control circuitry 435 may be a simple volatile or non-volatile register, in one embodiment, that can be loaded with different counts to adjust the phase of transmit clock TxClk. As discussed in connection with
Of interest, some conventional transceivers similar to the one of
As noted above in connection with
In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the various depicted embodiments. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, the interconnection between circuit elements or circuit blocks may be shown or described as multi-conductor or single conductor signal lines. Each of the multi-conductor signal lines may alternatively be single-conductor signal lines, and each of the single-conductor signal lines may alternatively be multi-conductor signal lines. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments.
While the present invention has been described in connection with specific embodiments, variations of these embodiments will be obvious to those of ordinary skill in the art. For example, while the foregoing embodiments reduce crosstalk in channels that extend between integrated circuits (ICs), the methods and circuits described herein can be adapted to reduce intra-IC crosstalk. Further, the timing of both the leading and trailing edges of transmitted data may be independently adjusted in some embodiments to reduce crosstalk effects. And, in still other embodiments, the crosstalk minimization schemes described herein are applied to asynchronous systems. Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection, or “coupling,” establishes some desired electrical communication between two or more circuit nodes, or terminals. Such coupling may often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims specifically reciting “means for” or “step for” should be construed in the manner required under the sixth paragraph of 35 U.S.C. Section 112.
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|May 19, 2004||AS||Assignment|
Owner name: RAMBUS INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ZERBE, JARED L.;REEL/FRAME:015384/0582
Effective date: 20040518