US 20050263870 A1
A slotted file is created by connecting two side walls and a back wall. The side walls have etched grooves facing directly across from each other. The platelet has flanges that fit into the grooves. In one embodiment, a completed cube is formed when the platelets fill the slotted file.
1. A system for stacking platelets, comprising in combination:
a slotted file; and
a plurality of platelets which fit into the slotted file.
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20. A method for stacking platelets, comprising in combination:
etching grooves into a wall material, wherein at least two side walls with a plurality of grooves and at least one back wall without the grooves is formed;
connecting the at least two side walls and the at least one back wall to form a slotted file; and
inserting a plurality of platelets into the slotted file forming a completed cube.
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29. A system for stacking platelets, comprising in combination:
a slotted file consisting of at least two side walls and at least one back wall, wherein the at least two side walls and the at least one back wall are composed of silicon, wherein the at least two side walls have been etched with a plurality of grooves, wherein the at least one back wall is connected to an end of each of the at least two side walls to form a “U” shape, and wherein the plurality of grooves on the at least two side walls face directly across from each other; and
a plurality of platelets, wherein each of the plurality of platelets is comprised of a semiconductor chip placed into a chip carrier, wherein the chip carrier has a floor and a frame, wherein the floor and the frame are composed of a ceramic material, wherein the floor protrudes past at least two edges of the frame forming flanges, wherein the flanges fit into the plurality of grooves in the at least two side walls of the slotted file, and wherein epoxy is used to seal a completed cube.
The United States Government has acquired certain rights in this invention pursuant to Contract No. DASG60-90-C-0136 awarded by the U.S. Army.
The present invention relates generally to circuit packages, and more particularly, relates to three-dimensional circuit packages that provide stacking for semiconductor platelets.
Three-dimensional integrated circuits are employed in applications in which space is a critical design factor. As the demand for more functionality in less space increases, so does the number of designs using three-dimensional packaging. In addition to the benefit of reducing space, these designs may also realize higher speeds because interconnects between circuit components may be shorter.
Memory stacking was the first application of three-dimensional packaging, but now applications range from stacking memory modules to stacking entire systems. Different layers in the stack may have different functionalities. For example, one layer may be a memory layer and another may be a logic layer. It is also possible that the different layers in the stack could have different dimensions.
These applications may require the precise stacking of very thin platelets into cubes. Platelets may consist of a semiconductor chip placed in a chip carrier. The platelets themselves may be less than 5 mils thick and there may be as many as sixty platelets stacked in one cube. It is critical that the spacing between the platelets is held to a very tight tolerance and that the platelets are not damaged during the stacking procedure.
Typically, the platelets are held in the cubical stack by a very thin layer of epoxy resin between each layer. This epoxy layer may be less than one micron thick. Other bonding materials, such as silicone rubber or eutectic solder alloy, may also be employed. The required spacing dimensions may be maintained by using an apparatus with a calibrated compression arm that applies pressure to the stack while the epoxy is setting. A typical amount of pressure may be ten Newtons of force. With this arrangement, only the overall cube dimensions can be maintained, and great care must be taken to prevent cracking the delicate platelets by excessive pressure. The critical layer to layer spacing is thus a derived property and is based upon the uniformity of the thickness and pressure-flow characteristics of the adhesive layer.
It would be desirable to provide a stacking method that provides a very tight spacing tolerance between the platelets and that minimizes damage to the platelets during the stacking process. The invention addresses current limitations and makes the critical spacing a directly controlled property resulting in much higher accuracy potential with a relative independence of the adhesive layers.
In accordance with this invention, a method for stacking semiconductor platelets in a three-dimensional circuit package is described. Three walls are connected to form a slotted file. The two side walls have grooves. The grooves on the two walls face directly across from each other. Placing a semiconductor chip into a frame of a chip carrier forms a platelet. The frame is located on the surface of a floor of the chip carrier. The floor protrudes past the sides of the frame forming flanges on each side of the frame. The flanges fit into the groves of the slotted file. The platelets are then inserted into the slotted file forming a completed cube.
Preferred embodiments are described below in conjunction with the appended drawing figures, wherein like reference numerals refer to like elements in the various figures, and wherein:
The frame 104 is positioned in the center of the floor 102. Because the width of the floor 102 is greater than the width of the frame 104, the floor 102 protrudes past the edges of the frame 104 forming two flanges 106, one on either side of the frame 104.
In an exemplary embodiment both the floor 102 and the frame 104 are formed with ceramic materials, but other materials such as metal and plastic may be used. The floor 102 contains a plurality of electrodes. The frame 104 has interior dimensions slightly larger than those of the semiconductor chip 108. The interior dimensions of the frame 104 may vary to accommodate a variety of different semiconductor chip 108 dimensions. The semiconductor chip 108 may be placed in the frame 104 face down on the floor 102 contacting the plurality of electrodes at the appropriate circuit interfaces to form a platelet 404 (see
The wall material 202 may be etched with grooves 204 deep enough to receive the flanges 106 of a chip carrier 100 and less than the thickness of the wall material 202. For example, the depth of the grooves may be less than 10 mils thick. The spacing between the grooves 204 may be selected based on design requirements, such as the thickness of the platelets 404, the number of platelets 404 in a completed cube 500, and an allocated space limitation (see
The back wall 304 may be connected to an end of each of the two side walls 302 to form a “U” shape. The grooves 204 on the two side walls 302 face directly across from each other. The three walls 302, 304 may be joined together by conventional methods to form a slotted file 300. For example, an etching process in which tabs and holes are created to join the walls may be employed.
It should be understood that the illustrated embodiments are exemplary only, and should not be taken as limiting the scope of the present invention.