Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20050269720 A1
Publication typeApplication
Application numberUS 11/141,859
Publication dateDec 8, 2005
Filing dateJun 1, 2005
Priority dateJun 3, 2004
Also published asUS7508052
Publication number11141859, 141859, US 2005/0269720 A1, US 2005/269720 A1, US 20050269720 A1, US 20050269720A1, US 2005269720 A1, US 2005269720A1, US-A1-20050269720, US-A1-2005269720, US2005/0269720A1, US2005/269720A1, US20050269720 A1, US20050269720A1, US2005269720 A1, US2005269720A1
InventorsHugo Burke, Aram Arzumanian
Original AssigneeInternational Rectifier Corp.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Crack protection for silicon die
US 20050269720 A1
Abstract
A wafer containing a plurality of die separated by streets which are to be sawn has a nitride passivation layer which has openings over die contact locations and gaps leaving nitride strips along the streets. The gaps in the nitride along the streets expose an oxide, preferably TEOS. A nickel/gold plate contact material overlies the nitride layer and contacts the exposed die contact areas but does not adhere to either the nitride surface or the oxide surfaces. A saw blade can then cut along the streets without being gummed by the metalizing and without producing cracks which propagate into the die termination areas.
Images(3)
Previous page
Next page
Claims(11)
1. A wafer of semiconductor material having a plurality of identical laterally spaced die areas thereon which are surrounded by streets to be sawn to separate the die; said wafer having a surface passivation layer of nitride thereon; said nitride layer having openings therethrough at locations of electrodes on said die to permit the formation of contacts to said electrodes, said nitride layer having spaced parallel gaps on the borders of said streets to leave a strip of nitride over each of said streets; each of said gaps having an oxide layer therein which borders said nitride strips; whereby said streets can be sawn to singulate said die without propagation of cracks into the termination areas of said die.
2. The wafer of claim 1, wherein said semiconductor material is monocrystaline silicon.
3. The wafer of claim 1, wherein said passivation layer is Si3 N4.
4. The wafer of claim 1, wherein said oxide layers are TEOS.
5. The wafer of claim 1, wherein said electrodes receive a nickel/gold plating.
6. The wafer of claim 2, wherein said passivation layer is Si3 N4.
7. The wafer of claim 6, wherein said oxide coating is TEOS.
8. The wafer of claim 7, wherein said electrodes are a nickel/gold plating.
9. The process of singulating adjoining semiconductor die from one another; said process comprising the steps of forming a nitride layer over said adjoining die, forming gaps in said nitride layer over a street area, between said adjoining die to form an isolated strip of nitride over the street area, and removing nitride areas from the electrode areas of said die; defining oxide layers in said gaps in said nitride layer, which oxide layers are in direct contact with the surface of said die at said street area; plating a contact material over said adjoining die which does not adhere to nitride or oxide; and sawing through said street area to separate said die without gumming the saw blade and without propagating cracks into termination areas said die.
10. The process of claim 9, wherein said contact material is a nickel/gold plate.
11. The process of claim 9, wherein said nitride is Si3 N4 and said oxide is TEOS.
Description
    RELATED APPLICATIONS
  • [0001]
    This application claims the benefit of U.S. Provisional Application No. 60/576,701, filed Jun. 3, 2004.
  • FIELD OF THE INVENTION
  • [0002]
    This invention relates to silicon wafer processing and more specifically relates to a wafer structure and process to prevent cracking of the die when they are singulated, or separated from the wafer.
  • BACKGROUND OF THE INVENTION
  • [0003]
    In the manufacture of semiconductor die such as diodes or MOSFETs or the like, the die structures are completed to the extent possible in a common wafer and are then singulated (separated) as by sawing in a scribe area (“streets”) between and circumscribing adjacent die.
  • [0004]
    In many semiconductor device products, such as the Flip Fet™ flip chip MOSFET of U.S. Pat. No. 6,653,740 which is owned by the assignee of the present invention, the die are not packaged and need to be otherwise passivated from ambient.
  • [0005]
    For that purpose, and while the die are still in the wafer a silicon nitride (Si3 N4) layer about 1.2 microns thick is applied to the wafer surface after the front metal has been applied to the die in the wafer. A PECVD process is conventionally used to deposit the nitride layer. The nitride passivation layer was then subjected to a photolithography step in which a mask was processed and opened only to expose the scribe lines which circumscribe each of the die and the contact regions to which contacts (for contact balls in the case of the device of U.S. Pat. No. 6,653,740) are to be formed on the passivated die.
  • [0006]
    After masking, the exposed nitride areas are dry-etched and the photoresist was stripped.
  • [0007]
    To then prepare the surface for solder ball formation, the first step was an electroless Ni/Au plating step over the full wafer surface. The plating adheres only to the exposed areas opened in the passivation layer so that the scribe lines were also plated along with the solder ball electrode pads.
  • [0008]
    As a result, during dicing or singulation of the die from the wafer, the saw blade became clogged or gummed up by the Ni/Au plate layer.
  • [0009]
    In an attempt to solve this problem, an oxide (TEOS) film (the surface of the wafer has an overlying TEOS layer beneath the nitride passivation) was left on the streets (after the etch of the nitride). This protected the streets from plating of Ni/Au, but a new problem was created. Thus, the TEOS film was cracking during dicing, with some cracks propagating into the die termination areas.
  • [0010]
    To solve this problem, the TEOS was removed from the street and a street protection photoresist mask was added to protect the streets from plating. This mask was then stripped with hot sulfuric acid after the plating operation. However, with this process, some of the exposed metals of the wafer were also etched, and the additional photo steps added cost to the process.
  • BRIEF DESCRIPTION OF THE INVENTION
  • [0011]
    In accordance with the invention, the nitride passivation over the streets is bordered on each side by oxide strips which interrupt and underlie and segregate a nitride strip over the street.
  • [0012]
    Thus, the nitride strip over the street prevents the deposit of the Ni/Au plate (or some other contact layer), and cracks in the nitride due to sawing propagate through the nitride but stop at the oxide border strips and do not go into the die termination areas.
  • [0013]
    One process to accomplish the boarder oxide strips employs a slight change in the contact mask which leaves spaced narrow (10 micron wide) oxide strips on each side of the street area unetched. The nitride passivation layer is then etched off the tops of the border oxide strips, leaving about a 6 micron wide opening over the 10 micron wide oxide strips. Thus, the nitride passivation is non-continuous, but protects the silicon in the street from being plated by the Ni/Au plating.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0014]
    FIG. 1 is a top view of a wafer containing plural identical die which are simultaneously processed to contain any desired junction pattern and electrode structure.
  • [0015]
    FIG. 2 is a cross-section of the street between adjacent die which is to be scribed or sawn to separate (or singulate) the die.
  • [0016]
    FIG. 3 is a top view of FIG. 2.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • [0017]
    FIG. 1 shows a conventional wafer after a plurality of identical die, which may be transistors, diodes, or the like, have been fully processed, and the die are ready to be singulated as by a saw cut through the streets 10 through 14 which circumscribe the die. Note that each of the die are shown as having contact bumps such as bumps 20, 21, 22 and 23 which are connected to various die electrodes which have been formed in the wafer during manufacturing stage. Such die may be Flip Fet die of the type shown in U.S. Pat. No. 6,653,740 (IR-1696) which is incorporated herein in its entirety, by reference.
  • [0018]
    FIG. 2 is a cross-section of a termination area and street area of two adjacent die in FIG. 1, identified roughly by the circled area labeled “FIG. 2” in FIG. 1. The wafer has an N+ body 30 (any conductivity type can be used) with a junction-receiving N epitaxially grown layer 31 thereon. The junction pattern and electrodes connected thereto can take any desired form and are not shown in FIG. 2, but can be those shown in U.S. Pat. No. 6,653,740 previously identified.
  • [0019]
    The termination shown includes polysilicon field plate layers 35 and 36. These are not critical to the invention.
  • [0020]
    The full wafer is passivated by a nitride (Si3 N4) layer 40 which is opened in areas of the device to be metallized. Thus, in order to attach the solder balls 20 to 23 in FIG. 1, a nickel gold layer is first deposited on the die electrodes through windows in the nitride layer (shown in dotted lines in FIG. 1). The nitride layer 40 is left in place over the termination area to prevent plating of the metal in this area which would gum up the saw blade. However, the nitride, which will not gum the blade, has been found to propagate cracks into the die termination areas during sawing.
  • [0021]
    In accordance with the invention, the nitride layer 40 is removed at narrow elongated gaps 42 and 43 which border a central nitride strip 40 a (FIG. 2). The gaps 42 and 43 contain elongated oxide (TEOS) strips 50 and 51, respectively. The TEOS strips 50 and 51 may be portions of a TEOS layer over the full wafer which is etched during the contact etch to expose windows for connection of balls 20 to 23. The strips 50 and 51 can be left in place by a simple change in the contact mask.
  • [0022]
    Note that the oxide layers 50 an 51 may have a width of about 10 microns and may be overlapped along their edges by the nitride layer. The gaps in the nitride may be about 6 microns wide.
  • [0023]
    When the Ni/Au electroless plate layer is now applied, it will not adhere to any of the oxide or nitride surfaces in the street area of FIG. 2. Thus, the die can be sawn along the center of nitride strip 40 (without clogging the saw blade) and cracks which may propagate from nitride layer 40 a will not propagate past the oxide border strips 50 and 51 and into the die terminations.
  • [0024]
    Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5024970 *Dec 5, 1989Jun 18, 1991Mitsubishi Denki Kabushiki KaishaMethod of obtaining semiconductor chips
US5844304 *Sep 25, 1995Dec 1, 1998Nec CorporationProcess for manufacturing semiconductor device and semiconductor wafer
US6365958 *Jan 21, 1999Apr 2, 2002Texas Instruments IncorporatedSacrificial structures for arresting insulator cracks in semiconductor devices
US20030100143 *Nov 28, 2001May 29, 2003Mulligan Rose A.Forming defect prevention trenches in dicing streets
US20050116333 *Mar 24, 2004Jun 2, 2005Kazutaka AkiyamaSemiconductor device and semiconductor device manufacturing method
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7741196Jan 29, 2007Jun 22, 2010Freescale Semiconductor, Inc.Semiconductor wafer with improved crack protection
US20080179710 *Jan 29, 2007Jul 31, 2008Heng Keong YipSemiconductor wafer with improved crack protection
Classifications
U.S. Classification257/797, 257/E23.179, 257/E21.599, 257/E23.194, 438/460, 257/E23.12, 257/E21.508
International ClassificationH01L21/60, H01L21/46, H01L21/44, H01L23/29, H01L21/78, H01L23/00, H01L23/544, H01L21/48, H01L23/58, H01L21/50, H01L21/301
Cooperative ClassificationH01L2924/01033, H01L2924/13091, H01L2924/01078, H01L2924/01077, H01L2924/10253, H01L23/562, H01L23/296, H01L21/78, H01L2224/13099, H01L23/544, H01L23/585, H01L2924/014, H01L24/11, H01L2924/01079
European ClassificationH01L24/11, H01L23/562, H01L23/544, H01L23/58B, H01L21/78, H01L23/29P6
Legal Events
DateCodeEventDescription
Jun 1, 2005ASAssignment
Owner name: INTERNATIONAL RECTIFIER CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BURKE, HUGO;ARZUMANYAN, ARAM;REEL/FRAME:016634/0417
Effective date: 20050601
Sep 24, 2012FPAYFee payment
Year of fee payment: 4