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Publication numberUS20050278513 A1
Publication typeApplication
Application numberUS 11/132,423
Publication dateDec 15, 2005
Filing dateMay 19, 2005
Priority dateMay 19, 2004
Also published asCN101002169A, US8719837, US9003422, US20050273559, US20050278505, US20050278517, US20050289321, US20050289323, US20140208087, WO2005114441A2, WO2005114441A3
Publication number11132423, 132423, US 2005/0278513 A1, US 2005/278513 A1, US 20050278513 A1, US 20050278513A1, US 2005278513 A1, US 2005278513A1, US-A1-20050278513, US-A1-2005278513, US2005/0278513A1, US2005/278513A1, US20050278513 A1, US20050278513A1, US2005278513 A1, US2005278513A1
InventorsAris Aristodemou, Rich Fuhler, Kar-Lik Wong
Original AssigneeAris Aristodemou, Rich Fuhler, Kar-Lik Wong
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Systems and methods of dynamic branch prediction in a microprocessor
US 20050278513 A1
Abstract
A hybrid branch prediction scheme for a multi-stage pipelined microprocessor that combines features of static and dynamic branch prediction to reduce complexity and enhance performance over conventional branch prediction techniques. Prior to microprocessor deployment, a branch prediction table is populated using static branch prediction techniques by executing instructions analogous to those to be executed during microprocessor deployment. The branch prediction table is stored, and then loaded into the BPU during deployment, for example, at the time of microprocessor power on. Dynamic branch prediction is then performed using the pre-loaded data, thereby enabling dynamic branch prediction with a required “warm-up” period. After resolving each branch in the selection stage of the microprocessor instruction pipeline, the BPU is updated with the address of the next instruction that resulted from that branch to enhance performance.
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Claims(22)
1. A method of performing branch prediction in a microprocessor having a multistage instruction pipeline, the method comprising:
building a branch prediction history table of branch prediction data through static branch prediction prior to microprocessor deployment;
storing the branch prediction data in a memory;
loading the branch prediction data into a branch prediction unit (BPU) of the microprocessor upon power on; and
performing dynamic branch prediction with the BPU based on the preloaded branch prediction data.
2. The method according to claim 1, further comprising updating the branch prediction data in the BPU if, during instruction processing, prediction data changes.
3. The method according to claim 2 wherein updating comprises after resolving a branch in a select stage of the instruction pipeline, updating the BPU with the address of a next instruction that resulted from that branch.
4. The method according to claim 1, wherein building a branch prediction history table comprises simulating instructions that will be executed by the processor during deployment and populating a table of branch history with information indicating whether conditional branches were taken or not.
5. The method according to claim 4, wherein building comprises using at least one of a simulator and a compiler to generate branch history.
6. The method according to claim 1, wherein performing dynamic branch prediction with the branch prediction unit based on the preloaded branch prediction data comprises parsing a branch history table in the BPU that indexes non-sequential instructions by their addresses in association with the next instruction taken.
7. The method according to claim 1, wherein the microprocessor is an embedded microprocessor.
8. The method according to claim 1, further comprising after performing dynamic branch prediction, storing branch history data in the branch prediction unit in a non-volatile memory for preload upon subsequent microprocessor use.
9. In a multistage pipeline microprocessor employing dynamic branch prediction, the method of enhancing branch prediction performance comprising:
performing static branch prediction to build a branch prediction history table of branch prediction data prior to microprocessor deployment;
storing the branch prediction history table in a memory;
loading the branch prediction history table into a branch prediction unit (BPU) of the microprocessor; and
performing dynamic branch prediction with the BPU based on the preloaded branch prediction data.
10. The method according to claim 9, wherein static branch prediction is performed prior to microprocessor deployment.
11. The method according to claim 9, wherein loading the branch prediction table is performed subsequent to microprocessor power on.
12. The method according to claim 9, further comprising updating the branch prediction data in the BPU if, during instruction processing, prediction data changes.
13. The method according to claim 12, wherein the microprocessor includes an instruction pipeline having a select stage, and updating comprises after resolving a branch in the select stage, updating the BPU with the address of the next instruction resulting from that branch.
14. The method according to claim 9, wherein building a branch prediction history table comprises simulating instructions that will be executed by the processor during deployment and populating a table of branch history with information indicating whether conditional branches were taken or not.
15. The method according to claim 14, wherein building comprises using at least one of a simulator and a compiler to generate branch history.
16. The method according to claim 9, wherein performing dynamic branch prediction with the branch prediction unit based on the preloaded branch prediction data comprises parsing a branch history table in the BPU that indexes non-sequential instructions by their addresses in association with the next instruction taken.
17. The method according to claim 9, wherein the microprocessor is an embedded microprocessor.
18. The method according to claim 9, further comprising after performing dynamic branch prediction, storing branch history data in the branch prediction unit in a non-volatile memory for preload upon subsequent microprocessor use
19. An embedded microprocessor comprising:
a multistage instruction pipeline; and
a BPU adapted to perform dynamic branch prediction, wherein the BPU is preloaded with branch history table created through static branch prediction, and subsequently updated to contain the actual address of the next instruction that resulted from that branch during dynamic branch prediction.
20. The microprocessor according to claim 19, wherein the branch history table contains data generated prior to microprocessor deployment and the BPU is preloaded at power on of the microprocessor.
21. The microprocessor according to claim 19, wherein after resolving a branch in a select stage of the instruction pipeline, the BPU is updated to contain the address of the next instruction that resulted from that branch.
22. The microprocessor according to claim 19, wherein the BPU is preloaded with a branch history table created through static branch prediction during a simulation processing that simulated instructions that will be executed by the microprocessor during deployment and wherein the BPU comprises a branch history table that indexes non-sequential instructions by their addresses in association with the next instruction taken.
Description
    CROSS REFERENCE TO RELATED APPLICATION(S)
  • [0001]
    This application claims priority to provisional application No. 60/572,238 filed May 19, 2004, entitled “Microprocessor Architecture” hereby incorporated by reference in its entirety.
  • FIELD OF THE INVENTION
  • [0002]
    This invention relates generally to microprocessor architecture and more specifically to improved systems and methods for performing branch prediction in a multi-stage pipelined microprocessor.
  • BACKGROUND OF THE INVENTION
  • [0003]
    Multistage pipeline microprocessor architecture is known in the art. A typical microprocessor pipeline consists of several stages of instruction handling hardware, wherein each rising pulse of a clock signal propagates instructions one stage further in the pipeline. Although the clock speed dictates the number of clock signals and therefore pipeline propagations per second, the effective operational speed of the processor is dependent partially upon the rate that instructions and operands are transferred between memory and the processor.
  • [0004]
    One method of increasing processor performance is branch prediction. Branch prediction uses instruction history to predict whether a branch or non-sequential instruction will be taken. Branch or non-sequential instructions are processor instructions that require a jump to a non-sequential memory address if a condition is satisfied. When an instruction is retrieved or fetched, if the instruction is a conditional branch, the result of the conditional branch, that is, the address of the next instruction to be executed following the conditional branch, is speculatively predicted based on past branch history. This predictive or speculative result is injected into the pipeline by referencing a branch history table. Whether or not the prediction is correct will not be known until a later stage of the pipeline. However, if the prediction is correct, several clock cycles will be saved by not having to go back to get the next non-sequential instruction address.
  • [0005]
    If the prediction is incorrect, the current pipeline behind the stage in which the prediction is determined to be incorrect must be flushed and the correct branch inserted back in the first stage. This may seem like a severe penalty in the event of an incorrect prediction because it results in the same number of clock cycles as if no branch prediction were used. However, in applications where small loops are repeated many times, such as applications typically implemented with embedded processors, branch prediction has a sufficiently high success rate that the benefits associated with correct predictions outweigh the cost of occasional incorrect predictions—i.e., pipeline flush. In these types of embedded applications branch prediction can achieve accuracy over ninety percent of the time. Thus, the risk of predicting an incorrect branch resulting in a pipeline flush is outweighed by the benefit of saved clock cycles.
  • [0006]
    There are essentially two techniques for implementing branch prediction. The first, dynamic branch prediction, records runtime program flow behavior in order to establish a history that can be used at the front of the pipeline to predict future non-sequential program flow. When a branch instruction comes in, the look up table is referenced for the address of the next instruction which is then predictively injected into the pipeline. Once the look up table is populated with a sufficient amount of data, dynamic branch prediction significantly increases performance. However, this technique is initially ineffective, and can even reduce system performance until a sufficient number of instructions have been processed to fill the branch history tables. Because of the required “warm-up” period for this technique to become effective, runtime behavior of critical code could become unpredictable making it unacceptable for certain embedded applications. Moreover, as noted above, mistaken branch predictions result in a flush of the entire pipeline wasting clock cycles and retarding performance.
  • [0007]
    The other primary branch prediction technique is static branch prediction. Static branch prediction uses profiling techniques to guide the complier to generate special branch instructions. These special branch instructions typically include hints to guide the processor to perform speculative branch prediction earlier in the pipeline when not all information required for branch resolution is yet available. However, a disadvantage of static branch prediction techniques is that they typically complicate the processor pipeline design because speculative as well as actual branch resolution has to be performed in several pipeline stages. Complication of design translates to increased silicon footprint and higher cost. Static branch prediction techniques can yield accurate results but they cannot cope with variation of run-time conditions. Therefore, static branch prediction also suffers from limitations which reduce its appeal for critical embedded applications.
  • [0008]
    Thus, it would be desirable to have a branch prediction technique that ameliorates and ideally eliminates one or more of the above-noted deficiencies of conventional branch prediction techniques. However, it should be appreciated that the description herein of various advantages and disadvantages associated with known apparatus, methods, and materials is not intended to limit the scope of the invention to their exclusion. Indeed, various embodiments of the invention may include one or more of the known apparatus, methods, and materials without suffering from their disadvantages.
  • [0009]
    As background to the techniques discussed herein, the following references are incorporated herein by reference: U.S. Pat. No. 6,862,563 issued Mar. 1, 2005 entitled “Method And Apparatus For Managing The Configuration And Functionality Of A Semiconductor Design” (Hakewill et al.); U.S. Ser. No. 10/423,745 filed Apr. 25, 2003, entitled “Apparatus and Method for Managing Integrated Circuit Designs”; and U.S. Ser. No. 10/651,560 filed Aug. 29, 2003, entitled “Improved Computerized Extension Apparatus and Methods”, all assigned to the assignee of the present invention.
  • SUMMARY OF THE INVENTION
  • [0010]
    Various embodiments of the invention may ameliorate or overcome one or more of the shortcomings of conventional branch prediction techniques through a hybrid branch prediction technique that takes advantage of features of both static and dynamic branch prediction.
  • [0011]
    At least one exemplary embodiment of the invention may provide a method of performing branch prediction in a microprocessor having a multi-stage instruction pipeline. The method of performing branch prediction according to this embodiment comprises building a branch prediction history table of branch prediction data through static branch prediction prior to microprocessor deployment, storing the branch prediction data in a memory in the microprocessor, loading the branch prediction data into a branch prediction unit (BPU) of the microprocessor upon powering on, and performing dynamic branch prediction with the BPU based on the preloaded branch prediction data.
  • [0012]
    At least one additional exemplary embodiment of the invention may provide a method of enhancing branch prediction performance of a multi-stage pipelined microprocessor employing dynamic branch prediction. The method of enhancing branch prediction performance according to this embodiment comprises performing static branch prediction to build a branch prediction history table of branch prediction data prior to microprocessor deployment, storing the branch prediction history table in a memory in the microprocessor, loading the branch prediction history table into a branch prediction unit (BPU) of the microprocessor, and performing dynamic branch prediction with the BPU based on the preloaded branch prediction data.
  • [0013]
    Yet an additional exemplary embodiment of the invention may provide an embedded microprocessor architecture. The embedded microprocessor architecture according to this embodiment comprises a multi-stage instruction pipeline, and a BPU adapted to perform dynamic branch prediction, wherein the BPU is preloaded with branch history table created through static branch prediction, and subsequently updated to contain the actual address of the next instructed that resulted from that branch during dynamic branch prediction.
  • [0014]
    Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0015]
    FIG. 1 is a block diagram illustrating a multistage instruction pipeline of a conventional microprocessor core;
  • [0016]
    FIG. 2 is a flow chart illustrating the steps of a method for performing dynamic branch prediction based on preloaded static branch prediction data in accordance with at least one exemplary embodiment of the invention; and
  • [0017]
    FIG. 3 is a block diagram illustrating the flow of data into and out of a branch prediction unit in accordance with at least one exemplary embodiment of the invention.
  • DETAILED DESCRIPTION OF THE DISCLOSURE
  • [0018]
    The following description is intended to convey a thorough understanding of the invention by providing specific embodiments and details involving various aspects of a new and useful microprocessor architecture. It is understood, however, that the invention is not limited to these specific embodiments and details, which are exemplary only. It further is understood that one possessing ordinary skill in the art, in light of known systems and methods, would appreciate the use of the invention for its intended purposes and benefits in any number of alternative embodiments, depending upon specific design and other needs.
  • [0019]
    FIG. 1 illustrates a typical microprocessor core 100 with a multistage instruction pipeline. The first stage of the microprocessor core 100 is the instruction fetch stage (FET) 110. In the instruction fetch stage 110, instructions are retrieved or fetched from instruction RAM 170 based on their N-bit instruction address. During instruction fetches, a copy of the instruction, indexed by its address, will be stored in the instruction cache 112. As a result, future calls to the same instruction may be retrieved from the instruction cache 112, rather than the relatively slower instruction RAM 170.
  • [0020]
    Another typical component of the fetch stage 110 of a multi-stage pipelined microprocessor is the branch prediction unit (BPU) 114. The branch prediction unit 114 increases processing speed by predicting whether a branch to a non-sequential instruction will be taken based upon past instruction processing history. The BPU 114 contains a branch look-up or prediction table that stores the address of branch instructions and an indication as to whether the branch was taken. Thus, when a branch instruction is fetched, the look-up table is referenced to make a prediction as to the address of the next instruction. As discussed herein, whether or not the prediction is correct will not be known until a later stage of the pipeline. In the example shown in FIG. 1, it will not be known until the sixth stage of the pipeline.
  • [0021]
    With continued reference to FIG. 1, the next stage of the typical microprocessor core instruction pipeline is the instruction decode stage (DEC) 120, where the actual instruction is decoded into machine language for the processor to interpret. If the instruction involves a branch or a jump, the target address is generated. Next, in stage (REG) 130, any required operands are read from the register file. Then, in stage (EXEC) 140, the particular instruction is executed by the appropriate unit. Typical execute stage units include a floating point unit 143, a multiplier unit 144, an arithmetic unit 145, a shifter 146, a logical unit 147 and an adder unit 148. The result of the execute stage 140 is selected in the select stage (SEL) 150 and finally, this data is written back to the register file by the write back stage (WB) 160. The instruction pipeline increments with each clock cycle.
  • [0022]
    Referring now to FIG. 2, a flow chart illustrating the steps of a method for performing dynamic branch prediction based on preloaded static branch prediction data in accordance with at least one exemplary embodiment of this invention is illustrated. As discussed above, dynamic branch prediction is a technique often employed to increase pipeline performance when software instructions lead to a non-sequential program flow. The problem arises because instructions are sequentially fed into the pipeline, but are not executed until later stages of the pipeline. Thus, the decision as to whether a non-sequential program flow (hereinafter also referred to as a branch) is to be taken or not, is not resolved until the end of the pipeline, but the related decision of which address to use to fetch the next instruction is required at the front of the pipeline. In the absence of branch prediction, the fetch stage would then have to fetch the next instruction after the branch is resolved leaving all stages of the pipeline between the resolution stage and the fetch stage unused. This is an undesired hindrance to performance. As a result, the choice as to which instruction to fetch next is made speculatively or predictively based on historical performance. A branch history table is used in the branch prediction unit (BPU) which indexes non-sequential instructions by their addresses in association with the next instruction taken. After resolving a branch in the select stage of the pipeline, the BPU is updated with the address of the next instruction that resulted from that branch.
  • [0023]
    To alleviate the limitations of both dynamic and static branch prediction techniques, the present invention discloses a hybrid branch prediction technique that combines the benefits of both dynamic and static branch prediction. With continued reference to FIG. 2, the technique begins in step 200 and advances to step 205 where static branch prediction is performed offline before final deployment of the processor, but based on applications which will be executed by the microprocessor after deployment. In various exemplary embodiments, this static branch prediction may be performed using the assistance of a complier or simulator. For example, if the processor is to be deployed in a particular embedded application, such as an electronic device, the simulator can simulate various instructions for the discrete instruction set to be executed by the processor prior to the processor being deployed. By performing static branch prediction a table of branch history can be fully populated with the actual addresses of the next instruction after a branch instruction is executed.
  • [0024]
    After developing a table of branch prediction data during static branch prediction, operation of the method continues to step 210 where the branch prediction table is stored in memory. In various exemplary embodiments, this step will involve storing the branch prediction table in a non-volatile memory that will be available for future use by the processor. Then, in step 215, when the processor is deployed in the desired embedded application, the static branch prediction data is preloaded into the branch history table in the BPU. In various exemplary embodiments, the branch prediction data is preloaded at power-up of the microprocessor, such as, for example, at power-up of the particular product containing the processor.
  • [0025]
    Operation of the method then advances to step 220 where, during ordinary operation, dynamic branch prediction is performed based on the preloaded branch prediction data without requiring a warm-up period or without unstable results. Then, in step 225, after resolving each branch in the selection stage of the multistage processor pipeline, the branch prediction table in the BPU is updated with the results to improve accuracy of the prediction information as necessary. Operation of the method terminates in step 230. It should be appreciated that in various exemplary embodiments, each time the processor is powered down, that the “current” branch prediction table may be stored in non-volatile memory so that each time the processor is powered up, the most recent branch prediction data is loaded into the BPU.
  • [0026]
    Referring now to FIG. 3, a block diagram illustrating the flow of data into and out of a branch prediction unit 314 in accordance with at least one exemplary embodiment of the invention is illustrated. In the Fetch stage 310 of the instruction pipeline, the BPU 314 maintains a branch prediction look-up table 316 that stores the address of the next instruction indexed by the address of the branch instruction. Thus, when the branch instruction enters the pipeline, the look-up table 316 is referenced by the instruction's address. The address of the next instruction is taken from the table 316 and injected in the pipeline directly following the branch instruction. Therefore, if the branch is taken then the next instruction address is available at the next clock signal. If the branch is not taken, the pipeline must be flushed and the correct instruction address injected back at the fetch stage 310. In the event that a pipeline flush is required, the look-up table 316 is updated with the actual address of the next instruction so that it will be available for the next instance of that branch instruction.
  • [0027]
    While the foregoing description includes many details and specificities, it is to be understood that these have been included for purposes of explanation only. The embodiments of the present invention are not to be limited in scope by the specific embodiments described herein. For example, although many of the embodiments disclosed herein have been described with reference to branch prediction in embedded RISC-type microprocessors, the principles herein are equally applicable to branch prediction in microprocessors in general. Indeed, various modifications of the embodiments of the present inventions, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such modifications are intended to fall within the scope of the following appended claims. Further, although the embodiments of the present inventions have been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the embodiments of the present inventions can be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the embodiments of the present inventions as disclosed herein.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5155843 *Jun 29, 1990Oct 13, 1992Digital Equipment CorporationError transition mode for multi-processor system
US5327536 *May 22, 1991Jul 5, 1994Nec CorporationMicroprocessor having branch prediction function
US5339365 *Aug 27, 1990Aug 16, 1994Canon Kabushiki KaishaImage processing apparatus capable of using fuzzy logic
US5422739 *Jul 7, 1992Jun 6, 1995Canon Kabushiki KaishaColor expressing method, color image reading apparatus and color image processing apparatus
US5454117 *Aug 25, 1993Sep 26, 1995Nexgen, Inc.Configurable branch prediction for a processor performing speculative execution
US5504592 *Feb 21, 1995Apr 2, 1996Canon Kabushiki KaishaColor expressing method, color image reading apparatus and color image processing apparatus
US5577217 *May 7, 1996Nov 19, 1996Intel CorporationMethod and apparatus for a branch target buffer with shared branch pattern tables for associated branch predictions
US5655122 *Apr 5, 1995Aug 5, 1997Sequent Computer Systems, Inc.Optimizing compiler with static prediction of branch probability, branch frequency and function frequency
US5659752 *Jun 30, 1995Aug 19, 1997International Business Machines CorporationSystem and method for improving branch prediction in compiled program code
US5692168 *Feb 27, 1996Nov 25, 1997Cyrix CorporationPrefetch buffer using flow control bit to identify changes of flow within the code stream
US5752014 *Apr 29, 1996May 12, 1998International Business Machines CorporationAutomatic selection of branch prediction methodology for subsequent branch instruction based on outcome of previous branch prediction
US5761723 *Apr 8, 1996Jun 2, 1998Motorola, Inc.Data processor with branch prediction and method of operation
US5778423 *Jun 29, 1990Jul 7, 1998Digital Equipment CorporationPrefetch instruction for improving performance in reduced instruction set processor
US5995248 *Mar 20, 1997Nov 30, 1999Minolta Co., Ltd.Image forming device and method having MTF correction
US6076158 *Jul 1, 1993Jun 13, 2000Digital Equipment CorporationBranch prediction in high-performance processor
US6151672 *Feb 23, 1998Nov 21, 2000Hewlett-Packard CompanyMethods and apparatus for reducing interference in a branch history table of a microprocessor
US6189091 *Dec 2, 1998Feb 13, 2001Ip First, L.L.C.Apparatus and method for speculatively updating global history and restoring same on branch misprediction detection
US6253287 *Sep 9, 1998Jun 26, 2001Advanced Micro Devices, Inc.Using three-dimensional storage to make variable-length instructions appear uniform in two dimensions
US6339822 *Oct 2, 1998Jan 15, 2002Advanced Micro Devices, Inc.Using padded instructions in a block-oriented cache
US6353882 *Jul 11, 2000Mar 5, 2002Hewlett-Packard CompanyReducing branch prediction interference of opposite well behaved branches sharing history entry by static prediction correctness based updating
US6427206 *May 3, 1999Jul 30, 2002Intel CorporationOptimized branch predictions for strongly predicted compiler branches
US6477683 *Feb 5, 1999Nov 5, 2002Tensilica, Inc.Automated processor generation system for designing a configurable processor and method for the same
US6499101 *Mar 18, 1999Dec 24, 2002I.P. First L.L.C.Static branch prediction mechanism for conditional branch instructions
US6526502 *Dec 16, 2000Feb 25, 2003Ip-First LlcApparatus and method for speculatively updating global branch history with branch prediction prior to resolution of branch outcome
US6560754 *Mar 13, 2000May 6, 2003Arc International PlcMethod and apparatus for jump control in a pipelined processor
US6571331 *Apr 3, 2001May 27, 2003Ip-First, LlcStatic branch prediction mechanism for conditional branch instructions
US6647491 *Oct 1, 2001Nov 11, 2003Hewlett-Packard Development Company, L.P.Hardware/software system for profiling instructions and selecting a trace using branch history information for branch predictions
US6681295 *Aug 31, 2000Jan 20, 2004Hewlett-Packard Development Company, L.P.Fast lane prefetching
US6763452 *Jun 24, 1999Jul 13, 2004Ati International SrlModifying program execution based on profiling
US6886093 *May 4, 2001Apr 26, 2005Ip-First, LlcSpeculative hybrid branch direction predictor
US6948052 *Oct 29, 2002Sep 20, 2005Seiko Epson CorporationHigh-performance, superscalar-based computer system with out-of-order instruction execution
US20010021974 *Feb 1, 2001Sep 13, 2001Samsung Electronics Co., Ltd.Branch predictor suitable for multi-processing microprocessor
US20010032309 *Apr 3, 2001Oct 18, 2001Henry G. GlennStatic branch prediction mechanism for conditional branch instructions
US20010040686 *Jun 26, 1998Nov 15, 2001Heidi M. SchoolcraftStreamlined tetrahedral interpolation
US20010044892 *Sep 10, 1998Nov 22, 2001Shinichi YamauraMethod and system for high performance implementation of microprocessors
US20010056531 *Mar 19, 1998Dec 27, 2001Mcfarling ScottBranch predictor with serially connected predictor stages for improving branch prediction accuracy
US20020066006 *Nov 29, 2000May 30, 2002Lsi Logic CorporationSimple branch prediction and misprediction recovery method
US20020069351 *Dec 29, 2000Jun 6, 2002Shyh-An ChiMemory data access structure and method suitable for use in a processor
US20020073301 *Dec 7, 2000Jun 13, 2002International Business Machines CorporationHardware for use with compiler generated branch information
US20020078332 *Dec 19, 2000Jun 20, 2002Seznec Andre C.Conflict free parallel read access to a bank interleaved branch predictor in a processor
US20020083312 *Dec 27, 2000Jun 27, 2002Balaram SinharoyBranch Prediction apparatus and process for restoring replaced branch history for use in future branch predictions for an executing program
US20020087851 *Dec 27, 2001Jul 4, 2002Matsushita Electric Industrial Co., Ltd.Microprocessor and an instruction converter
US20020087852 *Dec 28, 2000Jul 4, 2002Jourdan Stephan J.Method and apparatus for predicting branches using a meta predictor
US20020138236 *Jan 18, 2002Sep 26, 2002Akihiro TakamuraProcessor having execution result prediction function for instruction
US20020157000 *Mar 1, 2001Oct 24, 2002International Business Machines CorporationSoftware hint to improve the branch target prediction accuracy
US20020188833 *May 4, 2001Dec 12, 2002Ip First LlcDual call/return stack branch prediction system
US20020194461 *May 4, 2001Dec 19, 2002Ip First LlcSpeculative branch target address cache
US20020194462 *May 4, 2001Dec 19, 2002Ip First LlcApparatus and method for selecting one of multiple target addresses stored in a speculative branch target address cache per instruction cache line
US20020194463 *May 4, 2001Dec 19, 2002Ip First Llc,Speculative hybrid branch direction predictor
US20020194464 *May 4, 2001Dec 19, 2002Ip First LlcSpeculative branch target address cache with selective override by seconday predictor based on branch instruction type
US20020199092 *Jul 12, 2002Dec 26, 2002Ip-First LlcSplit history tables for branch prediction
US20030023838 *Jul 27, 2001Jan 30, 2003Karim Faraydon O.Novel fetch branch architecture for reducing branch penalty without branch prediction
US20030204705 *Apr 30, 2002Oct 30, 2003Oldfield William H.Prediction of branch instructions in a data processing apparatus
US20040015683 *Jul 18, 2002Jan 22, 2004International Business Machines CorporationTwo dimensional branch history table prefetching mechanism
US20040049660 *Sep 6, 2002Mar 11, 2004Mips Technologies, Inc.Method and apparatus for clearing hazards using jump instructions
US20040068643 *Sep 25, 2003Apr 8, 2004Dowling Eric M.Method and apparatus for high performance branching in pipelined microsystems
US20040139281 *Jul 31, 2003Jul 15, 2004Ip-First, Llc.Apparatus and method for efficiently updating branch target address cache
US20040172524 *Jun 20, 2002Sep 2, 2004Jan HoogerbruggeMethod, apparatus and compiler for predicting indirect branch target addresses
US20040186985 *Mar 21, 2003Sep 23, 2004Analog Devices, Inc.Method and apparatus for branch prediction based on branch targets
US20040193843 *Mar 31, 2003Sep 30, 2004Eran AltshulerSystem and method for early branch prediction
US20040193855 *Mar 31, 2003Sep 30, 2004Nicolas KacevasSystem and method for branch prediction access
US20040225870 *May 7, 2003Nov 11, 2004Srinivasan Srikanth T.Method and apparatus for reducing wrong path execution in a speculative multi-threaded processor
US20040225871 *Jun 15, 2004Nov 11, 2004Naohiko IrieBranch control memory
US20040225872 *Jun 4, 2002Nov 11, 2004International Business Machines CorporationHybrid branch prediction using a global selection counter and a prediction method comparison table
US20040230782 *May 12, 2003Nov 18, 2004International Business Machines CorporationMethod and system for processing loop branch instructions
US20040255104 *Jun 12, 2003Dec 16, 2004Intel CorporationMethod and apparatus for recycling candidate branch outcomes after a wrong-path execution in a superscalar processor
US20040268102 *Jun 30, 2003Dec 30, 2004Combs Jonathan D.Mechanism to remove stale branch predictions at a microprocessor
US20050027974 *Jul 31, 2003Feb 3, 2005Oded LempelMethod and system for conserving resources in an instruction pipeline
US20050050309 *Aug 27, 2004Mar 3, 2005Renesas Technology Corp.Data processor
US20050066305 *Sep 20, 2004Mar 24, 2005Lisanke Robert JohnMethod and machine for efficient simulation of digital hardware within a software development environment
US20050076193 *Oct 6, 2003Apr 7, 2005Ip-First, Llc.Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
US20050091479 *Aug 19, 2004Apr 28, 2005Sung-Woo ChungBranch predictor, system and method of branch prediction
US20050125613 *Dec 3, 2003Jun 9, 2005Sangwook KimReconfigurable trace cache
US20050125632 *Dec 3, 2003Jun 9, 2005Advanced Micro Devices, Inc.Transitioning from instruction cache to trace cache on label boundaries
US20050125634 *Jan 4, 2005Jun 9, 2005Fujitsu LimitedProcessor and instruction control method
US20050132175 *Nov 1, 2004Jun 16, 2005Ip-First, Llc.Speculative hybrid branch direction predictor
US20050154867 *Jan 14, 2004Jul 14, 2005International Business Machines CorporationAutonomic method and apparatus for counting branch instructions to improve branch predictions
US20050172277 *Jan 18, 2005Aug 4, 2005Saurabh ChhedaEnergy-focused compiler-assisted branch prediction
US20050216703 *Mar 26, 2004Sep 29, 2005International Business Machines CorporationApparatus and method for decreasing the latency between an instruction cache and a pipeline processor
US20050216713 *Mar 25, 2004Sep 29, 2005International Business Machines CorporationInstruction text controlled selectively stated branches for prediction via a branch target buffer
US20050223202 *Mar 31, 2004Oct 6, 2005Intel CorporationBranch prediction in a pipelined processor
US20060015706 *Jun 30, 2004Jan 19, 2006Chunrong LaiTLB correlated branch predictor and method for use thereof
US20060036836 *Oct 17, 2005Feb 16, 2006Metaflow Technologies, Inc.Block-based branch target buffer
US20060041868 *Oct 29, 2004Feb 23, 2006Cheng-Yen HuangMethod for verifying branch prediction mechanism and accessible recording medium for storing program thereof
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7779241 *Apr 10, 2007Aug 17, 2010Dunn David AHistory based pipelined branch prediction
US7971042Sep 28, 2006Jun 28, 2011Synopsys, Inc.Microprocessor system and method for instruction-initiated recording and execution of instruction sequences in a dynamically decoupleable extended instruction pipeline
US8131982 *Jun 13, 2008Mar 6, 2012International Business Machines CorporationBranch prediction instructions having mask values involving unloading and loading branch history data
US8473727Aug 6, 2010Jun 25, 2013David A. DunnHistory based pipelined branch prediction
US8521999Mar 11, 2010Aug 27, 2013International Business Machines CorporationExecuting touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history
US8719837May 19, 2005May 6, 2014Synopsys, Inc.Microprocessor architecture having extendible logic
US9003422Mar 21, 2014Apr 7, 2015Synopsys, Inc.Microprocessor architecture having extendible logic
US9135012Jun 14, 2012Sep 15, 2015International Business Machines CorporationInstruction filtering
US9135013Nov 25, 2013Sep 15, 2015International Business Machines CorporationInstruction filtering
US9152424Jun 14, 2012Oct 6, 2015International Business Machines CorporationMitigating instruction prediction latency with independently filtered presence predictors
US9152425 *Dec 10, 2013Oct 6, 2015International Business Machines CorporationMitigating instruction prediction latency with independently filtered presence predictors
US9519480 *Feb 11, 2008Dec 13, 2016International Business Machines CorporationBranch target preloading using a multiplexer and hash circuit to reduce incorrect branch predictions
US20050278505 *May 19, 2005Dec 15, 2005Lim Seow CMicroprocessor architecture including zero impact predictive data pre-fetch mechanism for pipeline data memory
US20050289323 *May 19, 2005Dec 29, 2005Kar-Lik WongBarrel shifter for a microprocessor
US20070260862 *May 3, 2006Nov 8, 2007Mcfarling ScottProviding storage in a memory hierarchy for prediction information
US20090204798 *Feb 11, 2008Aug 13, 2009Alexander Gregory WSimplified Implementation of Branch Target Preloading
US20100287358 *May 5, 2009Nov 11, 2010International Business Machines CorporationBranch Prediction Path Instruction
US20110225401 *Mar 11, 2010Sep 15, 2011International Business Machines CorporationPrefetching branch prediction mechanisms
US20140101418 *Dec 10, 2013Apr 10, 2014International Business Machines CorporationMitigating instruction prediction latency with independently filtered presence predictors
US20140229721 *Mar 30, 2012Aug 14, 2014Andrew T. ForsythDynamic branch hints using branches-to-nowhere conditional branch
Classifications
U.S. Classification712/228, 712/E09.052, 712/240, 712/E09.051
International ClassificationG06F15/76, G06F12/08, G06F12/00, G06F15/78, G06F9/318, G06F15/00, H03M13/00, G06F9/30, G06F9/00, G06F9/38
Cooperative ClassificationG06F9/30145, Y02B60/1207, G06F12/0802, G06F9/3897, G06F15/7867, G06F9/30181, G06F9/30149, G06F9/3885, G06F9/3816, G06F9/325, G06F9/3802, G06F9/3844, G06F9/30032, G06F9/30036, G06F9/3846, Y02B60/1225, G06F9/3806, G06F5/01, G06F9/32, G06F11/3648, G06F9/3861
European ClassificationG06F9/38B2B, G06F9/30X, G06F11/36B7, G06F9/38T8C2, G06F15/78R, G06F9/38D2, G06F9/38B9, G06F9/38T, G06F9/30A1M, G06F9/32B6, G06F9/30T2, G06F9/38B, G06F9/30A1P, G06F5/01, G06F9/38E2S, G06F9/38E2D
Legal Events
DateCodeEventDescription
Aug 29, 2005ASAssignment
Owner name: ARC INTERNATIONAL, UNITED KINGDOM
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ARISTODEMOU, ARIS;FUHLER, RICH;WONG, KAR-LIK;REEL/FRAME:016932/0953;SIGNING DATES FROM 20050825 TO 20050826