US 20050280155 A1
The present invention provides a method of coupling substrates together. The method includes providing first and second substrates and then coupling the first and second substrates together. One of the first and second substrates includes devices with an interconnect region positioned thereon and the other substrate carries a device structure.
1. A method of forming circuitry comprising:
providing a first substrate with electronic devices formed thereon;
providing an interconnect region on a surface of the first substrate, the interconnect region having conductive interconnects and vias extending therethrough;
providing a second substrate with a device structure positioned thereon, the device structure including a stack of semiconductor layers; and
coupling the device structure to the interconnect region.
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11. A method of forming a circuit comprising:
providing a handle substrate;
providing a donor substrate with a device structure positioned thereon, the device structure including a stack of semiconductor layers;
coupling the first and second substrates together;
removing the donor substrate from the first device structure so that the first device structure is carried by the handle substrate;
providing an acceptor substrate which carries an interconnect region, the interconnect region being electrically coupled to electronic devices carried by the acceptor substrate;
coupling the first device structure and interconnect region together; and
removing the handle substrate and the first and second dielectric regions.
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15. A method of forming a circuit comprising:
providing a first substrate;
positioning an interconnect region on a surface of the first substrate, the interconnect region having conductive interconnects and vias extending therethrough;
providing a second substrate;
positioning a device structure on a surface of the second substrate, the device structure including a stack of doped semiconductor material layers; and
coupling the device structure to the interconnect region.
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This is a continuation-in-part of application Ser. No. 10/873,969, entitled “THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE AND METHOD OF MAKING SAME”, which was filed 21 Jun. 2004 and is incorporated in its entirety herein by reference.
1. Field of the Invention
The present invention relates generally to semiconductors and, more particularly, to forming circuitry using wafer bonding.
2. Description of the Related Art
Advances in semiconductor manufacturing technology have provided computer chips with integrated circuits that include many millions of active and passive electronic devices, along with the interconnects to provide the desired circuit connections. As is well-known, most integrated circuits include laterally oriented active and passive electronic devices that are carried on a single major surface of a substrate. Active devices typically include transistors and passive devices typically include resistors, capacitors, and inductors. However, these laterally oriented devices consume significant amounts of chip area.
For example, a typical computer system includes a main computer chip with a processor circuit, a control circuit, and a memory cache that are carried on a single major surface of a substrate. The typical computer system also includes main memory which is positioned on a separate memory chip outside the main computer chip. Since the memory cache is positioned on the same substrate as the processor and control circuits in the main computer chip, it is often referred to as embedded memory.
The memory cache typically includes fast and expensive memory cells, such as Static Random Access Memory (SRAM) cells, and the main memory typically includes slower and less expensive Dynamic Random Access Memory (DRAM) cells. Both SRAM and DRAM cells are larger than the devices included in the processor and control circuits, with SRAM cells being much larger than DRAM cells. As is well-known in the art, cache memory (L1 cache or L2 cache, for example) is used to store information from a slower storage medium or subsystem, such as the main memory or peripherals like hard disks and CD-ROMs, that is accessed frequently to speed up the operation of the main computer chip.
The operation of the main computer chip is increased because its idle time is reduced. For example, when the processor circuit accesses the main memory, it does so in about 60 nanoseconds (ns) because the main memory is external to the main computer chip and it includes slower memory cells. However, a typical processor circuit can have cycle times of about 2 nanoseconds. As a result, the processor circuit is idle for many cycle times while it accesses the main memory. In this example, there are about 30 wasted cycles while the processor circuit accesses the main memory. The processor circuit, however, can access the cache memory in about 10 ns to 30 ns, so the idle time is significantly reduced if the information needed is temporarily stored in the cache memory. The access time of the processor circuit to a hard disk is even slower at about 10 milliseconds (ms) to 12 ms, and the access time to a CD-ROM drive is about 10 times greater than this. Hence, cache memory uses a small amount of fast and expensive memory to allow the processor circuit faster access to information normally stored by a large amount of slower, less-expensive memory.
With this in mind, it seems like the operation of the computer system can be increased even more by embedding the main memory with the main computer chip so it does not take as long for the processor to access it. One way to embed the main memory to the computer chip is to bond it thereto, as in a 3-D package or a 3-D integrated circuit (IC).
Conventional 3-D packages and 3-D ICs both include a substrate with a memory circuit bonded to it by a bonding region positioned therebetween. The memory circuit typically includes lateral memory devices and the processor circuit typically includes lateral active and passive devices. Further, the memory and processor circuits are prefabricated before the bonding takes place. In both the 3-D package and 3-D ICs, the memory and processor devices are connected to large bonding pads included in respective circuits. However, in the 3-D package, the bonding pads are connected together using wire bonds so that the memory and processor circuits can communicate with each other. In the 3-D IC, the bonding pads are connected together using conductive interconnects which extend therebetween. There are several problems, however, with using 3-D packages and 3-D ICs.
One problem is that the use of wire bonds increases the access time between the processor and memory circuits because the impedance of wire bonds and large contact pads is high. The contact pads are large in 3-D packages to make it easier to attach the wire bonds thereto. Similarly, the contact pads in 3-D ICs have correspondingly large capacitances which also increase the access time between the processor and memory circuits. The contact pads are large in 3-D ICs to make the alignment between the lateral memory devices in the memory circuit, the lateral active and passive devices in the processor circuit, and the conductive interconnects extending therebetween easier. These devices need to be properly aligned with each other and the interconnects because they are fabricated before the bonding takes place. Another problem is that the use of wire bonds is less reliable because the wire bonds can break and become detached.
Another problem with using 3-D packages and 3-D ICs is cost. The use of wire bonds is expensive because it is difficult to attach them between the processor and memory circuits and requires expensive equipment. Further, it requires expensive equipment to align the various devices in the 3-D IC. The bonding and alignment is made even more difficult and expensive because of the trend to scale devices to smaller dimensions.
As mentioned above, the SRAM cells are larger and expensive, so increasing the number of them in the memory circuit would increase the cost of the computer chip dramatically. DRAM cells are less expensive and smaller, but to include them in the memory circuit will still increase the cost. One reason the costs increase for both embedded SRAM and DRAM cells is because they both use a number of masks to fabricate them.
One problem with using lateral memory devices in the memory circuit is their size. The size of a conventional SRAM cell is about 70-120 F2 and the size of a conventional DRAM memory cell is about 15 F2. As is known in the art, 1 F is the minimum photolithographic feature size. For example, if the computer chip is being fabricated using 90 nm lithography, then 1 F corresponds to 90 nm and 1 F2 corresponds to an area that it 90 nm by 90 nm in size. If the computer chip is being fabricated using 60 nm lithography, then 1 F corresponds to 60 nm and 1 F2 corresponds to an area that it 60 nm by 60 nm in size. Hence, to increase the number of memory cells in the memory circuit, the DRAM or SRAM cells would have to be scaled to smaller dimensions, but this requires advances in lithography and increasingly expensive manufacturing equipment. Further, the DRAM and SRAM cells become less accurate and reliable when scaled to smaller dimension.
Accordingly, it is highly desirable to provide new structures and methods for fabricating computer chips which operate faster and are cost effective to fabricate.
The present invention provides a method of coupling substrates together including providing first and second substrates, both the first and second substrates having a conductive bonding region formed thereon; and coupling the first and second substrates together with the conductive bonding regions, where one of the substrate has devices with interconnect region and the other substrate has stack of doped semiconductor layers.
The present invention provides a method of coupling substrates together which includes providing a first substrate with a nonconductive or partially nonconductive bonding region coupled to it; providing a second substrate with a conductive bonding region coupled to it; and bonding the surface of the conductive bonding region to the first substrate so that the conductive bonding region and the first substrate are coupled together, where one of the substrate has devices with interconnect region and the other substrate has stack of doped semiconductor layers.
The present invention provides a method of coupling substrates together including providing first and second substrates, both the first and second substrates having a nonconductive bonding region formed thereon; and coupling the first and second substrates together with the nonconductive bonding regions, where one of the substrate has devices with interconnect region and the other substrate has stack of doped semiconductor layers.
The present invention further provides a method of forming a circuit providing first, second, and third substrates, each having various bonding regions formed thereon; and forming a bond between the bonding surfaces using the third substrate as a handle substrate so that the first and second substrates are coupled together, where one of the substrate has devices with interconnect region and the other substrate has stack of doped semiconductor layers.
These and other features, aspects, and advantages of the present invention will become better understood with reference to the following drawings, description, and claims.
The portions carried by the acceptor substrate are shown in
Circuitry 100 is formed using a wafer bonding method which has several advantages. One advantage is that circuitry 100 includes more electronic devices in a given volume because the devices extend laterally across the acceptor substrate as well as above it. This reduces manufacturing costs because the mask set used to fabricate the devices is less complicated. The mask set is less complicated because the devices positioned above the acceptor substrate can be formed with a different mask set than the devices formed on the acceptor substrate. The cost is further reduced because the yield increases. The yield increases because the die size decreases so that fewer chips will be defective. Still another advantage is that the donor substrate does not have to be aligned very accurately with the acceptor substrate when bonding them together. This is because the donor substrate includes blanket layers of semiconductor materials and the devices formed therewith are formed after the bonding has taken place.
An interconnect region 131 is positioned on surface 130 a. Here, interconnect region 131 includes an ILD (InterLayer Dielectric) region 133 with one or more interconnects extending therethrough. The interconnect typically includes one or more interconnect line 132 and/or conductive vias 134. Lines 132 and vias 134 extend therethrough region 131 between surface 130 a and a surface 131 a of region 131. Contacts 134 b are coupled to the electronic devices carried by substrate 130 and extend upwardly from surface 130 a. ILD region 133 can be formed using many different methods, such as CVD (Chemical Vapor Deposition) and SOG (Spin On Glass). Interconnection lines 132 and vias 134 include conductive materials, such as aluminum, copper, tungsten, tungsten silicide, titanium, titanium silicide, tantalum, and doped polysilicon.
Interconnect region 131 can have many different structures other than that shown in
It should be noted that interconnect region 131 can include a blocking region 124, as shown in
In some embodiments, contact region 121 can include one or more layers of materials. For example, in
In this particular example, structure 141 includes an n+pn+ stack, although it can have other layer stacks, such as npn, p+np+, and pnp. The n+pn+ stack includes an n+-doped region 143 a on surface 140 a, a p-doped region 143 b on region 143 a, and an n+-doped region 143 c on region 143 b. In this embodiment, regions 143 a-143 c can be doped by ion implantation, diffusion, or plasma. However, in other embodiments, regions 143 a-143 c can be doped during growth. More information about forming regions 143 a-143 c can be found in a co-pending U.S. patent application titled “SEMICONDUCTOR LAYER STRUCTURE AND METHOD OF MAKING THE SAME” filed on an even date herewith by the same inventor and incorporated herein by reference.
In another example, device structure 141 can include a structure with an n+pn+pnp+ stack of semiconductor layers. In this example, the stack can be processed into a negative differential resistance static random access memory device which includes a transistor and a thyristor. More information about this device structure can be found in a co-pending U.S. patent application titled “SEMICONDUCTOR MEMORY DEVICE” filed on an even date herewith by the same inventor and incorporated herein by reference.
Detaching region 142 can be formed in many different ways. For example, it can be formed by implanting hydrogen, forming an anodized porous material layer, or implanting oxygen therein so that it is defective and its mechanical strength and chemical compositions are different from adjacent material regions. As discussed in conjunction with
As shown in
In other embodiments, a dielectric region 148 can be positioned on surface 141 a of device structure 141 as shown in
In another embodiment as shown in
In accordance with the invention, it is desired to couple device structure 141 and/or device structure 149 to the electronic devices carried by substrate 130. As shown in
In accordance with the invention, once device structure 141 or 149 is coupled to the electronic devices carried by acceptor substrate 130 through bonding, it is desirable to remove a portion of donor substrate 140 to leave device structure 141. In the examples discussed below, it is shown that portions of substrate 140 are removed so that device structure 141 can be subsequently processed to form electronic devices therewith. The processing steps involved in the formation of the electronic devices out of device structure 141 includes steps well known in the art, such as lithography, etching, and deposition, among other steps. More details of the processing steps and examples of device structures can be found in a co-pending U.S. patent application titled “SEMICONDUCTOR MEMORY DEVICE” filed on an even date herewith by the same inventor and incorporated herein by reference.
The devices formed from device structure 141 and/or 151 are typically called “vertical” devices because their layer structure extends substantially perpendicular to surface 131 a. In other words, the n+pn+ layers of region 141 are stacked on top of each other so that current flow through them is substantially perpendicular to surface 131 a. This is different from conventional devices which are often called lateral or planar devices. Lateral devices have their layer structure extending horizontally relative to a surface of a material region that carries them. In other words, the n+pn+ layers included in a lateral device are positioned side-by-side so that current flow through them is substantially parallel to the supporting surface.
Substrate 140 can be removed in several different ways. In
Another advantage of this method is that the donor wafer is bonded to the handle wafer and then processed as described above in conjunction with
This is desired because the acceptor wafer has electronic devices already formed thereon and high temperature and pressure processing can negatively impact the performance of these devices. Hence, the donor wafer is attached to the handle wafer and processed. After processing, the donor wafer is bonded to the acceptor wafer and the handle wafer is removed.
Dielectric regions 111 and 148 are separated from each other to separate dielectric region 111 and handle substrate 110 from device structure 141. In
The present invention is described above with reference to preferred embodiments. However, those skilled in the art will recognize that changes and modifications may be made in the described embodiments without departing from the nature and scope of the present invention. Various further changes and modifications will readily occur to those skilled in the art. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof.