Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20060029325 A1
Publication typeApplication
Application numberUS 11/245,915
Publication dateFeb 9, 2006
Filing dateOct 7, 2005
Priority dateJun 19, 2003
Also published asCN1601384A, CN1601384B, EP1634117A1, US6983086, US20040258344, WO2005001558A1, WO2005006063A1
Publication number11245915, 245915, US 2006/0029325 A1, US 2006/029325 A1, US 20060029325 A1, US 20060029325A1, US 2006029325 A1, US 2006029325A1, US-A1-20060029325, US-A1-2006029325, US2006/0029325A1, US2006/029325A1, US20060029325 A1, US20060029325A1, US2006029325 A1, US2006029325A1
InventorsBehzad Fardi, Farshid Adibi, Chaoyang Li, Anirban Bandyopadhyay, Mahesh Junnarkab
Original AssigneeBehzad Fardi, Farshid Adibi, Chaoyang Li, Anirban Bandyopadhyay, Mahesh Junnarkab
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Thermally isolating optical devices
US 20060029325 A1
Abstract
A thermo-optic device may be formed with trenches that undercut the substrate beneath the thermo-optic device. Through the removal of the underlying substrate, the heat dissipation of the thermo-optic device may be reduced. This may reduce the thermal budget of the device, reducing the power requirements for operating the device in some embodiments.
Images(3)
Previous page
Next page
Claims(9)
1. A method comprising:
forming a thermo-optic device on a semiconductor substrate; and
removing a portion of the semiconductor substrate underneath the thermo-optic device.
2. The method of claim 1 wherein removing a portion includes using an isotropic etch.
3. The method of claim 2 including using an isotropic etch to form a first opening and forming a second opening through the first opening.
4. The method of claim 3 including forming the second opening using an anisotropic etch.
5. The method of claim 1 including forming a waveguide core on the semiconductor substrate and covering said core with an upper cladding.
6. The method of claim 5 including forming an opening through said upper cladding on either side of said core.
7. The method of claim 6 including leaving a portion of said upper cladding surrounding said core.
8. The method of claim 6 including forming a resistance heater over said upper cladding over said core.
9. The method of claim 1 including removing a portion of the semiconductor substrate on two opposed sides of said thermo-optic device.
Description
    CROSS-REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This application is a continuation of U.S. patent application Ser. No. 10/465,210, filed on Jun. 19, 2003.
  • BACKGROUND
  • [0002]
    This invention relates generally to optical components including those used in optical communication networks.
  • [0003]
    In optical communication networks, a waveguide core may extend across a semiconductor substrate. The core may be covered by an upper cladding and may be positioned over a lower cladding. The core may define an optical signal path. The cladding may have a lower refractive index than the core.
  • [0004]
    In some cases the optical characteristics of the core may be thermally modified. For example, thermo-optic devices may be operated through the application of heat. The refractive index of an optical device may be changed by heating. Thermo-optic switches may be used in Mach-Zehnder interferometers and directional couplers, as two examples.
  • [0005]
    Generally, the more heat that is dissipated by the thermo-optic device, the more the power requirements of the overall component. It is desirable to reduce the heat transfer to only that needed to achieve the thermo-optic effect.
  • [0006]
    Thus, there is a need for ways to reduce the amount of heat loss in thermo-optic devices.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0007]
    FIG. 1 is an enlarged cross-sectional view of one embodiment of the present invention at an early stage of manufacture;
  • [0008]
    FIG. 2 is an enlarged cross-sectional view of one embodiment of the present invention at a subsequent stage of manufacture;
  • [0009]
    FIG. 3 is an enlarged cross-sectional view of one embodiment of the present invention at a subsequent stage of manufacture;
  • [0010]
    FIG. 4 is an enlarged cross-sectional view of one embodiment of the present invention at a subsequent stage of manufacture;
  • [0011]
    FIG. 5 is an enlarged cross-sectional view of one embodiment of the present invention at a subsequent stage of manufacture; and
  • [0012]
    FIG. 6 is an enlarged cross-sectional view of one embodiment of the present invention at a subsequent stage of manufacture.
  • DETAILED DESCRIPTION
  • [0013]
    Referring to FIG. 1, a waveguide core 12 may be defined on a lower cladding 11 over a semiconductor substrate 10. In one embodiment, the core 12 may be part of a planar lightwave circuit. The core 12 and lower cladding 11 may, in turn, be covered by an upper cladding 14 as shown in FIG. 2.
  • [0014]
    Referring to FIG. 3, an electric resistance heater 16 may be defined over the upper cladding 14 atop the core 12. The heater 16 may be a more resistive material coupled to a source of power by a less resistive material. The electrical resistance heater 16 is selectively operable to change the optical properties of the core 12 in the vicinity of the heater 16. For example, in one embodiment, a thermo-optic switch may be formed.
  • [0015]
    Referring to FIG. 4, a pair of trenches 18 may be formed on either side of the heater 16 and core 12. The trenches 18 may be spaced from the core 12 to leave protective upper cladding 14 around the core 12, in one embodiment. The trenches 18 may extend through the upper cladding 14 and the lower cladding 11 down to the semiconductor substrate 10 in one embodiment of the present invention. A thermo-optic device 26 is defined between the trenches 18, in one embodiment.
  • [0016]
    Using the thermo-optic device 26 as a mask, an isotropic etch may be implemented into the substrate 10 through the trenches 18 to form the undercut regions 20, in one embodiment of the present invention, shown in FIG. 5. The etchant is more selective of the substrate 10 material and is less selective of the cladding material 11 and 14. Because of the isotropic nature of the etching, the etching extends under the lower cladding 11 on opposed sides of each trench 18. By the term isotropic, it is intended to refer to an etchant that etches outwardly under a mask that defines an opening for the etchant to etch an underlying material.
  • [0017]
    The resulting regions 20 extend under the structure that includes the core 12 and the heater 16. One result of this under-etching is to reduce the amount of substrate 10 material underneath the core 12 and the heater 16.
  • [0018]
    Referring to FIG. 6, the trenches 18 may guide the anisotropic etching from the bottoms of the regions 20. The etchant is more selective of the substrate 10 than of the cladding 11 or 14. As a result, an anisotropically etched trench 22 extends below the regions 20 formed by isotropic etching. A substantial portion of the substrate 10 material underneath the core 12 and the heater 16 is removed, leaving a relatively thin pillar 24 of substrate 10.
  • [0019]
    The inventors of the present invention have determined that a substantial portion of the heat loss from heater 16 occurs through the semiconductor substrate 10. By reducing the amount of available substrate 10 underneath the heater 16, this heat loss may be reduced. The heat loss may increase the power needs of the device and dispersed heat may adversely affect the optical properties of surrounding components.
  • [0020]
    In some embodiments, the regions 20 and the trenches 22 may be filled with a thermally isolating material. Also, in some embodiments, the trenches 18 may also be filled or covered with a thermally isolating material.
  • [0021]
    While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
  • [0022]
    What is claimed is:
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4978188 *Oct 13, 1989Dec 18, 1990Nippon Telegraph And Telephone CorporationIntegrated optical device and method for manufacturing thereof
US5182234 *Jul 26, 1991Jan 26, 1993Advanced Power Technology, Inc.Profile tailored trench etch using a SF6 -O2 etching composition wherein both isotropic and anisotropic etching is achieved by varying the amount of oxygen
US5465860 *Jul 1, 1994Nov 14, 1995Intel CorporationMethod of forming an integrated circuit waveguide
US6248206 *Oct 1, 1996Jun 19, 2001Applied Materials Inc.Apparatus for sidewall profile control during an etch process
US6847750 *Nov 22, 2000Jan 25, 2005Optun (Bvi) Ltd.Thermo-optical waveguide switch
US6870979 *Oct 7, 2003Mar 22, 2005The Furukawa Electric Co., LtdOptical circuit, method for manufacturing optical circuit, optical circuit device and method for controlling optical circuit device
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7853108Dec 28, 2007Dec 14, 2010Massachusetts Institute Of TechnologyFabrication-tolerant waveguides and resonators
US7903909Oct 22, 2008Mar 8, 2011Massachusetts Institute Of TechnologyLow-loss bloch wave guiding in open structures and highly compact efficient waveguide-crossing arrays
US7920770May 1, 2008Apr 5, 2011Massachusetts Institute Of TechnologyReduction of substrate optical leakage in integrated photonic circuits through localized substrate removal
US8032027Jul 25, 2006Oct 4, 2011Massachusetts Institute Of TechnologyWide free-spectral-range, widely tunable and hitless-switchable optical channel add-drop filters
US8068706Oct 15, 2010Nov 29, 2011Massachusetts Institute Of TechnologyFabrication-tolerant waveguides and resonators
US8105758Jul 11, 2007Jan 31, 2012Massachusetts Institute Of TechnologyMicrophotonic maskless lithography
US8111994Aug 16, 2007Feb 7, 2012Massachusetts Institute Of TechnologyBalanced bypass circulators and folded universally-balanced interferometers
US8116603Jan 6, 2011Feb 14, 2012Massachusetts Institute Of TechnologyLow-loss Bloch wave guiding in open structures and highly compact efficient waveguide-crossing arrays
US8340478Dec 3, 2009Dec 25, 2012Massachusetts Institute Of TechnologyResonant optical modulators
US8483521May 28, 2010Jul 9, 2013Massachusetts Institute Of TechnologyCavity dynamics compensation in resonant optical modulators
US8655114Mar 26, 2008Feb 18, 2014Massachusetts Institute Of TechnologyHitless tuning and switching of optical resonator amplitude and phase responses
US20080014534 *Jul 11, 2007Jan 17, 2008Massachusetts Institute Of TechnologyMicrophotonic maskless lithography
US20080044184 *Aug 16, 2007Feb 21, 2008Milos PopovicBalanced bypass circulators and folded universally-balanced interferometers
US20090142019 *Oct 22, 2008Jun 4, 2009Massachusetts Institute Of TechnologyLow-loss bloch wave guiding in open structures and highly compact efficient waveguide-crossing arrays
US20090274418 *May 1, 2008Nov 5, 2009Massachusetts Institute Of TechnologyReduction of substrate optical leakage in integrated photonic circuits through localized substrate removal
US20100209038 *Mar 26, 2008Aug 19, 2010Massachusetts Institute Of TechnologyHitless tuning and switching of optical resonator amplitude and phase responses
US20110026879 *Oct 15, 2010Feb 3, 2011Massachusetts Institute Of TechnologyFabrication-tolerant waveguides and resonators
US20110158584 *Jan 6, 2011Jun 30, 2011Massachusetts Institute Of TechnologyLow-loss bloch wave guiding in open structures and highly compact efficient waveguide-crossing arrays
Classifications
U.S. Classification385/14
International ClassificationG02F1/025, G02F1/01, G02B6/12
Cooperative ClassificationG02F1/0147, G02F1/025
European ClassificationG02F1/025, G02F1/01T