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Publication numberUS20060033945 A1
Publication typeApplication
Application numberUS 11/201,922
Publication dateFeb 16, 2006
Filing dateAug 10, 2005
Priority dateAug 13, 2004
Also published asUS8286125, US8539398, US20100275173, WO2006020897A2, WO2006020897A3
Publication number11201922, 201922, US 2006/0033945 A1, US 2006/033945 A1, US 20060033945 A1, US 20060033945A1, US 2006033945 A1, US 2006033945A1, US-A1-20060033945, US-A1-2006033945, US2006/0033945A1, US2006/033945A1, US20060033945 A1, US20060033945A1, US2006033945 A1, US2006033945A1
InventorsJohn McDonald, Jon Pearson, Kenneth Ogami, Doug Anderson
Original AssigneeMcdonald John, Jon Pearson, Kenneth Ogami, Doug Anderson
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Design model for a hardware device-independent method of defining embedded firmware for programmable systems
US 20060033945 A1
Abstract
A processing device programming system automatically provides a user interface comprising a selectable list of one or more processing devices based on a system level solution, automatically generates an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices, and automatically programs the processing device according to the embedded programmable system solution.
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Claims(22)
1. A method, comprising:
automatically providing a user interface comprising a selectable list of one or more processing devices based on a system level solution;
automatically generating an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices; and
automatically programming the processing device according to the embedded programmable system solution.
2. The method of claim 1, wherein prior to the automatically providing, determining the selection of one or more processing devices by matching resource requirements of one or more functions of the system level solution to one or more base projects associated with the one or more processing devices.
3. The method of claim 1, further comprising automatically generating one or more base projects associated with the one or more processing devices based upon the resource requirements of the one or more functions of the system level solution and physical parameters associated with the one or more processing devices.
4. The method of claim 1, wherein prior to the automatically generating, providing the user interface with a selectable list of a plurality of high level devices to design the system level solution.
5. The method of claim 4, further comprising updating the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices after each selection of a high level device from the plurality of high level devices.
6. The method of claim 5, wherein prior to updating the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices, validating a current state of the system level solution.
7. The method of claim 6, wherein validating the current state of the system level solution further comprises:
validating executable expressions associated with the selected high level devices; and
validating the one or more processing devices by matching resources required by the current state of the system level solution to the one or more processing devices.
8. The method of claim 1, wherein the selectable list of one or more processing devices is comprised of at least one of a programmable logic device, a field programmable gate array, a micro-controller, a microprocessor-based device, or a circuit comprising a processing device.
9. A system, comprising:
a processing device maker engine to provide a user interface comprising a selectable list of one or more processing devices based on a system level solution; and
a hardware designer engine to receive the system level solution from the processing device maker and to generate an embedded programmable system solution from the system level solution and a processing device selected from the one or more processing devices, and to program the processing device according to the embedded programmable system solution.
10. The system of claim 9, wherein to provide the user interface, the processing device maker engine to determine the selection of one or more processing devices by matching resource requirements of one or more functions of the system level solution to one or more base projects associated with the one or more processing devices.
11. The system of claim 9, wherein the processing device maker engine further to generate one or more base projects associated with the one or more processing devices based upon the resource requirements of the one or more functions of the system level solution and physical parameters associated with the one or more processing devices.
12. The system of claim 9, wherein the processing device maker engine to provide the user interface with a selectable list of a plurality of high level devices to design the system level solution.
13. The system of claim 12, wherein the processing device maker engine to update the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices after each selection of a high level device from the plurality of high level devices.
14. The system of claim 13, wherein prior to the update of the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices, the processing device maker engine to validate a current state of the system level solution.
15. The system claim 14, wherein to validate the current state of the system level solution, the processing device maker engine further to validate executable expressions associated with the selected high level devices, and to validate the one or more processing devices by matching resources required by the current state of the system level solution to the one or more processing devices.
16. The system of claim 10, wherein the processing device maker engine further to save a first file comprising the system level solution, to delete one or more lower level files associated with the embedded programmable system, and to generate a schematic of the programmed selected processing device, wherein the schematic includes at least one of functional pins, input output devices, or interfacing circuitry.
17. The system of claim 10, wherein the selectable list of one or more processing devices is comprised of at least one of a programmable logic device, a field programmable gate array, a micro-controller, a microprocessor-based device, or a circuit comprising a processing device.
18. A machine readable medium having embodied thereon an instruction set, the instruction set being executable by a machine to perform operations comprising:
providing a user interface comprising a selectable list of one or more processing devices based on a system level solution;
generating an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices; and
programming the processing device according to the embedded programmable system solution.
19. The machine readable medium of claim 18, wherein prior to the automatically generating, providing the user interface with a selectable list of a plurality of high level devices to design the system level solution.
20. The machine readable medium of claim 19, further comprising updating the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices after each selection of a high level device from the plurality of high level devices.
21. The machine readable medium of claim 20, wherein prior to updating the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices, validating a current state of the system level solution.
22. The machine readable medium of claim 21, wherein validating the current state of the system level solution further comprises:
validating executable expressions associated with the selected high level devices; and
validating the one or more processing devices by matching resources required by the current state of the system level solution to the one or more processing devices.
Description
RELATED APPLICATION

This application claims the benefit of U.S. Provisional Patent Application No. 60/601,263, filed Aug. 13, 2004, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present invention relates generally to electronic circuits and in particular the programming of processing devices.

BACKGROUND

Processing devices, such as microcontrollers, field programmable arrays, etc., are widely used in the industry as control elements in many solutions. Most processing devices are general in purpose and are designed for use in a wide variety of problem solutions. As processing devices become more programmable and more widely applicable, a designer needs more specific device knowledge to select and use the appropriate processing device to solve a problem. For example, a Cypress MicroSystem's Programmable System on a Chip™ microcontroller (PSoC™ microcontroller) device may be the most widely applicable microcontroller devices currently on the market. Broadly applicable devices require a high amount of device specific knowledge to program the device to fit a variety of solutions. Unfortunately, many engineers charged with designing a system level solution do not possess the required specific knowledge to create the low level program of the solution for the device.

In a conventional solution using processing devices, hardware and software are usually created for a specific processing device, and may be redesigned (sometimes completely) following a change in requirements. The faster the time-to-market or the shorter the design, the more likely requirement changes are to occur. A common sequence of events is to first determine the system requirements to address a problem, then second to determine hardware and software requirements, then third to determine processing device and interfacing circuitry requirements, and fourth to find a suitable processing device and design suitable interfaces. Finally, the user must manually configure the processing device and write device specific firmware. In some cases, the user/programmer may have to re-write firmware, redesign circuitry, or choose another processing device based upon changing requirements.

These changing requirements result in one or all of costly and inefficient code changes and software and hardware architecture changes, which might also require a change in the processing device and/or significant redesign of the entire project. Such a redesign may be costly and further delay design and production schedules.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which:

FIG. 1 is a high level diagram illustrating multiple system level architectures for the programming of processing devices, according to various embodiments of the present invention;

FIG. 2 is a block diagram illustrating components making up a programming system, according to one embodiment of the present invention;

FIG. 3 is a flowchart illustrating a process for programming a processing device based on a user created system level solution, according to one embodiment of the invention;

FIG. 4 illustrates file types involved in processing device code generation, according to one embodiment of the present invention;

FIG. 5 is a flowchart illustrating a high level process for programming a processing device based on a user created system level solution, according to one embodiment of the invention;

FIG. 6 illustrates a diagrammatic representation of a machine in the exemplary form of a computer system within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that certain embodiments of the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the presented embodiments of the invention. The following detailed description includes several modules, which will be described below. These modules may be implemented by hardware components, such as logic, or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the operations described herein. Alternatively, the operations may be performed by a combination of hardware and software.

The following detailed description refers to programming processing devices based on a user created system level solution. It can be appreciated by those skilled in the art that a processing device (e.g., processing device 106 of FIG. 1) as referred to in the programming process, may include one or more general-purpose programmable processing devices, such as a microcontroller, an embedded programmable logic device (PLD), or the like. Alternatively, the processing device may include one or more special-purpose programmable processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like. The processing device may also include any combination of a general-purpose programmable processing device and a special-purpose programmable processing device. Additionally, the processing device to be programmed may include a larger circuit which incorporates any one or more of the named devices above.

FIG. 1 is a high level diagram illustrating multiple system level architectures for the programming of processing devices, according to various embodiments of the present invention. A user 102 is provided with a high level of abstraction to build a system level solution without prior knowledge and expertise of a particular programming device (e.g., processing device 106). The system level solution allows for lower level processes invisible to the user 102 to verify the system level solution, provide potential processing devices that may fit the design, and to build the design into an embedded programmable system solution that may be used to program a selected processing device.

In one embodiment, an application or program generates a GUI (graphical user interface, not shown) on computer 104 that permits a user 102 to interactively select, combine, and program a multitude of functional elements to generate a system level solution to be programmed on the processing device 106 (e.g., microcontroller, etc.). In various embodiments, the application or applications responsible for the GUI and system level solution processing may be wholly or partially running on computer 104 or may be wholly or partially running a remote device, such as server 108 in communication with computer 104 through network 110. This allows for user 102 to create a system level solution from a location remote from a system configured to generate the embedded programmable system solution and/or to physically program the processing device 106.

Once the user 102 has completed the system level solution, the user may select from one or more possible processing devices derived from processing the system level solution, either remotely or locally. Processing of the system level solution to create the embedded programmable system solution is controlled and facilitated by lower level processes invisible to the user 102. After the processing device 106 has been selected, a programming device 112, under control of the lower level processes, creates a programming image file 222 (See FIG. 2) and programs the processing device 106 accordingly. The physical programming the processing device 106 may occur locally or remotely. For example, the computer 104 may include a programming device module to program processing device 106 in a similar fashion to programming device 112. In another embodiment, the programming device 112 may be located remotely and configured to program the processing device 106 based on receiving the programming file from either the computer 104 or the server 108 through network 110.

FIG. 2 is a block diagram illustrating components making up a programming system 200, according to one embodiment of the present invention. The programming system 200 may be divided into two domains; a user domain 250 representing higher order processes and controls, and an expert domain 252 representing lower order processes and controls, which is an embedded development environment that requires a high level of expertise to develop embedded programmable system solutions. In one embodiment of the present invention, the user domain 250 may include the GUI of computer 104 that permits the user 102 to interactively select, combine, and program a multitude of high level functional elements to generate a system level solution. However, the system level solution must be converted in the expert domain 252 to the embedded programmable system solution, and more specifically into the programming image file 222 that may be used by the programming device 112 to program the processing device 106.

In the user domain 250, a specific application layer 201 includes the applications a battery charger maker 202, a temp controller maker 204, and a power meter maker 206, collectively known as applications 202, 204, 206. These are high level software applications which are visible to the user via the GUI of computer 104. The applications 202, 204, 206 are by example only, it can be appreciated that there may be a multitude of applications representing many kinds of devices and device functions. The applications 202, 204, 206 present options to the user 102 during the development of a system level solution. In one embodiment, the options are formatted metadata made available to each of the applications 202, 204, 206 for display to the user 102. The user 102 provides input selections or data based on these options, which may be captured in one or more files in various formats known in the art, such as HTML (hypertext markup language), XML (extended markup language), or any other format known in the art for structuring data in files. In one embodiment, the data is captured in a project design file 210, which is a single ASCII (American standard code for information interchange) file of XML.

In one embodiment, a processing device maker (PDM) engine 208 is a generic application in generic application layer 211 and is configured to receive and process data from the applications 202, 204, 206, and to dynamically update the project design file 210. The PDM engine 208 receives high level device drivers and associated device descriptions from a high level database 214. For example, the PDM engine 208 may provide the user 102, via the UI on the computer 104, a list of device elements based on the high level device descriptions, such as a temperature sensor, a fan, a voltage input, an LED (light emitting diode), etc. In one embodiment, the system level solution created by the user 102 may include one or a combination of device elements and associated functionality. Device elements include pin designations, inputs, and outputs, each of which may include operational attributes, such as a voltage input range for an input pin or a pushbutton switch that may be opened or closed. Additionally, the user 102 may also include operational instructions that include logic to activate device elements or portions thereof if a programmed condition occurs. For example, a user may use the GUI of computer 104 to program and simulate a fan switch to go to an ‘on’ state when the temperature sensor reads 100 degrees Celsius.

In one embodiment, as the user 102 makes connections within or between device elements and/or provides operational instructions, the PDM engine 208, in addition to updating the project design file 210, also verifies and validates the user the connections and operational instructions. A validation process ensures that the user 102 cannot create faulty interconnects, operational instructions, or create a system level solution that cannot be programmed into one of the available processing devices (e.g., processing device 106). For example, after each change during the design process the list of device elements and processing devices is dynamically updated such that the user 102 cannot make a faulty selection.

After the user 102 has created and simulated the system level solution, the PDM engine 208 creates a processing device file 216 based on the project design file 210 and the selected processing device 106. The processing device file 216 is a file specifically created to provide hardware designer (HD) engine 218 in the firmware generation layer 221 with the low level data necessary to build the created system level design into an embedded programmable system solution on a programmable image file 222 to be programmed on the selected processing device 106. In one embodiment, the processing device file 216 includes data pertaining to the locations in the low level database 220 for low level device drivers associated with one or more high level device drivers of the system level design in addition to all the appropriate links to the data required so the HD engine 218 may resolve the calls and functions. In various embodiments, the processing device file 216 may be HTML (hypertext markup language), XML (extended markup language), or any other format known in the art for structuring data in files.

An automation interface 212 is triggered by the PDM engine 208 and is configured to provide commands to launch the HD engine 218. These commands, among other things, instruct the HD engine 218 to find and open the processing device file 216 and perform the operations of low level code generation including pulling together all the necessary resources to compile and link the low level code to generate the programming image file 222. In various embodiments, the automation interface 212 provides the commands through a single command line string, a batch file, or a script file. In one embodiment, the automation interface 212 may be configured such that the PDM engine 208 is compatible with multiple HD engine types (e.g., different HD engine manufacturers) by altering the commands accordingly and updating the high level database 214 to reflect the device types associated with each of the multiple HD engine types.

Application code files 224 are custom files generated by the PDM engine 208 and include header files, ‘include’ files, and device driver information. The generated code in the application code files 224 is customized for the system level solution according to what device elements were called out by the user 102 and further includes code to control and operate the selected device elements. For example, the user 102 creates system level design that includes a temperature sensor controlling a fan with an LED status. The application code files 224 are generated creating a program to startup the fan based on device driver calls. Similar programs may be generated for the temperature sensor and the LED. In other words, the application code files 224 provide state information for the device elements of the system level design. In one embodiment, some or all of these functions are called out of a period task module or an event handler module. In one embodiment, the application code files 224 may be single file. In various embodiments, the application code files 224 may be generated in assembly programming language or in one of a multitude of variations of ‘C’ programming languages.

In one embodiment of the present invention, the HD engine 218 triggered by the commands received from the automation interface 212 assembles project data that includes a base project, lower level device drivers and user modules from the low level database 220 based on processing the low level design parameters described in the processing device file 216 and the operational code from the application code files 224. The HD engine 218 based on the project data builds the programming image file 222 that may be executed in the hardware layer 228 to program the embedded programmable system solution based on the system level solution created by the user 102.

The base project (not shown) is associated with the processing device 106 family chosen by the user 102. Base projects are one of the code elements comprised of metadata that are specific to the hardware platform chosen and set low-level hardware implementation details, such as the user modules required (which determine which kind of channels that can be supported) and the family and pin/package for the processing device. For example, to cover a family of devices having an 8, 20, 28, 44, and 48-pin package, five versions of the same base project would be required. Transparently to the user 102, a choice is made by the PDM engine 208 as to whether any or all of these can handle the system level solution defined by the user 102. For example, if the user 102 designs a simple 3 switch/3 LED design, all 5 base projects are presented, with the 8-pin presented as the top recommendation. In another example, if the user designs a 20 switch/20 LED design which requires 40 pins, only the 44 and 48 pin versions would be shown. In one embodiment, the base projects are designed and entered into the high level database 214 and/or the low level database 220 by processing device experts. In other embodiments, a base project synthesizer 230 dynamically creates the base projects by processing the project design file 210 to determine valid processing device configurations for the system level design. In various embodiments, the synthesized base projects may or may not be permanently or temporality stored in the high level database 214 and/or the low level database 220.

In one embodiment of the present invention, a device driver design domain 226 may provide scalability to the programming system 200. The user 102 or a third party processing device manufacturer could provide high level and low level design and driver information, and base project information that could be added to the high level database 214 and/or the low level database 220, respectively, through the device driver design domain 226. Any updated, added, or deleted processing device files and base projects would then be available for the validation of the system level solution created by the user 102, as described above. For example, the user 102 may have selected in the high level design a temperature sensor requiring successive approximation but the only processing device in the high level database 214 only includes delta sigma ADCs (analogue to digital converters) and therefore would not be on the list of available devices shown on the GUI of computer 104. However, upon updating the high level database 214 (and the low level database 220) to include successive approximation on that processing device or adding a new processing device that supports that feature, that updated device or the new device may now be included in the list available to the user 102.

FIG. 3 is a flowchart illustrating a process for programming a processing device based on a user created system level solution, according to one embodiment of the invention. Among various embodiments, some operations may be removed or become optional. At operation 302, a base project is selected by the PDM engine 208. As discussed above, the base project may be a static element stored in the high level database 214 and/or the low level database 220, or the base project may be dynamically created during the design process.

At operation 304, the drivers (e.g., temperature sensors, fans, LEDs) are assigned their respective channels in the project design file 210 by the PDM engine 208 according to the selected base project metadata. The PDM engine 208 selects a user module configuration, a set of user modules in a base project, and hardware and the software to configure the base project. The channel assignments bind the drivers to particular pins on the selected processing device. By virtue of the user module configuration, the drivers have access to the signals designated by the base project. The user module configuration is software that configures hardware to perform a peripheral function (e.g., a hardware counter or timer or a UART).

Optionally, at operation 306, some or all files associated with any previous build may be deleted by the PDM engine 308. This operation could be executed at any time for previous builds. In one embodiment, the files are deleted after the processing device 106 (processing device) has been programmed and the user session is closed on computer 104. However, the project design file 210 will be stored indefinitely unless manually deleted. This ensures that if base projects are changed, no conflicts would exist for any subsequent build since a new processing device file would be created, which included the new base projects, from the existing project design file 210. Additionally, this operation limits the amount of storage required to maintain the system level solution stored in the project design file 210.

At operation 308, the PDM engine 208 uses the automation interface 212 to send a command to the HD engine 218 to clone the selected base project to preserve the original base project for other future system level designs.

At operation 310, the PDM engine 208 uses the automation interface 212 to send a command to the HD engine 218 to generate the HD engine 218 source files based on the process design file 216 received from the PDM engine 208. This operation generates files consistent with the processing device configuration for the base project.

Project design source files are generated, at operation 312, by the PDM engine 208 in response to the project design file 210. The source file generation can be divided into three types: driver source files, variable transfer function source files, and system source files. For driver source files and variable transfer function source files, the source file generation follows a similar pattern. The file generation is based on instances indicated in the project design file 210. For drivers, the driver instances guide the driver source file generation. For variable transfer functions, function and variable instances guide the system transfer function source file. System source files are controlled by the files in the install path that are always generated regardless of the base project selection or project design file 210 content. Although system source files are always generated, their content is influenced by the project design file 210.

At operation 314, the HD engine 218 builds the programming image file 222 based on the embedded programmable system solution created by processing the combination of files that are created and retrieved in conjunction with the processing device file 216. The programming image file 222 represents the system level solution created by the user 102 to be programmed on the processing device 106.

FIG. 4 illustrates file types involved in processing device code generation, according to one embodiment of the present invention. The processing device (PD) code generation engine 402 may be part of the PDM engine 208 or may be its own module within the generic application layer 211. The file types make up a code generation file set 412, which includes a specification processing device file 404, fragment files 406, and template files 408. The specification processing device file 404 provides a file list for the PD code generation engine 402. The fragment files 406 provide a format for information as it is inserted into source files 410. The template files 408 provide the location for the fragments within each source file of the source files 410. The PD code generation engine 402 digests the project design file 210 and creates a set of keyword substitutions that replace known keywords with the data contained in the project design file 210. Special keywords are also used to collect keywords of a particular type.

In a first driver code generation operation, driver instances point to a code generation file set 412 based on the driver name. Each code generation file set 412 specifies the file list and fragments for that driver. In particular, a parameter block is defined such that a single copy of the driver functions can accommodate all instances of that driver type. The parameter block contains instance specific data as the channel assignment, driver property values, etc. The parameter blocks are collected and may be stored in ROM space so that RAM is conserved.

In a second variable transfer function code generation operation, variable transfer functions point to a code generation file set 412 based on the function selected. Each code generation file set 412 specifies the file list and fragments for that function. A parameter block is defined such that a single copy of the function source can accommodate all instances of that function. The parameter block contains instance specific data as the function input list, variant structures, and other data that vary with each instance of the function. The parameter blocks are collected and may be stored in ROM space so that RAM is conserved.

In a third system source file code generation operation, system source files (not shown) are those files that are always generated regardless of the project design file 210 content or the base project selected. They are influenced by the project design file 210 in that they include special collection keywords that gather the desired source lines in the designated location. In most cases, the collections are order independent. However, in the case of the transfer function evaluation, there are dependencies that exist between intermediate variables and output drivers that require a precise update order. In this case, the dependency order is calculated and the function calls are ordered accordingly.

In a fourth build project operation, the project is compiled and linked together to form a programming image file 222 (e.g., .hex file) used to program the processing device 106 (processing device). Due to the nature of the components combined and the processing device code generation, the firmware is error-free. Only system logic errors are relevant to the user, not microcontroller code errors. Therefore, for a valid project design file 210, all builds will be successful.

In a fifth bill of materials (BOM) and schematic creation operation, BOM and schematic data are derived from the driver channel assignments. From these assignments, pin assignments, driver schematic fragments, and BOM fragments are assembled. In one embodiment, the fragments are assembled for presentation via Web technologies into such files as HTML files. In other embodiments, the fragments may be assembled for presentation for various other platforms and applications (e.g., Adobe® .pdf, etc.)

In a sixth simulation and design verification operation, the user 102 may view and analyze the system behavior before the programming image file 222 is built. In one embodiment, the GUI displayed on computer 104 allows the user to view the system in real-time. In a first step termed simulation stimulus creation operation, simulation stimulus files are necessary to drive the inputs to the system under test. The stimulus file sets the input to the specified values at predetermined points so that the system behavior can be monitored. The stimulus file can be created in Excel™, or other spreadsheet program, and imported to the programming system 200. In a second step termed simulation code generation, the simulation code generation is analogous to code generation for the programming image file 222, except that the input and output driver functions are not needed. The driver functions are replaced by the input stimulus file for the input drivers, and by data logging for the output drivers. The remaining code generation is for the transfer functions only. The form of the code is also a scripting language, as Java™ script, instead of “C” language. The script is passed to the simulation engine where it is combined with the stimulus file for simulation execution. In a third step termed simulation execution/analysis, the simulation execution is real-time and can be logged to a file. In one embodiment of the present invention, the GUI of computer 104 shows widgets reacting to the stimulus file directly, and other widgets reacting to transfer function evaluation.

FIG. 5 is a flowchart illustrating a high level process for programming processing devices based on a user created system level solution, according to one embodiment of the invention. In one embodiment of the present invention, at operation 502, the programming system 200 automatically provides a user interface including a selectable list of one or more processing devices (e.g., a processing device such as a microcontroller or a circuit including a processing device) based on a system level solution created by the user 102. At operation 504, the programming system 200 automatically generates an embedded programmable system solution from the system level solution and a processing device 106 selected by the user 102. At operation 506, the programming system 200 automatically programs the processing device 106, selected from the one or more processing devices, according to the embedded programmable system solution.

Advantages of the improved method include that no embedded code development is required by the user, as all embedded code is generated automatically. Furthermore, no programmable device-specific knowledge is required, and consistent firmware with deterministic results is created. In addition, the GUI definition method provides easier definition of system design aspects and provides easier redefinition/modification of system design aspects in light of changing requirements. The GUI definition method also provides clearer presentation of system design aspects, and design verification is raised to system-level, rather than old method, firmware, device-specific, team-member subjective verification. One advantage is that firmware results are not dependent upon individual firmware engineer's skills or subjective approaches, and are not repeatedly rewritten for new requirements.

FIG. 6 illustrates a diagrammatic representation of machine in the exemplary form of a computer system 600 within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein. In alternative embodiments, the machine operates as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine may operate in the capacity of a server or a client machine in server-client network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a server computer, a client computer, a personal computer (PC), a tablet PC, a set-top box (STB), or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The exemplary computer system 600 includes a processor 602 (e.g., a central processing unit (CPU) a graphics processing unit (GPU) or both), a main memory 604 and a static memory 606, which communicate with each other via a bus 608. The computer system 600 may further include a video display unit 610 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)). The computer system 600 also includes an alphanumeric input device 612 (e.g., a keyboard), a cursor control device 614 (e.g., a mouse), a storage unit 616 (e.g., hard-disk drive), a signal generation device 618 (e.g., a speaker) and a network interface device 620.

The storage unit 616 includes a machine-readable medium 622 on which is stored one or more sets of instructions (e.g., software 624) embodying any one or more of the methodologies or functions described herein. The software 624 may also reside, completely or at least partially, within the main memory 604 and/or within the processor 602 during execution thereof by the computer system 600, the main memory 604 and the processor 602 also constituting machine-readable media. The software 624 may further be transmitted or received over a network 626 via the network interface device 620.

While the machine-readable medium 622 is shown in an exemplary embodiment to be a single medium, the term “machine-readable medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “machine-readable medium” shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present invention. The term “machine-readable medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical and magnetic media, and carrier wave signals.

Referring to FIGS. 3 and 5, although the embodiments of the processing device programming method is shown in the form of flow charts having separate blocks and arrows, the operations described in a single block do not necessarily constitute a process or function that is dependent on or independent of the other operations described in other blocks. Furthermore, the order in which the operations are described herein is merely illustrative, and not limiting, as to the order in which such operations may occur in alternate embodiments. For example, some of the operations described may occur in series, in parallel, or in an alternating and/or iterative manner.

It should be appreciated that reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Therefore, it is emphasized and should be appreciated that two or more references to “an embodiment” or “one embodiment” or “an alternative embodiment” in various portions of this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined as suitable in one or more embodiments of the invention.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7904878Feb 7, 2007Mar 8, 2011Vayavya Technologies Private LimitedSimplifying generation of device drivers for different user systems to facilitate communication with a hardware device
US8484616 *Jun 23, 2009Jul 9, 2013Emc CorporationUniversal module model
US20120296954 *May 16, 2011Nov 22, 2012International Business Machines CorporationSender motivated optimization of uri rendering in instant messaging
WO2009053777A2 *Oct 23, 2007Apr 30, 2009Maxim AdelmanMethod and system for pin assignment
Classifications
U.S. Classification358/1.13
International ClassificationG06F3/12
Cooperative ClassificationG06F8/38
European ClassificationG06F8/38
Legal Events
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Sep 17, 2013CCCertificate of correction
Oct 28, 2005ASAssignment
Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MCDONALD, JOHN;REEL/FRAME:017141/0040
Effective date: 20051024
Aug 10, 2005ASAssignment
Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PEARSON, JON;OGAMI, KENNETH;ANDERSON, DOUG;REEL/FRAME:016893/0157
Effective date: 20050810