US20060038746A1 - Low-Cost Lithography - Google Patents
Low-Cost Lithography Download PDFInfo
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- US20060038746A1 US20060038746A1 US11/163,864 US16386405A US2006038746A1 US 20060038746 A1 US20060038746 A1 US 20060038746A1 US 16386405 A US16386405 A US 16386405A US 2006038746 A1 US2006038746 A1 US 2006038746A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
Definitions
- the present invention relates to the field of integrated circuits, and more particularly to low-cost lithography.
- Lithography is the process of creating patterns in an IC layer. It involves mask fabrication, lithographic and related processes. With the advancement of integrated circuits, masks become more and more expensive. At the 0.13 ⁇ m node, a conventional mask costs ⁇ $30,000, and well over $100,000 for a phase-shift mask (PSM); a typical mask set costs ⁇ $1 million. For medium- to small-volume production, mask cost becomes a significant portion of the overall IC cost.
- the present invention particularly addresses the lithographic costs associated with opening-related patterns (e.g. inter-level connection and segmented-line), high-precision mask (e.g. OPC-mask and PSM), SCIC (semi-custom IC) and ASIC (application-specific IC), and others.
- Opening-related pattern refers to the pattern at which an opening is formed in the photoresist during its manufacturing process. There are many types of opening-related patterns in an integrated circuit. The most common ones are inter-level connections and segmented-lines.
- FIGS. 1A-1B illustrate a conventional inter-level connection (i.e. physical connection 50 va between upper- and lower-metal lines 162 , 174 ). It is a 1F-via 50 va , i.e. its dimension (Dv) is equal to or less than 1F, which is the minimum width (Dm, Dl) of metal lines 162 , 174 .
- the 1F-via requires precise control over the shape of the opening on the mask (mask opening). Accordingly, the mask fabrication needs expensive equipment (e.g. e-beam writing).
- this type of bordered via i.e. via 50 va is completely encompassed by the overlapping area of metal lines 162 , 174 ) has small overlay tolerance. It incurs a high processing cost.
- FIG. 1B B illustrates a segmented-line 161 S.
- a continuous line 161 C is illustrated in FIG. 1B A.
- This segmented-line 161 S comprises two segments 161 ′, 161 ′′ separated by a segment-gap 161 g .
- This segment-gap 161 g is, in fact, a form of opening (referring to FIG. 26 ). Note that the segments 161 ′, 161 ′′ have the same width and if the segment 161 ′ is extended to the right, it preferably coincides with the segment 161 ′′.
- High-precision masks such as OPC-mask (optical proximity correction) and PSM (phase-shift mask) are developed to extend optical lithography beyond the range of conventional imaging. Both provide the first-order correctional structures to mask patterns.
- the OPC adds serifs to mask features to recover the loss of shape fidelity due to diffraction and the PSM adds phase-shifter to mask features in such a way that pattern diffraction is partly cancelled. As a result, the imaged wafer patterns have more desired shapes.
- the correctional structures used by the OPC and the PSM are in direct contact with the zero-order pattern (the mask pattern that forms the majority portion the wafer pattern). Details on OPC and PSM can be found on “Silicon Processing for the VLSI Era”, Vol. 1, 2nd Ed., by Wolf and Tauber, pp. 628-37. Both techniques add significant cost to lithography.
- SCIC Semi-Custom Integrated Circuit
- SCIC In an SCIC, customers are only involved in the design of a limited number of layers. SCIC manufacturers stock a large number of base wafers. On base wafers, only transistor patterns are finished. Interconnects between transistors are not processed until customer inputs are received. There are two key concepts in SCIC: one is SCIC family; the other is SCIC product. A SCIC family comprises a number of SCIC products. In a SCIC product, all chips have the same transistor and interconnect patterns; in a SCIC family, all SCIC products have the same transistor pattern, but chips from different SCIC products may have different interconnect pattern.
- the patterns used in SCIC include common patterns and custom patterns: the common patterns are shared in a SCIC family and created by common masks; the custom patterns are only used in a single SCIC product and conventionally created by custom masks.
- one exemplary SCIC is read-only memory (ROM); in the logic world, one exemplary SCIC is programmable gate-array (PGA).
- FIGS. 1 CA- 1 CB if used in ROM, represent two ROM products: in FIG. 1C A, ROM cells 93 , 94 represent “0”, “1”, whereas, “1”, “ 0 ” in FIG. 1C B.
- 3D-ROM three-dimensional read-only memory
- FIGS. 1 CA- 1 CB the connections between metal lines are configured by vias. Accordingly, vias are referred to as config-vias. If used in PGA, the via configuration of FIGS. 1 CA- 1 CB creates two metal connections: in FIG. 1C A, horizontal line 162 is connected with vertical line 174 , whereas, in FIG. 1C B, it is connected with vertical line 173 .
- routings can be configured through metal-line segmentation.
- the gap 161 g will segment the metal line 161 S into two segments 161 ′, 161 ′′, each of which can be used for separate routing and has smaller capacitive load; on the other hand, if the metal mask of FIG. 1B A is used, the metal line 161 C will be a continuous line.
- the metal lines of FIGS. 1 BA- 1 BB can be used in different configurations.
- ASIC Application-Specific Integrated Circuit
- ASIC application specific integrated circuit
- all masks used in an ASIC product are custom masks.
- the large number of custom masks makes medium- to small-volume ASIC expensive.
- the fabrication of a conventional mask is similar to lithographic process in IC. First, photoresist is coated on mask blank, and exposed by e-beam. Then the undesired Cr film is etched away. It is time-consuming and expensive. For PGA, ROM and others, the mask-making should take advantage of the fact that typical openings in these devices are regularly sized and spaced. The opening masks for these devices can be made in a shorter time and at a lower cost.
- Optical discs such as CD, VCD, DVD, have a huge consumer market.
- An optical disc is fabricated by pressing a master optical disc on a disc blank.
- the fabrication of master optical disc is similar to the fabrication of mask in IC. It is time-consuming and expensive.
- the low-cost lithography disclosed in the present invention is based on two approaches: 1. Use low-precision mask (e.g. nF-opening mask) to implement high-precision pattern (e.g. opening-related patterns); 2. Improve the mask re-usability (e.g. with programmable litho-system and/or logic litho-system). To take full advantage of these techniques, “design-for-litho-programming (DFL)” is preferred.
- DFL design-for-litho-programming
- Low-cost lithography can be used in litho-programmable integrated circuits (e.g. litho-programmable SCIC and litho-programmable ASIC), as well as the fabrication of conventional masks and master optical discs.
- pattern-distribution enables the mask-repair by redundancy. It further enables highly-corrected mask, which provides higher-order correctional structures for clear patterns on wafer.
- the present invention discloses means for implementing high-precision pattern through low-precision (thus low-cost) mask.
- This approach is particularly suitable to implement opening-related patterns (e.g. inter-level connection and segmented-line).
- opening-related patterns e.g. inter-level connection and segmented-line.
- inter-level connection the dimension of the opening perpendicular to the upper metal line is controlled by the width of the upper metal line; the dimension of the opening along the upper metal line can be larger than the width of the lower metal line.
- the dimension of the opening i.e. segment-gap
- the dimension of the opening used in these patterns can be larger than the width of the metal line it interacts with.
- the opening dimension could be nF, with n>1.
- the nF-opening mask (n>1, feature size>1F) can be used to implement high-precision opening-related patterns (feature size ⁇ 1F). It offers the following benefits: 1. With a large feature size, the nF-opening mask costs less; 2. With a large toleration on the pattern shape, the nF-opening mask can be made with low-precision tools, even in-house with a conventional litho-tool; 3. The nF-opening mask can tolerate large alignment errors to the upper/lower-level metal patterns. The associated processing cost is lower.
- the inter-level connection manufactured from the nF-opening mask is referred to as aiv.
- damascene, particularly dual-damascene technique is preferably used.
- Dual damascene can take the form of embedded nf-opening, nF-opening-first-trench-second, trench-first-nF-opening-second.
- segmented-line can be implemented through litho-“OR” between an nF-opening mask and a continuous-line mask.
- a programmable litho-system can be used to improve the mask re-usability. Its core technology is a programmable mask. Being a “soft” mask, a programmable mask can adjust the pattern thereon based on a set of configuration data. Accordingly, the configuration data are coded into an image carrier (i.e. the object that receives the exposure light in a litho-tool, e.g. wafer, mask blank, or master disc. Unless being specifically mentioned, wafer is used as an example). Opening-programmable mask (OPM) is one type of programmable mask that is well suited to adjust the light intensity at openings.
- OPM Opening-programmable mask
- An OPM comprises at least an opening-defining plane (ODP) and a light-modulating plane (LMP).
- the ODP defines the final shape of openings on wafer; the LMP controls light intensity at said opening.
- the ODP and the LMP are located on separate surfaces. This arrangement offers more design freedom, better manufacturability and longer exposure endurance.
- the LMP comprises a plurality of light-modulating cells (LMC). They include liquid-crystal-LMC (LC-LMC), MEMS-type-LMC (MEMS-LMC), and emissive-LMC.
- LC-LMC and the MEMS-LMC can be either transmissive or reflective.
- the LC-LMC is similar to liquid-crystal display (LCD).
- the MEMS-LMC comprises at least one movable element, whose position controls the state of opening (“ON” or “OFF”).
- Typical movable elements are slider, rotor, roller-shade, digital micro-mirror, and digital light-valve.
- the emissive-LMC controls light emission at each cell.
- the LMC can be built in three-dimension (multi-level) to improve its density.
- the peripheral circuit of an LMC preferably comprises a transistor and may use technologies developed in SOI (e.g. backside grinding, smart-cut).
- wafer pattern is generated through a series of litho-logic operations between mask images.
- Typical litho-logic operations include litho-“OR” and litho-“AND”.
- Litho-“OR” can be implemented through multiple exposures on a wafer.
- Litho-“AND” can be implemented through multiple filterings to the exposure light.
- pattern-distribution wafer patterns are distributed on a plurality of mask, or in a plurality of mask regions on a single mask (a.k.a. pattern-distributed mask). After performing a litho-logic operation to the patterns from these masks (regions), the desired wafer pattern can be obtained. Pattern-distribution can be used to improve the mask re-usability. It can further enable the mask-repair through redundancy and highly-corrected masks.
- one portion of the circuit is quite mature (mature circuit), with another often subject to change (volatile circuit).
- a small circuit change translates to a costly new order for the whole mask.
- the wafer patterns can be distributed on two masks: one for mature circuit (mature mask) and the other for volatile circuit (volatile mask).
- the mature mask can be used in a number of products—an improvement of the mask re-usability.
- the data amount on the volatile mask is typically small and therefore, its fabrication is much less time-consuming and less expensive.
- Pattern-distribution enables the mask-repair through redundancy.
- the defective primary mask i.e. the mask supposed to carry the patterns to be formed on wafer
- the defect sites are first cleared on the primary mask then the correctional structures are formed in the cleared space. Because a typical mask is “feature-dense”, “repair-at-site” will likely damage the adjacent “known-good” mask features and therefore, is error-prone. The situation becomes even worse for the OPC-mask and the PSM.
- pattern-distribution Another important application of pattern-distribution is in the area of highly-corrected masks.
- prior arts because the features are closely spaced, there is not much space to accommodate higher-order correctional structures. This is no longer true to a pattern-distributed mask.
- the feature spacing on the pattern-distributed mask can be much larger than that on a conventional mask. This results in less proximity effect and less OPC-computing.
- the larger spacing between mask features can be used to accommodate highly-order correctional structures.
- the highly-corrected masks can achieve much better lithographic resolution.
- the highly-corrected mask can still be a binary mask. This can greatly simplify the mask fabrication.
- GPM general-purpose masks
- the GPM examples include uniform opening programming mask (UOPM) and uniform metal-line mask (UMLM).
- UOPM uniform opening programming mask
- UMLM uniform metal-line mask
- all programmable openings have the same size and same spacing, preferably 1F or 2F;
- UMLM uniform metal-line mask
- IC layout preferably follows “design-for-litho-programming (DFL)”.
- DFL design-for-litho-programming
- One set of DFL rules require that: a. any inter-level connection on a wafer should correspond to the location of a programmable opening on the UOPM; b. at least the metal lines inside the programming area has the same width and same pitch, preferably with a smaller or equal corresponding width than and equal or half corresponding pitch to the programmable openings on the UOPM.
- Composite litho-system combines programmable litho-system with logic litho-system. Besides programmable SoC and programmable lines, a composite litho-system enables the deep-sub- ⁇ m litho-programming based on manufacturable OPM. It can also improve the mask yield and offer longer exposure endurance to an OPM.
- the size of typical manufacturable LMC is ⁇ 5 ⁇ m. With R (image-reduction ratio of a reduction stepper) 4 ⁇ -5 ⁇ and assuming no ODP, the wafer opening could be as large as 1 ⁇ m. This is too large for any deep-sub- ⁇ m litho-programming. Fortunately, because the ODP opening is the opening that defines the final shape of the wafer opening, a small ODP opening size can make the final wafer opening small enough. However, the LMC size still dictates the wafer-opening period Pw. With a large Pw ( ⁇ 1 ⁇ m), not all wafer openings can be litho-programmed at once.
- a practical solution is to use a composite litho-system, where a multi-pass exposure with displacement is adopted (i.e. inter-leaved exposure).
- a multi-pass exposure with displacement i.e. inter-leaved exposure.
- a displacement ⁇ S is made to the wafer or to the mask before a second number of openings are exposed.
- the Pw requirement can be met.
- the litho-tools with large R e.g. 20
- Another practical solution is by twice-imaging (referring to section “Quasi-opening-programmable mask”).
- an OPM preferably goes through a field inspection to ensure a desired pattern is generated.
- An image sensor can be used for this purpose.
- a redundant mask region
- the OPM is well suited for this purpose.
- the OPM can endure long-term exposure. Between exposures, the location of the ODP is fixed, while the LMP is displaced. As a result, all regions on LMP are evenly heated and this prolongs the OPM lifetime.
- Low-cost lithography combines techniques such as nF-opening mask, programmable litho-system, and logic litho-system. It is ideal for the fabrication of litho-programmable integrated circuits (LP-IC).
- the LP-IC comprises a plurality of litho-programmable opening-related patterns (e.g. inter-level connections and segmented-lines). It can be implemented with an UOPM and optionally with an UMLM.
- UOPM litho-programmable opening-related patterns
- UOPM optionally with an UMLM.
- the overall expected revenue for this order which is the product of the order volume and the price quote, can be smaller than the cost of the conventional custom opening-mask set corresponding to said opening-related patterns (custom patterns).
- the completion of the same order involves making a new set of (conventional) custom masks.
- the manufacturing cost, including other processing and materials costs, should at least be higher than the cost for these masks. Namely, the overall expected revenue of the conventional (non-litho-programmable) IC cannot be lower than the mask cost.
- LP-IC litho-programmable SCIC
- LP-SCIC litho-programmable SCIC
- LP-SCIC litho-programmable SCIC
- LP-ROM litho-programmable ROM
- LP-PGA litho-programmable PGA
- LP-ASIC litho-programmable ASIC
- the LP-ASIC design needs to follow a more stringent ASIC-DFL: in at least one metal layer, metal lines are aligned along a first direction with their width and spacing preferably 1F; in a metal layer next to said metal layer, metal lines are aligned along a second direction with their width and spacing also preferably 1F.
- GPM's such as UOPM and UMLM, all interconnect patterns are formed. Shared in many LP-ASIC products, the GPM's add little cost to ASIC chip.
- QOPM quasi-opening programmable mask
- Low-cost lithography can also be used to fabricate master optical disc. This process is similar to that of the QOPM. Note that pits on the master optical disc are on a spiral. Between exposures, the disc needs to be rotated and displaced.
- the LP-IC preferably follows an internet business model, i.e. a customer send a set of customer data to the fab through internet.
- the customer data may comprise a file pointer.
- Said file pointer points to a file in a database, which the fab has fast access to.
- the prior-art ROM usually only stores “public” information (e.g. operating system).
- litho-programmable ROM LP-ROM
- the LP-ROM data sent to the fab are preferably encrypted.
- a decryption engine and a key storage are preferably formed on the same chip as the LP-ROM. After it is shipped back from the fab, user inputs the key to enable the chip. Thus, the key is not exposed to any third party, during the chip manufacturing or during the chip usage. This guarantees maximum data security.
- FIGS. 1 A- 1 CB illustrate several opening-related patterns used in prior arts.
- FIG. 2A illustrates a preferred nF-opening and its interaction with various metal lines
- FIG. 2B illustrates the core and peripheral portions of said opening on an nF-opening mask.
- FIGS. 3 AA- 3 BB illustrate several preferred aivs.
- FIGS. 4 AA- 4 CC illustrate several preferred dielectric structures used in aiv.
- FIGS. 5A-5D (including FIG. 5A ′) describe several preferred aiv processes based on the conventional metallization.
- FIGS. 6 A- 6 C′ describe several preferred aiv processes based on single damascene.
- FIGS. 7 AA- 7 CE′ describe several preferred aiv processes based on dual damascene.
- FIGS. 8 AA- 8 BC illustrate several preferred programmable litho-systems.
- FIGS. 9 AA- 9 BE illustrate the structures and relative placements of the LMP and the ODP in several preferred opening-programmable masks.
- FIGS. 10 AA- 10 CC illustrate the structures and peripheral circuits of a preferred liquid-crystal LMC (LC-LMC).
- LC-LMC liquid-crystal LMC
- FIGS. 11 A- 11 MD illustrate the structures and peripheral circuits for several preferred sliders.
- FIGS. 12 A- 12 EC illustrate the structures and peripheral circuits for several preferred rotors.
- FIGS. 13 AA- 13 CB illustrate the structures and peripheral circuits for several preferred hinges.
- FIGS. 14 A- 14 EB illustrate the structures and peripheral circuits of a preferred roller-shade LMC (RS-LMC).
- RS-LMC roller-shade LMC
- FIGS. 15A-15C illustrate the structures of several preferred reflective LMC's (R-LMC).
- FIG. 16B illustrate the structure and circuit symbol of a preferred emissive LMC (E-LMC).
- FIGS. 17 AA- 17 BC illustrate the structures of several three-dimensional LMC (3D-LMC).
- FIG. 18D describe a preferred process flow for a peripheral circuit in an LMC.
- FIG. 19C explains the concept of “OR” litho-system.
- FIGS. 20 AA- 20 EG illustrate several preferred “OR” litho-systems.
- FIGS. 21A-21C explains the concept of “AND” litho-system.
- FIGS. 22A-22B illustrate two preferred “AND” litho-systems.
- FIGS. 23 AA- 23 DC illustrate several preferred correctional structures for vias on a highly-corrected mask.
- FIGS. 24 AA- 24 BC illustrate several preferred correctional structures for line-spaces on a highly-corrected mask.
- FIGS. 25A-25C illustrate a preferred implementation of vias on an SoC chip through litho-“OR”.
- FIGS. 26 A- 26 FC describe several preferred implementations of segmented-lines through litho-“OR”.
- FIGS. 27 AA- 27 DB illustrate several preferred thin-film masks.
- FIGS. 28A-28B illustrate two preferred general-purpose masks (GPM).
- FIGS. 29 A- 29 BC describe several preferred “design-for-litho-programming (DFL)”.
- FIGS. 30 A- 30 CB illustrate several preferred programmable SoC opening patterns and preferred programmable line patterns.
- FIGS. 31 AA- 31 DC′ illustrate several preferred implementations of the litho-programmable deep-sub- ⁇ m openings through litho-“OR”.
- FIGS. 32 AA- 32 B illustrate several preferred implementations of the litho-programmable deep-sub- ⁇ m openings through litho-“AND”.
- FIGS. 33 AA- 33 FC illustrate several preferred mask-inspection and mask-repair means.
- FIGS. 34 AA- 34 BB illustrate a preferred OPM with long-term exposure endurance.
- FIG. 35 illustrates a preferred flow for a litho-programmable integrated circuit (LP-IC).
- LP-IC litho-programmable integrated circuit
- FIGS. 36 AA- 36 F illustrate several preferred implementations of litho-programmable ASIC.
- FIGS. 37A-37C illustrate a preferred implementation of a quasi-opening-programmable mask.
- FIGS. 38 A- 38 CB illustrate a preferred implementation of master optical disc.
- FIGS. 39 A- 39 BC illustrate several preferred business models for an LP-IC and a preferred litho-programmable ROM (LP-ROM).
- LP-ROM litho-programmable ROM
- FIG. 11 refers to FIGS. 11 A- 17 MD
- FIG. 11M refers to FIG. 11M A- 11 MD.
- low-precision masks can be used to implement high-precision opening-related patterns (e.g. inter-level connections and segmented-lines).
- Opening-related pattern refers to the pattern at which an opening is formed in the photoresist during its manufacturing process.
- FIG. 2A illustrates an opening 50 o . It can interact with metal line 162 (and 174 ) adjacent to it. If the metal lines 162 , 174 are on adjacent metal levels, the opening 50 o can form an inter-level connection between them; on the other hand, the opening 50 o can also segment the metal line 162 to form metal segments 162 l , 162 r . Accordingly, inter-level connection and segmented-lines are referred to as opening-related patterns.
- Wo, Lo of the opening 50 o can be larger than Dm, Dl of the metal lines 162 , 174 ( ⁇ 1F); for segmented-lines, Wo of the opening 50 o can larger than Dm of the metal line 162 ( ⁇ 1F).
- the dimension Wo (and Lo) of the opening pattern 50 o can be larger than the width Dm (and Dl) of the metal-line patterns it interacts with.
- the opening 50 o is referred to as nF-opening (with n>1, preferably 2).
- the nF-opening mask can use masks from the 0.25 ⁇ m node. Apparently, they are much less expensive.
- FIG. 2B illustrates the core portion 50 oc and the peripheral portion 50 op of the nF-opening 50 o on an nF-opening mask 50 om .
- the core portion 50 oc needs to be fully exposed.
- the peripheral portion 50 op there is little requirement on exposure dosage and image fidelity (as will become apparent as FIGS. 3 AA- 3 BB and FIGS. 26 A- 26 FC are explained).
- the nF-opening masks can be made in-house, even in a conventional litho-tool. That further lowers the mask cost and shortens the turn-around time.
- FIG. 3A A illustrates the relative placement of the nF-opening pattern vs. the upper-level metal pattern
- FIG. 3A B illustrates the relative placement of the nF-opening pattern vs. the lower-level metal pattern for two aivs 321 a , 322 a . Because the cross-sectional views along both the length and width directions of an aiv are shown therein, FIG. 3 and figures thereafter choose this aiv configuration to illustrate the invention.
- the length direction of an aiv is perpendicular to the upper-level metal line; the width direction is along the upper-level metal line.
- the nF-openings 321 , 322 provide inter-level connections between the upper-level metal line 311 and the lower-level metal line 331 , between the upper-level metal line 312 and the lower-level metal line 332 , respectively.
- the aiv pattern on wafer is the intersection of nF-opening pattern and upper-level metal pattern.
- FIG. 3A C illustrates the cross-sectional view of aivs 321 a , 322 a along A 1 -A 2 .
- the aiv width 2 wa is equal to the width 2 wm of the upper-level metal line 312 . Accordingly, at this direction, the precision of the aiv pattern is controlled by the upper-level metal mask.
- the aiv length 1 la is equal to the length 1 lo of the nF-opening 321 and it can be larger than the width 1 wl of the lower-level metal line 331 .
- the right edge lar of the aiv 321 a (corresponding to the right edge 1 r of nF-opening 321 in FIG. 3A A) does not touch the adjacent lower-level metal line 332 , circuit performance will not be affected much. Accordingly, the layout of nF-openings is very flexible.
- adjacent openings 50 oa , 50 ob can be combined into a merged opening 50 o 2 ( FIG. 3B A). It provides inter-level connection for the upper-level metal line 162 and two lower-level metal lines 174 , 175 .
- the merged aiv 50 a 2 is continuous ( FIG. 3B B).
- a standalone aiv 50 od i.e. not merged with other aivs
- the merged opening 50 o 2 can help further lower the mask cost.
- the inter-level connection is a bipolar connection (i.e. its resistance along both directions is low). It should be noted that, other forms of inter-level connections can also use the nF-opening mask. Examples include programmable inter-level connection (e.g. antifuse) and unipolar inter-level connection (i.e. its resistance is higher in one direction than in the other, e.g. 3D-ROM cell).
- aiv comprises an antifuse layer
- aiv comprises a ROM layer (a.k.a. quasi-conduction layer).
- the aiv length in these devices can also be larger than the width of the lower-level metal line, and the aiv width can be equal to the width of the upper-level metal line.
- Their manufacturing process can be similar to the (bipolar) inter-level connection of FIGS. 2 A- 3 BB.
- FIGS. 4 AA- 4 CC illustrate several preferred dielectric structures.
- FIGS. 4 AA- 4 AB illustrate several preferred lower-level dielectrics 400 l .
- FIG. 4A A it comprises a single, uniform dielectric 400 d 0 .
- FIG. 4A B it comprises at least two dielectric films 400 d 8 , 400 d 9 .
- the dielectric film 400 d 9 typically comprises low- ⁇ dielectric (e.g. silicon dioxide, SiLK).
- the dielectric film 400 d 8 can be used as an etchstop layer for the inter-level dielectric 400 a . It may comprise silicon nitride, high- ⁇ poly- or amorphous silicon.
- FIGS. 4 BA- 4 BC illustrate several preferred inter-level dielectrics 400 a .
- FIG. 4B A it uses a single, uniform dielectric 400 d 1 .
- FIG. 4B B it comprises two dielectric films 400 d 2 , 400 d 3 .
- the dielectric film 400 d 2 can be used as etchstop layer for the dielectric film 400 d 3 . It comprises silicon nitride, high- ⁇ poly- or amorphous silicon.
- the dielectric film 400 d 3 comprises low- ⁇ dielectric.
- the inter-level dielectric 400 a comprises three dielectric films 400 d 4 , 400 d 5 , 400 d 6 .
- Each dielectric film can be an etchstop layer for the film located thereon. Examples are: the dielectric film 400 d 5 comprises low- ⁇ dielectric; the dielectric films 400 d 4 , 400 d 6 comprise silicon nitride, high- ⁇ poly- or amorphous silicon.
- FIGS. 4 CA- 4 CC illustrate several preferred upper-level dielectrics 400 m .
- the upper-level dielectric 400 m comprises two dielectric films 400 d 11 , 400 d 12 .
- the dielectric film 400 d 12 can be used as a hard-mask for the dielectric film 400 d 11 . Examples are: the dielectric film 400 d 11 comprises low- ⁇ dielectric; the dielectric film 400 d 12 comprises silicon nitride, high- ⁇ poly- or amorphous silicon.
- the upper-level dielectric 400 m comprises three dielectric films 400 d 13 , 400 d 14 , 400 d 15 .
- Each dielectric film can be an etchstop layer for the film located thereon.
- Example are: the dielectric film 400 d 14 comprises low- ⁇ dielectric; the dielectric films 400 d 13 , 400 d 15 comprise silicon nitride, high- ⁇ poly- or amorphous silicon. Alternatively, the dielectric film 400 d 13 may comprise silicon nitride, etc; the dielectric film 400 d 15 may comprise high- ⁇ poly- or amorphous silicon.
- FIGS. 5 A- 7 CE′ illustrate several preferred aiv processes. They can be categorized according to the metallization process. They include conventional metallization, single damascene, and dual damascene.
- FIGS. 5A-5D (including FIG. 5A ′) describe several preferred aiv process flows based on conventional metallization.
- an inter-level dielectric 400 a is formed above, upon which the nF-opening pattern 340 a is transferred ( FIG. 5A ).
- a conductive film 310 m is formed ( FIG. 5B ).
- a conductive film 310 m forms upper-level metal lines 311 , 312 ( FIG. 5C ).
- an upper-level dielectric 400 m is filled in and planarized ( FIG. 5D ).
- FIG. 5A ′ is a variation of FIG.
- a tapered sidewall is formed in the inter-level dielectric 400 a ′. It facilitates the etch of the upper-level metal lines.
- the taper sidewall can also be used in other aiv structures.
- FIGS. 6 A- 6 C′ describe several preferred aiv process flows based on single damascene.
- a single damascene step is performed, i.e. a metal plug 400 p is formed in the nF-openings ( FIG. 6A ).
- a metal plug 400 p is formed in the nF-openings ( FIG. 6A ).
- the conductive film is then etched to form upper-level metal lines 311 , 312 .
- This etching step may remove a portion of the metal plug 400 p ( FIG. 6B ) or stop thereon ( FIG. 6B ′).
- the last step is the fill-in of an upper-level dielectric and planarization ( FIG. 6C , FIG. 6C ′).
- Dual damascene can take the form of embedded nF-opening (FIGS. 7 AA- 7 AF, including FIG. 7A A′ and FIG. 7A E′), nF-opening-first-trench-second (FIGS. 7 BA- 7 BH), and trench-first-nF-opening-second (FIGS. 7 CA- 7 CF, including FIG. 7C E′).
- FIGS. 7 AA- 7 AF illustrate a preferred aiv process based on dual damascene with embedded nF-opening.
- the name “embedded nF-opening” is derived from the fact that the nF-opening pattern is embedded between the inter-level dielectric 400 a and the upper-level dielectric 400 m .
- Its process flow is as follows. First, an inter-level dielectric 400 a is formed on the lower-level metal lines 331 , 332 ( FIG. 7A A). It may use the preferred dielectric of FIG. 4B C, i.e. it comprises three dielectric films 400 d 4 , 400 d 5 , 400 d 6 .
- the nF-opening pattern is transferred to the dielectric film 400 d 6 ( FIG. 7A B). Then an upper-level dielectric 400 m is formed. It may use the preferred dielectric of FIG. 4C A. This is followed by the pattern transfer of a trench mask 340 b ( FIG. 7A C). Then a series of etches are performed: a first etch removes the upper-level dielectric 400 m and the dielectric film 400 d 5 until the dielectric film 400 d 4 is reached ( FIG. 7A D); a second etch removes the remaining dielectric 400 d 4 until the lower-level metal lines 331 , 332 are reached. Thus, aiv 321 a , 322 a and trenches 311 t , 312 t are formed ( FIG. 7A E). At last, a conductive material is filled in and planarized ( FIG. 7A F).
- an etchstop layer 400 d 4 preferably covers the top surface of the lower-level dielectric 400 l (the preferred dielectric of FIG. 4B C), or there is an etchstop layer 400 d 8 along both sides of the top surface of the lower-level metal line 331 (the preferred dielectric of FIG. 4A B).
- FIG. 7A A′, FIG. 7A E′ illustrate an alternate preferred aiv process with embedded nF-opening.
- the inter-level dielectric 400 a and upper-level dielectric 400 m are both single, uniform dielectrics. Preferably they comprise different dielectrics (for example, 400 a comprises nitride, 400 m comprises oxide). Other processing steps are similar to those in FIGS. 7 AA- 7 AF.
- FIG. 7A the nF-opening pattern-transfer occurs between the formation of the inter-level dielectric and the upper-level dielectric.
- FIG. 7B and FIG. 7C all pattern transfers occur after these dielectrics are formed. The difference between FIG. 7B and FIG. 7C is the order in which the masks are applied.
- FIGS. 7 BA- 7 BH illustrate a preferred aiv process based on dual damascene with the nF-opening-first-trench-second.
- an inter-level dielectric 400 a and an upper-level dielectric 400 m are formed on the lower-level metal lines 331 , 332 ( FIG. 7B A).
- the inter-level dielectric 400 a uses the dielectric of FIG. 4B B
- the upper-level dielectric 400 m uses the dielectric in the first example of FIG. 4C C.
- the nF-opening patterns 321 , 322 are transferred to the dielectric film 400 d 15 ( FIG. 7B B).
- the etched dielectric film 400 d 15 can be used as a hard-mask for subsequent processing.
- a pattern-transfer is performed to a trench mask 340 b ( FIG. 7B C). This is followed by a series of etches: a first etch removes the exposed dielectric film 400 d 14 until 400 d 13 is reached ( FIG. 7B D); a second etch removes the exposed dielectric films 400 d 15 , 400 d 13 until 400 d 3 , 400 d 14 are reached ( FIG. 7B E); a third etch removes the exposed dielectric films 400 d 3 , 400 d 14 until 400 d 2 , 400 d 13 are reached ( FIG.
- FIG. 7B F photoresist is then removed and a fourth etch removes the exposed dielectric films 400 d 2 , 400 d 13 , 400 d 15 until 400 d 3 , 400 d 14 are reached ( FIG. 7B G).
- a conductive material is filled in and planarized ( FIG. 7B H).
- FIGS. 7 CA- 7 CF illustrate a preferred aiv process based on dual damascene with trench-first-nF-opening-second.
- an inter-level dielectric 400 a and an upper-level dielectric 400 m are formed on top of the lower-level metal lines 331 , 332 .
- the trench patterns 311 , 312 are transferred to the dielectric film 400 d 15 first ( FIG. 7C A).
- the nF-opening pattern 340 a is transferred to photoresist ( FIG. 7C B).
- the dielectric film 400 d 15 can be used as a hard-mask.
- a first etch removes the exposed dielectric film 400 d 14 until 400 d 15 is reached ( FIG. 7C C); a second etch removes the exposed dielectric film 400 d 13 until 400 d 3 , 400 d 15 are reached ( FIG. 7C C); then photoresist 340 a is removed and a third etch removes the exposed dielectric films 400 d 3 , 400 d 14 until 400 d 2 , 400 d 13 , 400 d 15 are reached ( FIG. 7C D); a fourth etch removes the exposed dielectric films 400 d 2 , 400 d 13 , 400 d 15 until 400 d 3 , 400 d 14 are reached ( FIG. 7C E). At last, a conductive material is filled in and planarized ( FIG. 7C F).
- a dielectric spacer 400 sp can be formed on the sidewall of the aiv and the trench ( FIG. 7C E′). Said dielectric spacer 400 sp ensures electrical isolation between the aiv and the adjacent lower-level metal line.
- a dielectric spacer can also be used in the damascene structures of FIGS. 5C, 6B , 6 B′, 7 AE, 7 AE′, 7 BG. In FIGS. 5C, 6B , 6 B′, the dielectric spacer is formed along both sides of the nF-opening; in FIGS. 7 AE, 7 AE′, 7 BG, it is formed along both sides of the aiv.
- etch-stop layers there are a plurality of etch-stop layers.
- timed etch could also be used.
- some etchstop layers may not be needed in the aiv structure.
- a programmable litho-system can be used to improve the mask re-usability. Its core technology is a programmable mask. Being a “soft” mask, a programmable mask can adjust the pattern thereon based on a set of configuration data. The configuration data are coded into an image carrier (i.e. the object that receives the exposure light in a litho-tool, e.g. wafer, mask blank, or master disc. Unless being specifically mentioned, wafer is used as an example). Opening-programmable mask (OPM) is one type of programmable mask that is well suited to adjust the brightness of openings.
- OPM Opening-programmable mask
- FIG. 8A A illustrates the flow of customer data 17 from a customer 12 to a fab 14 (e.g. a foundry).
- the customer data 17 can be encrypted or in plain-text. They are delivered to the fab 14 through a medium 18 .
- the medium 18 includes internet, hard-disk drive (HDD), optical disc and other means.
- the customer data 17 are converted into a set of configuration data 16 .
- the configuration data 16 are then hard-coded into the image carrier by the programmable litho-system 20 .
- FIG. 8A B illustrates the hierarchy of a programmable litho-system 20 . Its core portion is an OPM 30 .
- An OPM comprises at least an opening-defining plane (ODP) 32 and a light-modulating plane (LMP) 38 .
- the ODP 32 defines the final shape of openings on a wafer, while the LMP 38 controls the light intensity at said opening.
- the ODP 32 comprises a plurality of ODP openings 70 and the LMP 38 comprises a plurality of light-modulating cells (LMC) 40 .
- Each LMC 40 comprises a light-modulating area (LMA) 50 and a peripheral circuit 60 .
- LMA light-modulating area
- FIGS. 8 BA- 8 BC illustrate three preferred programmable litho-system: transmissive, reflective and emissive.
- a transmissive programmable litho-system 20 comprises a light source 26 , a transmissive OPM 30 t and a projector 24 . After the light passes through the OPM 30 t , its intensity varies according to the patterns on said OPM 30 t , which is controlled by the configuration data 16 .
- FIG. 8B B illustrates a preferred reflective programmable litho-system 20 . It is well suited for the litho-system using ultra-violet light (UVL). The light is modulated by a reflective OPM 30 r before being projected onto the wafer 22 .
- UVL ultra-violet light
- an emissive programmable litho-system comprises an emissive OPM 30 e .
- the emissive OPM 30 e comprises of a plurality of light-emitting cells. By selectively turning on or off these cells, the configuration data 16 can be passed to the wafer 22 .
- the emissive OPM 30 e is similar to the multiple parallel electron guns used in an e-beam litho-system. Besides optical light, X-ray, e-beam or ion beam can also be used in the programmable litho-systems.
- FIG. 9A A is a plan view of a LMP 38 . It controls the exposure intensity at openings 70 aa - 70 bb ( FIG. 9A B).
- the LMP 38 comprises a configuration-data bus 16 and a 2 ⁇ 2 light-modulating matrix.
- the light-modulating matrix comprises an array of LMC's 40 aa - 40 bb , a row-decoder 16 a and a column decoder 16 b .
- the LMC is the basic building block of LMP 38 .
- Each LMC 400 aa - 40 bb comprises an LMA 50 aa - 50 bb and a peripheral circuit 60 aa - 60 bb .
- the LMA has a dimension of D c , a spacing of S c and a period of P c . Its state is controlled by address line 42 a - 42 b and data line 44 a - 44 b .
- the LMA can transmit light (for the transmissive OPM 30 t ) or reflect light to a pre-determined direction (for the reflective OPM 30 r ); at its “OFF” state, it cannot.
- FIG. 9A B is a plan view of the ODP 32 . It defines the final shape of the opening on wafer. Every opening is aligned with and preferably encompassed by an LMA (e.g. 70 aa is aligned to 50 aa , referring to FIGS. 9 BA- 9 BE).
- the making of the ODP 32 is a standard mask-making process. It may use the advanced mask-making techniques, such as optical proximity correction (OPC) and phase-shift mask (PSM).
- FIGS. 9 BA- 9 BE the relative placements of several preferred ODP's and LMP's in an OPM are illustrated.
- a movable element—slider 51 a is used as example.
- the LMC 40 aa is at the “OFF” state; otherwise, it is at the “ON” state.
- FIG. 9B A the LMP 32 and the ODP 38 are merged and there is no physical distinction between them.
- FIGS. 9 BB- 9 BC the ODP 32 and the LMP 38 are located on separate surfaces.
- FIG. 9B B the ODP 32 and the LMP 38 are located at two sides of the mask substrate 36 .
- FIGS. 9 BC- 9 BE the ODP 32 and the LMP 38 are located on two different substrates 36 a , 36 b .
- the preferred embodiment in FIG. 9B D can be used in a reflective-OPM or an emissive-OPM.
- the ODP 32 performs light reflection at each opening 32 r ; the LMP 38 can be built on a light-absorptive membrane 36 m .
- the emissive-OPM For the emissive-OPM, the emissive plane 32 emits light at every opening 32 r ; the LMP 38 controls the intensity of light passing through.
- the preferred embodiment of FIG. 9B E can be used in a reflective-OPM. Compared with FIG. 9B D, the placements of the ODP 32 and the LMP 38 are exchanged.
- the movable element 51 a comprises a reflective film.
- the LMC in FIG. 9B E may use various preferred embodiments of FIGS. 15A-15C .
- LMC Light-Modulating Cell
- LMC is the basic building block of an OPM. It adjusts its light intensity according to the configuration data. It can borrow many design ideas and process ideas from the display industry.
- FIGS. 10 AA- 16 B illustrate the structures and peripheral circuits of various preferred LMC's.
- LC-LMC Liquid-Crystal LMC
- FIGS. 10 AA- 10 AB illustrate a preferred LC-LMC 40 .
- the LC-LMC 40 comprises a switch 60 s and a liquid-crystal LMA (LC-LMA) 50 . It is aligned with an ODP opening 70 and preferably encompasses it.
- the dashed ODP openings 70 shown in the LMC 40 is actually the projected image of the ODP opening 70 on the LMC 40 , in the case the OPD opening 70 and the LMC 40 are not located on the same plane.
- the LC-LMC 40 comprises two opposing substrates 36 e , 36 f , two opposing electrodes 59 p , 59 m , two alignment layers 36 b , 36 d and a liquid crystal layer 36 c .
- For the transmissive cell there are two opposing polarizers on both sides of the liquid crystal.
- light transmission through liquid crystal can be modulated by a voltage between the electrodes 59 p and 59 m .
- reflective LC-LMC can be used. Its material and manufacturing are well known in the art.
- the LC-LMA 50 can occupy most area of the LMC 40 ( FIG. 10A A).
- the circuit symbol representing the LC-LMC is a capacitor 50 c 0 ( FIG. 10B ). Its peripheral circuits are illustrated in FIGS. 10 CA- 10 CC.
- the peripheral circuit of FIG. 10C A is a dynamic circuit. It uses a DRAM-type circuit 60 dp . When the voltage on the address line 42 rises to high, the switch 60 s is turned on. The corresponding configuration bit 44 is sent to the capacitor 50 c 0 and determines the state of the LMC.
- FIGS. 10 CB- 10 CC are static circuits. For static circuits, leakage current in the capacitor will not affect the LMC state. This is particularly useful for long-term exposure (no refresh is needed).
- 10C B is an SRAM-type circuit 60 sp 1 . It comprises two switches 60 s , 60 sb and an SRAM cell formed by two inverters 60 i 1 a , 60 i 1 b . Its operation is similar to that of FIG. 10C A.
- the preferred circuit in FIG. 10C C uses a non-volatile-memory (NVM)-type circuit 60 sp 2 . It comprises a NVM cell 60 nvm and a switch 60 sp . Its operation includes two steps: a programming step and an exposure step. During the programming step (i.e. before exposure), the configuration bit is stored in the NVM cell 60 nvm .
- NVM non-volatile-memory
- the switch 60 sp is turned on, and voltages are applied to the address line 42 and the configuration-bit line 44 .
- the threshold voltage of the cell 60 nvm is varied according to the configuration bit.
- the capacitor 50 c 0 is first discharged.
- all address lines 42 and the configuration-bit line 44 are grounded with the switch 60 sp on.
- the switch 60 sp is turned off, and the voltages on all address lines 42 and the configuration-bit line 44 rise to appropriate values. If its threshold voltage is high, the NVM cell 60 nvm is still off and the capacitor 50 c 0 is not charged; if its threshold voltage is low, the NVM cell 60 nvm is on and the capacitor 50 c 0 becomes charged. As a result, the light passing through the LMC is modulated.
- MEMS-LMC can directly modulate the exposure intensity at each opening. At its “ON” state, because the exposure light does not have to pass any additional medium, its intensity loss is minimized.
- the MEMS-based programmable litho-system can achieve comparable throughput to a conventional litho-tool.
- the MEMS-based OPM is insensitive to the wavelength of the exposure light. It can be used in DUV, EUV, X-ray, e-beam, ion-beam and other litho-systems. Examples of MEMS-LMC include: slider, rotor, hinge, roller-shade, digital micro-mirror, and digital light-valve.
- FIGS. 11 AA- 11 MD illustrate various preferred translational light-modulating cells (T-LMC).
- Its core element is a slider 51 a .
- the slider 51 a is at the “OFF” state, i.e. it covers the opening 70 ; whereas in FIG. 11A B, the slider 51 a is at the “ON” state, i.e. it moves away from the opening 70 .
- the relative position of the four corners WXYZ of slider 51 a does not change during the movement.
- FIGS. 11 CA- 11 GC illustrate a first preferred T-LMC type.
- This preferred T-LMC type comprises a floating slider and its driving forces are capacitive.
- a first preferred embodiment of the first T-LMC type is illustrated in FIGS. 11 CA- 11 CC.
- the slider 51 a Besides the slider 51 a , it further comprises two flange pairs 51 p 1 a / 51 m 1 a and 51 p 1 b / 51 m 1 b . These two flange pairs cover the outer edge of the slider 51 a .
- the slider 51 a aligns with the first flange pair 51 p 1 a / 51 m 1 a .
- the slider 51 a aligns with the second flange pair 51 p 1 b / 51 m 1 b .
- the cross-sectional view along BB′, CC′ are illustrated in FIGS. 11 CB- 11 CC, respectively.
- the slider 51 a Being constrained by the flange pair 51 p 1 a / 51 m 1 a on both sides, the slider 51 a can only move along the y direction on the surface of the substrate 36 .
- the inner surfaces of the flanges 51 p 1 a , 51 m 1 a are lined with a dielectric 51 b , which prevents electrical shorting between the slider 51 a and the neighboring flanges 51 p 1 a , 51 m 1 a.
- FIGS. 11 DA- 11 DC illustrate a preferred manufacturing sequence for the first preferred embodiment of the first T-LMC type.
- a first sacrificial layer 51 s 1 and the slider layer 51 a are formed on substrate 36 . They are etched to form a first slider stack 51 t 1 ( FIG. 11D A).
- the slider layer 51 may comprise poly-silicon or metals such as aluminum.
- the sacrificial layer 51 s 1 may comprise silicon oxide; in the case of metals, the sacrificial layer 51 s 1 may comprise polymeric materials (e.g. photo-resist).
- a second sacrificial layer 51 s 2 is formed on top of the first slider stack 51 i 1 ( FIG. 11D B).
- the second sacrificial layer 51 s 2 is planarized. It may comprise the same material as the first sacrificial layer 51 s 1 .
- the second sacrificial layer 51 s 2 is etched to form a second slider stack 51 t 2 . This is followed by deposition of dielectric 51 b and the flange layer. They are etched to form flange pair 51 p 1 a / 51 m 1 a ( FIG. 11D C).
- the slider 51 a is released by removing the sacrificial layers 51 s 1 , 51 s 2 in an aqueous or plasma environment.
- FIGS. 11 EA- 11 EB illustrate several alternate preferred embodiments of the first preferred T-LMC type.
- an insulating spacers 51 c is formed along the vertical edges of the flanges 51 p 1 a , 51 m 1 a . It provides better electrical isolation between the slider 51 a and the flanges 51 p 1 , 51 m 1 .
- dimples 51 d are added to the under-edge of the slider 51 a . They reduce the friction between the slider 51 a and the substrate 36 . They can be fabricated by etching, preferably isotropically, a portion of the first sacrificial layer 51 s 1 before the slider layer 51 a is deposited.
- 11E C further discloses a preferred embodiment using comb-drives.
- a plurality of interleaved fingers 51 f 1 a , 51 f 1 b are attached to the slider 51 a . They increase the capacitive driving forces exerted on the slider 51 a . Thus, it would take less time for the slider 51 a to switch position. As a result, the throughput of the programmable litho-system can be improved. Hence, further improvement in throughput can be achieved if the comb-drives and the dimples are combined.
- FIG. 11F is a circuit symbol representing the preferred T-LMC illustrated in FIGS. 11 CA- 11 CC and FIGS. 11 EA- 11 EC. It comprises two capacitors 50 c 1 a , 50 c 1 b . Each flange pair forms a capacitor: the flange pair 51 p 1 a / 51 m 1 a forms a first capacitor 50 c 1 a ; the flange pair 51 p 1 b / 51 m 1 b forms a second capacitor 50 c 1 b .
- the slider 51 a is represented by a floating electrode.
- FIG. 11G A illustrates a preferred peripheral circuit. It uses a DRAM-type circuit and comprises a switch 61 s and an inverter 61 i .
- FIGS. 11 GB- 11 GC are static peripheral circuits. Except for the additional inverters 61 i , 61 i 1 b between two capacitors 50 c 1 a , 50 c 1 b , these peripheral circuits are similar to those in FIGS. 10 CA- 10 CC.
- FIGS. 11 HA- 11 I illustrate a second preferred T-LMC type.
- This preferred T-LMC type comprises a floating slider and its driving forces are both capacitive and elastic.
- FIG. 11H A is a first preferred embodiment of this type.
- the driving force for its “OFF” state is provided by the flange pair 51 p 2 , 51 m 2 .
- the driving force for its “ON” state is an elastic force, which is generated by a spring 51 sp .
- One end of the spring 51 sp is attached to the slider 51 a and the other to the substrate by an anchor 51 sa . After the driving capacitor is discharged, the elastic force of the spring 51 sp pulls the slider 51 a away from the opening 70 .
- FIG. 11H A is a first preferred embodiment of this type.
- the driving force for its “OFF” state is provided by the flange pair 51 p 2 , 51 m 2 .
- the driving force for its “ON” state is an elastic force, which
- FIG. 11H B illustrates a second preferred embodiment of this type.
- a comb-drive is used to increase the driving force for the “ON” state.
- FIG. 11I is the circuit symbol representing the second preferred T-LMC type. It is a capacitor 50 c 2 and can use the peripheral illustrated in FIGS. 10 CA- 10 CC.
- FIGS. 11 JA- 11 MD illustrate a third preferred T-LMC type.
- the slider in the third preferred T-LMC type is shorted to an external electrical signal.
- the driving forces for this T-LMC type are capacitive. It comprises a flange pair 51 e and two opposing electrodes 51 p 3 , 51 m 3 ( FIG. 11J A). Limited by the flange pair 51 e , the slider 51 a can only move along the y direction.
- FIG. 11J B is a cross-sectional view of the preferred embodiment along DD′.
- the T-LMC 40 comprises a base pair 51 g , which provides mechanical support as well as electrical contact to the slider 51 a .
- FIG. 11K illustrates the circuit symbol representing the third preferred T-LMC type. It comprises two capacitors 51 c 3 a , 51 c 3 b in series. The middle terminal corresponds to the slider 51 a .
- FIG. 11L is a preferred peripheral circuit. The two end terminals 51 p 3 and 51 m 3 are tied to VDD and GND, respectively. The voltage on the middle terminal 51 a is controlled by the configuration bit 44 .
- This peripheral circuit is a dynamic circuit. Static circuits in FIGS. 10 CB- 10 CC can also be used.
- FIGS. 11 MA- 11 MD illustrate a preferred process flow of the preferred embodiment in FIGS. 11 HA- 11 HB.
- an additional step is performed to form a base pair 51 g ( FIG. 11M A) before the first sacrificial layer 51 s 1 is formed.
- FIG. 12E C illustrate various preferred in-plane rotational light-modulating cells (IPR-LMC).
- Its core element is a rotor 52 a . All four corners STUV of the rotor 52 a can rotate around axle 52 b .
- the rotor 52 a covers the opening 70 , it is at the “OFF” state ( FIG. 12A ); when it rotates away from the opening 70 , the rotor 52 a is at the “ON” state ( FIG. 12B ).
- FIGS. 12 CA- 12 CC illustrate a first preferred IPR-LMC type.
- This preferred IPR-LMC type comprises a floating rotor and its driving forces are capacitive.
- the rotor 52 a is anchored to the substrate 36 by the axle 52 b . It is further extended on two edges to form two fingers 52 f 1 a , 52 f 1 b . These two fingers 52 f 1 a , 52 f 1 b act as the floating electrodes for two capacitors 50 c 4 a , 40 c 4 b (formed by two electrode pairs 52 p 1 a / 52 m 1 a , 52 p 1 b / 52 m 1 b , FIG. 12C A).
- FIG. 12C A FIG.
- FIG. 12C B is a cross-sectional view of the floating rotor 52 a and its axle 52 b along EE′. Limited by the flange 52 c on the axle 52 b , the rotor 52 a can only rotate in the x-y plane. Its inner surface is lined with a dielectric 52 d . It provides electrical isolation between the rotor 52 a and the axle 52 b .
- FIG. 12C C represents the circuit symbol for this preferred IPR-LMC type. It comprises two capacitors 50 c 4 a , 50 c 4 b .
- the rotor 52 a With a voltage on the capacitor 50 c 4 a but no voltage on the capacitor 50 c 4 b , the rotor 52 a is driven into the capacitor 50 c 4 a and covers the opening 70 . Accordingly, the IPR-LMC is at the “OFF” state. Otherwise, the IPR-LMC is at the “ON” state.
- the process flow for this preferred IPR-LMC type is similar to that in FIGS. 11 BA- 11 BC.
- FIGS. 12 DA- 12 DD illustrate a second preferred IPR-LMC type.
- the rotor is shorted to an external electrical signal and the driving forces are capacitive.
- the first preferred embodiment in FIG. 12D A and FIG. 12D B uses straight capacitor electrodes 52 p 2 , 52 m 2 . Their edges are lined with a dielectric 52 d . It provides electrical isolation between the electrodes 52 p 2 , 52 m 2 and the rotor 52 a .
- FIG. 12D C illustrates an alternate preferred embodiment of the second IPR-LMC type. Instead of straight capacitor, it uses fingered capacitor.
- the electrode fingers 52 f 2 a , 52 f 2 b form two capacitors 50 c 5 a , 50 c 5 b with the claw-like electrodes 52 p 2 and 52 m 2 . These fingered capacitors provide more driving forces to the rotor 52 a .
- the circuit symbol representing the second preferred IPR-LMC type is illustrated in FIG. 12D D. Its peripheral circuits are similar to those used by the third preferred T-LMC type.
- FIGS. 12 EA- 12 EC illustrate a preferred process flow for the preferred IPR-LMC of FIGS. 12 DA- 12 DB.
- a first sacrificial layer 52 s 1 and a rotor layer 52 a are deposited on substrate 36 . They are etched to form a rotor stack 52 t . Then a selective over-etch is performed on the sacrificial layer 52 s 1 . Not affecting the rotor layer 52 a , this over-etch creates an undercut underneath the rotor layer 52 a ( FIG. 12E A). Afterwards, a second sacrificial layer 52 s 2 is deposited around this structure and etched to expose a portion of substrate 36 ( FIG. 12E B).
- a flange layer 52 c and a capacitor finger 52 m 2 This is followed by the formation of a flange layer 52 c and a capacitor finger 52 m 2 .
- a dielectric 52 d is formed around the capacitor finger 52 m ( FIG. 12E C).
- FIGS. 13 AA- 13 CB illustrate various out-of-plane rotational light-modulating cells (OPR-LMC).
- Its core element is a hinge 53 a .
- the hinge 53 a rotates around a hub 53 h , which is confined by a staple 53 b .
- the four corners of the hinge 53 a are labeled as OPQR.
- the hinge 53 a lays on the substrate and covers the opening 70 (FIGS. 13 AA- 13 AB).
- the hinge 53 a rotates away from the opening 70 .
- FIGS. 13 BA- 13 BC illustrate a first preferred OPR-LMC.
- FIG. 13B A is its plan view and FIG. 13B B is its cross-sectional view along I-I′.
- the hinge 53 a rotates ⁇ 90° around its hub 53 h when it is switched from “OFF” to “ON” state.
- the hinge 53 a and the staple 53 b are both located on a base 53 c , which provides electrical connection to the hinge 53 a .
- the electrode 53 p 1 also acts as a stop that limits the degree of the hinge rotation. It comprises a post 53 ps and an arm 53 ar .
- the arm 53 ar is enclosed by a dielectric 53 d .
- This dielectric provides electrical isolation between the electrode 53 p 1 and the hinge 53 a .
- the circuit symbol representing this preferred embodiment comprises two capacitors 53 c 6 a and 53 c 6 b ( FIG. 13B C). They share one common electrode 53 a . Its peripheral circuits are similar to those of the third preferred T-LMC type.
- the process flow of this preferred embodiment is similar to the third preferred T-LMC type.
- a third sacrificial layer 53 s 3 is formed on top ( FIG. 13B D).
- a via is formed inside the third sacrificial layer 53 s 3 and filled with a conductor.
- the electrode 53 p 1 is formed. Finally, all sacrificial layers are removed and the whole structure is released.
- FIGS. 13 CA- 13 CB illustrate a second preferred OPR-LMC.
- FIG. 13C A is a plan view and FIG. 13C B is a cross-sectional view along J-J′.
- the hinge 53 a rotates ⁇ 180° from its “OFF” state to “ON” state.
- the electrodes 53 p 2 , 53 p 2 are more symmetrical.
- the circuit symbol and peripheral circuit for this preferred embodiment are similar to those of the first preferred OPR-LMC.
- FIGS. 14A-14C illustrate a preferred roller-shade LMC (RS-LMC).
- the roller shade 54 a covers the opening 70 and anchors to the substrate 36 by a flange 54 f ( FIG. 14A ).
- the roller shade 54 a further comprises at least two thermal layers 54 b , 54 c ( FIG. 14B ). They have different thermal expansion coefficients ⁇ .
- a resistor 54 r sits on the top surface of the roller-shade 54 a . When a current passes through the resistor 54 r and heats up the roller-shade 54 a , the ⁇ difference between the thermal layers 54 b , 54 c rolls up the roller-shade 54 a ( FIG. 14C ). Accordingly, the RS-LMC switches to its “ON” state.
- the roller-shade 54 a can be modeled as a two-terminal resistor 54 r ( FIG. 14D ). In its “ON” state, preferably a current runs through the roller-shade 54 a . Being resistive, its peripheral circuit is different from capacitive LMC.
- a first preferred circuit is illustrated in FIG. 14E A. Compared with the DRAM-style circuit in FIG. 10C A, the capacitor 50 c 0 is replaced by a PMOS 64 s 2 and a resistor 54 r . The gate voltage of the PMOS 64 s 2 controls the current flow through the resistor 54 r . Its operation is similar to FIG. 10C A except that the RS-LMC switches to “ON” state when 44 is low.
- FIG. 14E B illustrates a second preferred circuit. It comprises an NVM cell 64 nvm and its operation includes two steps. In the first step, the NVM cell 64 nvm is programmed by the configuration bit. At this time, the voltage on 64 g is high. This turns on the switch 64 s 4 but turns off 64 s 5 . Thus, no programming current flows through the resistor 54 r . In the second step, the state of the NVM cell 64 nvm translates to the current flow through the resistor 54 r . At this time, 64 g is grounded. This turns off the switch 64 s 4 but turns on 64 s 5 .
- FIG. 15C illustrate several preferred reflective LMC (R-LMC).
- R-LMC digital micro-mirror display
- DMD digital micro-mirror display
- DLV digital light valve
- FIG. 15C illustrate several preferred reflective LMC (R-LMC).
- R-LMC reflective LMC
- it comprises a reflector 55 a .
- On its four corners are four spring arms 55 sp and four anchors 55 sa .
- the cross-sectional views of these preferred embodiments along LL′ are illustrated in FIG. 15C , respectively.
- the top surface of the reflector 55 a can be coated with interleaved silicon-molybdenum layers.
- the first preferred embodiment is a DMD.
- FIG. 15C is a digital light valve.
- the reflector 55 a is a membrane. Portion of the incident light is reflected from its surface, with another portion being reflected by the substrate 36 (or the lower electrode 55 b ).
- the reflector 55 a is at location 55 C; with a voltage applied on the lower electrode 55 b , the reflector 55 a is pulled to location 55 D.
- the reflected light changes its intensity.
- reflective liquid-crystal can also be used for the R-LMC. Since its substrate is in the optical path, the peripheral circuit of liquid-crystal-based R-LMC can be built on a single-crystalline wafer. Meanwhile, the reflector 55 a can be stacked on top of the peripheral circuit. Accordingly, the reflector (LMA) area is close to the LMC area, i.e. the fill ratio is nearly ideal.
- FIG. 16B illustrate a preferred E-LMC.
- the core element in this E-LMC is a VCSEL 56 a . It comprises two opposing electrodes 56 p , 56 m , two opposing Bragg reflectors 56 e , 56 f , and p-i-n laser medium 56 c - 56 d .
- the VCSEL can be integrated with TFT's, which act as its peripheral circuit.
- the equivalent circuit of a VCSEL is a diode, which is a non-linear resistor ( FIG. 16B ). Its peripheral circuits are similar to those of RS-LMC. They can be built in silicon or GaAs wafers.
- Three-dimensional LMC (3D-LMC) can improve the LMC density.
- the MEMS structures are built in multiple levels and can overlap each other.
- the spacing between the LMC's can be reduced and the LMC's density be improved.
- FIGS. 17 AA- 17 AC, FIGS. 17 BA- 17 BC illustrate a preferred 3D-slider and 3D-rotor, respectively.
- FIGS. 17 AA- 17 AC illustrate a preferred LMC with 3D-slider. For the reason of simplicity, only the core element of the LMC is shown in these figures.
- FIG. 17A A two adjacent LMC's 40 x , 40 y are both in their “OFF” state.
- the LMC disclosed in the earlier portion of the present invention has only one slider.
- the LMC 40 x comprises two sliders 51 xa 1 , 51 xa 2 . Closing from its upper and lower sides, the sliders 51 xa 1 , 51 xa 2 cover the opening 70 x .
- the LMC 40 y has a similar structure. In FIG.
- the LMC's 40 x , 40 y are both at their “ON” state.
- the slider 51 xa 2 moves towards the lower side of the opening 70 x
- the slider 51 ya 1 moves towards the upper side. Since they are located at two different levels 51 A, 51 B, the sliders 51 xa 2 , 51 ya 1 can overlap each other ( FIG. 17A C). With a three-dimensional arrangement of the sliders, the spacing S o between the openings can be reduced and the OPM can achieve a high density.
- FIGS. 17 BA- 17 BC illustrate a preferred LMC with 3D-rotor. Only the core element is shown in these figures.
- FIG. 17B A two adjacent LMC's 40 x , 40 y are both in their “OFF” state.
- the LMC disclosed in the earlier portion of the present invention has only one rotor.
- the LMC 40 x comprises four rotors 52 xa 1 - 51 xa 4 . Closing from its four corners, the rotors 52 xa 1 - 52 xa 4 cover the opening 70 x .
- the LMC 40 y has a similar structure.
- FIG. 17B B the LMC's 40 x , 40 y are both at their “ON” state.
- the rotors 52 xa 3 , 52 xa 4 rotates ⁇ 90° around their respective axles 52 xb 3 , 52 xb 4
- the rotors 52 ya 1 , 52 ya 2 rotates ⁇ 90° around their respective axles 52 yb 1 , 52 yb 2 .
- the rotors 52 xa 3 , 52 xa 4 , 52 ya 1 , 52 ya 2 can overlap each other. With a three-dimensional arrangement of rotors, the spacing S o between the openings can also be reduced and the OPM can achieve a high density.
- the manufacturing of the OPM peripheral circuit may take advantage of the techniques developed in SOI (silicon-on-insulator) technology.
- SOI silicon-on-insulator
- the performance of the single-crystalline-silicon (sc-Si)-based TFT is better than ⁇ - or p-Si-based TFT.
- FIG. 18D illustrate a preferred process flow for a sc-Si-based peripheral circuit.
- the starting material is an SOI wafer 350 SOI ( FIG. 18A ). It comprises a substrate 350 s , a buried oxide film 350 o , and a silicon film 350 si .
- the SOI wafer 350 SOI has a first surface 350 us and a second surface 350 ls .
- a quartz substrate 352 is thermally adhered to the SOI wafer 350 SOI ( FIG. 18B ). Then the backside of the SOI wafer 350 SOI is ground from its second surface 350 ls until the buried oxide film 350 o is reached. This is followed by an etch of the buried oxide film 350 o , which exposes the silicon film 350 si (FIG. 18 C). As a result, an sc-Si film 350 si is formed on top of the quartz substrate 352 . This sc-Si film 350 si can be used as the substrate for the OPM peripheral circuit ( FIG. 18D ). Especially, other technologies developed in SOI (e.g. smart-cut) can also be used to form an sc-Si film on the mask substrate. Besides silicon, other semiconductor materials can also be used for peripheral circuits.
- SOI e.g. smart-cut
- wafer pattern is generated through a series of litho-logic operations between mask patterns.
- Litho-logic operation can be performed between conventional masks, between OPM's, or between conventional mask and OPM.
- Typical litho-logic operations include litho-“OR” and litho-“AND”.
- pattern-distribution wafer patterns are distributed on a plurality of mask, or in a plurality of mask regions on a single mask. After performing a litho-logic operation to the images from these masks (regions), the desired wafer pattern can be obtained. Pattern-distribution can be used to improve the mask re-usability. It can further enable the mask-repair through redundancy (referring to FIGS. 33 CA- 33 FC) and highly-corrected masks.
- FIG. 19C explain the concept of “OR” litho-system.
- FIG. 19B illustrate the images of mask patterns 88 AP, 88 BP projected on a wafer during exposure.
- FIG. 19C illustrates the final wafer pattern 88 OLP after the photoresist development, which is the union of the mask patterns 88 AP, 88 BP.
- This litho-logic operation is referred to as litho-“OR”.
- the reference point OA of the mask pattern 88 AP coincides with the reference point OB of the mask pattern 88 BP.
- FIGS. 20 AA- 20 EG illustrate several preferred “OR” litho-systems.
- the preferred embodiment in FIG. 20C may need only one exposure pass, while all others need two exposure passes (without photoresist development between exposures).
- the preferred embodiments in FIGS. 20 B- 20 EG are seamless multiple-exposure tools, i.e. mask patterns can self-align to each other during multiple exposures. It can achieve a higher throughput.
- FIGS. 20 AA- 20 AB use a conventional litho-tool 120 O 1 . It comprises a single projector. Two exposure passes 88 EA, 80 EB are performed to the same wafer 22 . During exposure pass 88 EA, the image of the mask 88 A (i.e. the mask pattern 88 AP) is projected on the wafer 22 ; during exposure pass 88 EB, the image of the mask 88 B (i.e. the mask pattern 88 BP) is projected on the wafer 22 ; and the wafer needs to be aligned between exposure passes. After all exposure passes are performed, photoresist is developed in a single step.
- the litho-tool 120 O 2 in FIG. 20B comprises two projectors 20 A, 20 B with a shared stage 21 M.
- a wafer 22 is exposed first to the projector 20 A. Then it steps forward and is exposed to the projector 20 B.
- the relative placement of the masks 88 A, 88 B can be controlled in such a way that, if it is aligned with the mask 88 A in the projector 20 A, the wafer 22 becomes self-aligned to the mask 88 B when it steps into the projector 20 B.
- the litho-tool 120 O 3 in FIG. 20C comprises two projectors 20 C, 20 D with a 50/50 beam splitter 24 s .
- half of the light entering the beam splitter 24 s is reflected with another half passing through.
- the image formed on the wafer 22 combines the images of the masks 88 A and 88 B, as the image of the mask 88 A passes through the beam splitter 24 s ; the images of the mask 88 B is reflected by the beam splitter 24 s .
- only one exposure (flash) may be needed. It is acceptable to expose another wafer 22 ′ at the same time on the other side 120 d of the beam splitter 24 s . This improves the throughput.
- a mask-steppable litho-tool 120 O 4 is used. It comprises one projector.
- the masks 88 A, 88 B are placed in a mask-holder 88 H and their relative placement is fixed. Besides precisely controlling the wafer stepping, this litho-tool 120 O 4 can precisely control the stepping of the mask-holder 88 H. Similarly, wafer alignment between exposure passes may not be needed.
- FIGS. 20 EA- 20 EG is an extension of FIGS. 20 DA- 20 DB. Similar to FIGS. 20 DA- 20 DB, it also uses a mask-steppable litho-tool 120 O 5 and comprises one projector. Unlike FIG. 20D A- 20 DB where the mask patterns 88 AP, 88 BP come from two masks 88 A, 88 B, in FIG. 20E C, the mask patterns 88 AP, 88 BP come from two mask regions 88 A′, 88 B′ of a SINGLE mask 88 . Accordingly, this mask 88 is referred to as pattern-distributed mask.
- a pattern-distributed mask that wafer patterns are distributed over a plurality of mask regions.
- at least one mask regions 88 A′, 88 B′ can nearly fill the full aperture 25 of the projector, and the combined range of these mask regions 88 A′, 88 B′ exceeds that of the full aperture 25 .
- the origin OA of the mask region 88 A′ also designated as the origin MO of the mask 88
- the control of the mask stepping can be simplified.
- the pattern-distributed mask 88 might be larger and heavier than a conventional mask. If gravitational sagging is a concern, a support beam 88 s may be added thereunder between the mask regions 88 A′, 88 B′. It provides mechanical support to the mask 88 and will not interfere with the lithographic process. Note that the support beam 88 s can be used in the preferred embodiments of FIG. 23A B, FIG. 24A B, and FIG. 33E A. For the reason of simplicity, it is not shown in these figures.
- the exposure process in the mask-steppable litho-tool 12 O 5 is similar to that in FIGS. 20 DA- 20 DB.
- Two exposure passes 80 EA, 80 EB are performed.
- the aperture 25 is aligned with the mask region 88 A′, e.g. OA coincides with the origin OO of the aperture 25 ( FIG. 20E D).
- Dies 38 a - 38 d are exposed one-by-one to the mask region 88 A′ ( FIG. 20E F).
- the aperture 25 is aligned with the mask region 88 B′, e.g. OB coincides with OO ( FIG. 20E E). Similar, dies 38 a - 38 d are then exposed one-by-one to the mask region 88 B′ ( FIG. 20E G).
- the wafer origins WO, WO′ coincide.
- a single development step forms wafer pattern.
- FIGS. 21A-21C explain the concept of “AND” litho-system.
- FIGS. 21A-21B illustrate the first and second mask patterns 88 AP, 88 BP.
- FIG. 21C illustrates the final wafer pattern 88 ALP, which is the intersection between mask patterns 88 AP and 88 BP.
- the litho-logic operation is referred to as litho-“AND”.
- the reference point OA of the mask pattern 88 AP coincides with the reference point OB of the mask pattern 88 BP.
- FIGS. 22A-22B illustrate two preferred “AND” litho-systems.
- FIG. 22A is a transmissive “AND” litho-system 120 A 1 . It uses two masks 88 A, 88 B, each having a first and second mask patterns 88 AP, 88 BP. The exposure light is filtered by both masks 88 A and 88 B. Images are only formed in areas where the mask patterns 88 AP and 88 BP are both clear.
- FIG. 22B is a reflective “AND” litho-system 120 A 2 . Images are only formed in areas where both the masks 88 A, 88 B are reflective.
- FIGS. 23 A- 24 BC illustrate several preferred highly-corrected masks.
- FIGS. 23 AA- 23 AC illustrate a pattern-distributed mask to implement high-density vias and its related lithographic process.
- FIG. 23A A illustrates the desired via patterns 18 SI on wafer. The via shown here only means that this is a possible via location. If it is drawn in solid line (e.g. 18 a ), the via exists; if it is drawn in dashed line (e.g. 18 b ), there is no via.
- the via dimension D v and spacing S v are ⁇ 1F
- a pattern-distributed mask 18 MS with four mask regions 18 D ( FIG. 23A B) and a logic litho-system employing four exposure passes can be used.
- the mask region 18 A only comprises via patterns 18 e ′, 18 g ′, 18 m ′, 18 o ′.
- An exposure sequence is detailed in FIG.
- the via spacing Sv 3 is ⁇ 3F. This is three times larger than that on a conventional mask.
- its via spacing could be (2n ⁇ 1) ⁇ larger than that on a conventional mask.
- the pattern-distributed mask provides several benefits: First, the proximity effect between adjacent features is much less. This translates to less OPC computing and lower mask cost. Secondly and more importantly, the larger feature spacing can be used to accommodate higher-order correctional structures, thus enabling highly-corrected masks.
- FIGS. 23 BA- 23 DC illustrate several preferred highly-corrected masks.
- FIGS. 23 BA- 23 BC illustrate a rim-shift PSM.
- via 18 g ′ is a zero-order clear pattern and the phase-shifter 18 ps around the via 18 g ′ is its first-order correctional structure.
- W cs is the spacing between the outer edge of the highest-order correctional structures and the outer edge of the zero-order clear pattern
- F/2 the width of the phase-shifter 18 ps
- W cs is the spacing between the outer edge of the highest-order correctional structures and the outer edge of the zero-order clear pattern
- the via spacing S v3 is much larger ( ⁇ 3F) and W cs increases by more than three-fold ( ⁇ 3F/2). Accordingly, the phase-shifter 18 ps can be better sized and better lithographic resolution can be achieved.
- FIGS. 23 CA- 23 CC and FIGS. 23 DA- 23 DC illustrate two masks 18 A, 18 A′ with second-order correctional structures.
- the second-order correctional ring 18 psa in FIGS. 23 CA- 23 CB is separated from via 18 g ′ by a spacer film 18 sf .
- the spacer film 18 sf may comprise chrome, phase-shifter or even just a trench. Although it may comprise phase-shifter, the correctional ring 18 psa in FIGS. 23 CA- 23 CB does not comprise phase-shifter and it is a clear pattern. Namely, the mask 18 A is a binary mask. Its fabrication is easier and costs less.
- the E-field 18 psa E from the second-order correctional ring 18 psa nearly cancels out the first-order diffraction maximum of the E-field 18 g E from the zero-order clear pattern (via 18 g ′).
- the final exposure light 18 c E can render a good profile.
- the preferred embodiments in FIGS. 23 DA- 23 DB comprises a first-order correctional ring 18 ps ′ and a second-order correctional ring 18 ps ′′ around the via 18 g ′.
- the first-order correctional ring 18 ps ′ may comprise a phase-shifter, and the second-order correctional ring 18 ps ′′ may not.
- the addition of E-field components 18 ps E′, 18 ps E′′ from these two correctional structures can almost completely cancel out the first-order diffraction maximum of the E-field 18 g E.
- the final exposure light 18 c E′ can render an excellent profile.
- this preferred embodiment is an example of the second-order Fresnel plate.
- the high-density line patterns 28 a - 28 c of FIG. 24A A can be distributed on a pattern-distributed mask 28 MS of FIG. 24A B.
- only clear patterns i.e. line-spaces (space between lines, a zero-order clear pattern) are distributed.
- the mask region 28 A comprises line-space pattern 29 a ′, 29 c ′, while the mask region 28 B comprises the remaining line-space pattern 29 b ′, 29 z ′.
- the exposure sequence follows that in FIGS. 20 EA- 20 EG.
- FIGS. 24 BA- 24 BC illustrate several preferred correctional structures.
- FIG. 24B A is similar to FIG. 23B A.
- Mask 28 MSP comprises a first-order correctional structure 29 ps (a phase-shifter) along the edges of the line-space 29 b ′. Its W cs can exceed F/2.
- mask 28 B in FIG. 24B B comprises a second-order correctional structure 29 psa . It is a binary mask.
- FIG. 24B C is similar to FIG. 23B C.
- Mask 28 B′ comprises first- and second-order correctional structures 29 ps ′, 29 ps′′.
- Logic litho-system can also improve the mask re-usability.
- wafer patterns can be distributed on at least two masks (or mask regions): one for mature circuit (mature mask) and the other for volatile circuit (volatile mask).
- litho-“OR” the desired wafer pattern can be formed.
- the mature mask can be used in a number of products—an improvement of its re-usability.
- the data amount on the volatile mask is typically small and therefore, its fabrication is much less time-consuming and less expensive.
- SoC System-on-a-Chip
- FIG. 25A illustrates the via patterns 80 SOC in an SoC chip (SoC via patterns), which comprises an on-chip MPIC 80 mp and an on-chip ASIC 80 as. Note that the via patterns in the MPIC 80 mp may change frequently.
- the SoC via patterns can be formed from two masks (or mask regions): an ASIC via mask 80 ASO ( FIG. 25B ) and an MPIC via mask 30 MPO ( FIG. 25C ).
- the ASIC via mask 80 ASO comprises ASIC via patterns 90 aa , 90 ab , 90 ba , but not MPIC via patterns 90 bb - 90 cc .
- the MPIC via mask 30 MPO comprises MPIC via patterns 90 bb - 90 cc , but not ASIC via patterns 90 aa , 90 ab , 90 ba .
- the desired SoC via pattern 80 SOC can be formed through litho-“OR” between the ASIC via mask 80 ASO and the MPIC via mask 30 MPO.
- other layer patterns in an SoC chip can be formed in the same way.
- segment-gap e.g. 161 g
- length of the segmented-lines 161 ′, 161 ′′ can be customized ( FIG. 26A ).
- the segmented-lines can be implemented through litho-logic operation on two masks (regions): a continuous-line mask and a segment-gap mask.
- FIGS. 26B-26C illustrate several preferred implementations.
- FIGS. 26B-26C illustrate a continuous-line mask 80 M and a segment-gap mask 80 G.
- the line patterns 161 , 162 on the continuous-line mask 80 M are dark patterns; the opening patterns 161 o , 162 o on the segment-gap mask 80 G are clear patterns. Their relative position on wafer is illustrated in FIG. 26C .
- these two masks 80 M, 80 G form the segmented-line pattern of FIG. 26A .
- the extension 161 o of the opening 161 o over the line 161 has no effect on the final shape of segment-gap. Accordingly, the shape of the openings 161 o can be quite flexible (referring to FIG. 2B ).
- FIGS. 26 DA- 26 DC A first preferred segmented-line process is illustrated in FIGS. 26 DA- 26 DC (along C 1 -C 2 of FIG. 26A ). It is based on conventional metallization.
- photoresist 18 pr is exposed to the continuous-line mask 80 M. That exposure exposes everywhere except areas 161 , 162 ( FIG. 26D A).
- photoresist 18 pr is exposed to the opening mask 80 G, when the area 161 (i.e. inside segment-gap 161 g ) is exposed ( FIG. 26D B). After development, only photoresist in the area 162 remains.
- a second preferred segmented-line process is based on damascene technique.
- damascene a trench needs to be formed before the metal-filling.
- a conventional trench mask 80 T ( FIG. 26E ) is complementary to the continuous-line mask 80 M and is not suitable for litho-“OR”.
- negative photoresist is preferably used during the lithographic process.
- the same mask set i.e. the continuous-line mask 80 M and the segment-gap mask 80 G
- the associated process flow (FIGS. 26 FA- 26 FC) is similar to that in FIGS. 26 DA- 26 DB, except that photoresist 18 pr is only removed in the area 162 but remains in all other areas. Apparently, this process flow results in the same segmented-line pattern as FIGS. 26 DA- 26 DC.
- Logic litho-system can also be used in thin-film mask (e.g. X-ray mask, e-beam mask).
- Thin-film mask is built on a fragile thin film (e.g. silicon nitride).
- support beams are desired under the thin-film mask.
- a pattern-distributed mask is to be used, i.e. wafer patterns are distributed over multiple mask regions. Within each mask region, there are invalid exposure areas. These invalid exposure areas contains can be used to build support beams.
- the final wafer patterns are formed by performing litho-logic operation on these mask regions.
- FIGS. 27 AA- 27 BB illustrate a first preferred thin-film mask. It comprises a first mask regions 135 A and a second mask region 135 B.
- FIGS. 27 AA- 27 AB are the plan view and cross-sectional views of the first mask region 135 A.
- Support beam 138 s 1 is built in the first mask region 135 A.
- the area within the support beam 138 s 1 is the invalid exposure area.
- the wafer patterns in the invalid exposure area reside on the second mask region 135 B.
- FIGS. 27 BA- 27 BB are the plan view and cross-sectional view of the second mask region 135 B.
- the patterns of the support-beams 138 s 2 , 138 s 3 complements the pattern of the support beam 138 s 1 .
- the mask patterns 137 b ′, 137 c on the second mask region 135 B and the mask patterns 137 a , 137 b on the first mask region 135 A form the desired wafer pattern.
- FIGS. 27 CA- 27 DB illustrate a second preferred thin-film mask.
- the invalid exposure area 138 s 1 ′ in the second preferred thin-film mask is defined by the mask pattern 138 s 1 ′, but not by the support beam 138 s 1 .
- the invalid exposure area 131 s 1 ′ is more accurately defined.
- GPM general-purpose masks
- DFL design-for-litho-programming
- GPM examples include uniform opening-programmable mask (UOPM) and uniform metal-line mask (UMLM).
- UOPM uniform opening-programmable mask
- UMLM uniform metal-line mask
- all programmable openings have the same size D o and same spacing S o , preferably 1F or 2F ( FIG. 28A );
- all metal lines are continuous and have the same width D m and same spacing S m , preferably 1F ( FIG. 28B ).
- One advantage of the UMLM is that it is highly regular and can fully utilize the advanced mask-making techniques such as alternative PSM.
- the IC layout preferably follows the DFL.
- the DFL includes via DFL and metal-line DFL.
- FIG. 29A A preferred via DFL is illustrated in FIG. 29A . It can be used to implement the SoC via pattern in FIG. 25A . Note that in FIG. 25A , the via 90 ba is not aligned with its adjacent vias. In order to use the UOPM 30 U, the via 90 ba has to be displaced by ⁇ so that it coincides with its nearest programmable opening 50 ba . Because the spacing S o between programmable openings is ⁇ 1F on the UOPM 30 U, ⁇ is no larger than ⁇ F/2. Namely, the via DFL has small effect on the via layout.
- segmented-lines requires the alignment of the continuous-line patterns 80 M and the segment-gap patterns 80 G.
- the segment-gap patterns 80 G can be generated by an UOPM 30 U. Accordingly, the continuous-line patterns, at least the continuous-line patterns subject to programming, can coincide with programmable openings on the UOPM 30 U. If the line 166 is wider than 1F ( FIG. 29B A), it is preferably split into a few sub-lines 168 , 169 ( FIG. 29B B) or at least a few sub-lines 166 a , 166 b in the programming area 166 pa ( FIG. 29B C).
- the width of these sub-lines is smaller than or equal to that of the programming openings, preferably equal to 1F; the pitch of these sub-lines is equal to the period of the programming openings, preferably 2F Combined with openings 50 bb , 50 cb , the desired segmented-lines can be generated.
- Composite litho-system combines programmable litho-system with logic litho-system. Besides programmable SoC and programmable lines, the composite litho-system enables the application of manufacturable OPM in advanced lithography. It can also improve the mask yield and offer longer exposure endurance to OPM.
- the MPIC via patterns are formed from a custom opening mask. In fact, it can be created from the OPM 80 MPO′ of FIG. 30A . In the ASIC area 80 as, all corresponding programmable openings are at the “OFF” state; only in the MPIC area 80 mp , the OPM 80 MPO′ generates valid opening patterns. Accordingly, the OPM 80 MPO′ offers programmability to SoC chips.
- Line patterns can be formed by merging a plurality of square openings and they can be programmable.
- FIG. 30B A illustrates a line pattern, i.e. merged opening 50 o 3 . It can be formed by a single OPM 30 O 3 in an “OR” litho-system. To be more specific, it can be formed by multi-pass exposures with displacement. Here, two exposure passes are performed and the OPM 30 O 3 is displaced relative to the wafer by ⁇ S between the exposure passes. The first exposure pass forms a first opening 50 oa ( FIG. 30B B); the second exposure pass forms a second opening 50 ob ( FIG. 30B C). These opening patterns are merged to form the desired line pattern 50 o 3 .
- FIGS. 31 CA- 31 DC′ More details on multi-pass exposure with displacement will be disclosed in FIGS. 31 CA- 31 DC′.
- the programmable line pattern can also be used to form gap 166 g in wide metal lines ( FIG. 29B A).
- FIGS. 30 CA- 30 CB two exposure passes are performed and the OPM is displaced relative to the wafer by ⁇ S between the exposure passes.
- the combined openings 50 bb , 50 bb ′ cut the wider metal line 166 .
- litho-programmable deep-sub- ⁇ m features ( ⁇ 0.25 ⁇ m) can be rendered by manufacturable OPM ( ⁇ 5 ⁇ m).
- FIGS. 31 AA- 32 B illustrate several preferred implementations of the litho-programmable deep-sub- ⁇ m openings through litho-logic operation.
- FIGS. 31 AA- 31 AB illustrate a preferred implementations of the litho-programmable deep-sub- ⁇ m openings through litho-“OR”. It uses two OPM's 30 Z, 30 W. Each OPM comprises a plurality of LMC's 40 z 1 - 40 z 3 , 40 w 1 - 40 w 3 .
- the LMC 40 z 2 on OPM 30 Z is always dark, with another two LMC's 40 z 1 , 40 z 3 programmable ( FIG. 31A A);
- the LMC's 40 w 1 , 40 w 3 on OPM 30 W are always dark, with another LMC 40 w 2 programmable ( FIG. 31A B).
- the pattern from each LMC's 40 z 1 - 40 z 3 is aligned to and combined with pattern from each LMC's 40 w 1 - 40 w 3 .
- the LMC 40 z 2 ( 40 w 1 , 40 w 3 ) is always dark, its counterpart LMC 40 w 2 ( 40 z 1 , 40 z 3 ) on the OPM 30 W ( 30 Z) can still program the corresponding wafer opening. As a result, every wafer opening is still programmable.
- the LMC 40 z 2 in FIGS. 31 AA- 31 AB is always set to dark. This can be easily accomplished by removing the ODP opening at this “always-dark” LMC 40 z 2 . Accordingly, no structure needs to be built for this “always-dark” LMC 40 z 2 and an adjacent LMC can extend into its area. Occupying more area, this adjacent LMC is easier to design and manufacture.
- FIG. 31B A illustrates a preferred LC-OPM 30 LOX whose LMC extends into the adjacent cells.
- LMC 401 a 3 extends to an adjacent “always-dark” LMC (such as 40 z 2 in FIG. 31A A). If it can extend to three “always-dark” LMC's, the dimension of this LC-LMC could be 2R ⁇ P wo . For a 0.25 ⁇ m opening and a conventional 4 ⁇ litho-tool, this value could be as large as 4 ⁇ m.
- the LMC of this size is highly manufacturable and reliable.
- the openings imaged on wafer are separately controlled by the ODP opening 70 la 3 , they can still be small and have fine features.
- FIG. 31B B illustrates a preferred MEMS-OPM 30 MOX whose LMC extends into the adjacent cells. Similarly, its LMC can use a larger, more manufacturable movable elements 51 a.
- FIGS. 31 AA- 31 BB In the preferred embodiments of FIGS. 31 AA- 31 BB, two OPM's 30 Z, 30 W are used. In fact, one OPM is all needed to form the desired wafer pattern.
- FIGS. 31 CA- 31 DC′ illustrate two preferred implementations. These implementations are based on multi-exposure with displacement. This method is also referred to as inter-leaved stepping.
- FIGS. 31 CA- 31 CC′ The preferred implementation in FIGS. 31 CA- 31 CC′ is based on a multi-exposure with mask displacement. It is similar to FIGS. 20 EA- 20 EB, except that mask in this embodiment is an OPM 38 .
- the OPM 38 coincides with the aperture 38 A of the litho-tool, and it has a first mask pattern 38 ( 80 EA) ( FIG. 31C A). Dies 38 a - 38 d on wafer 22 are exposed one-by-one to the first mask pattern 38 ( 80 EA) ( FIG. 31C B).
- the first exposure pass 80 EA exposes a first half of the wafer openings 78 za - 78 zh ( FIG. 31C C).
- the OPM 38 is displaced by ⁇ S ( ⁇ S is preferably equal to the mask opening period P o ) relative to the aperture 38 A, i.e. its origin moves from MO to MO′. Meanwhile, the OPM 38 acquires a second mask pattern 38 ( 80 EB) ( FIG. 31C A′). The second exposure pass exposes a second half of the wafer openings 78 za ′- 78 zh ′ ( FIG. 31C C′). Their state is determined by the second mask pattern 38 ( 80 EB). Note that, at the beginning of each exposure pass, the wafer origin WO makes no displacement ( FIG. 31C B′). With a single development step after all exposures, the desired opening pattern is formed on wafer.
- FIGS. 31 DA- 31 DC′ The preferred implementation in FIGS. 31 DA- 31 DC′ is based on a multi-pass exposure with wafer displacement.
- the OPM 38 has a first mask pattern 38 ( 80 EA) ( FIG. 31D A). Dies 38 a - 38 d on wafer 22 are exposed one-by-one to the first mask pattern 38 ( 80 EA) ( FIG. 31D B).
- the first exposure pass 80 EA exposes a first half of the wafer openings 78 za - 78 zh ( FIG. 31D C). Their state is determined by the first mask pattern 38 ( 80 EA).
- the OPM 38 acquires a second mask pattern 38 ( 80 EB) ( FIG.
- FIG. 31D A′ and a second half of the wafer openings 78 za ′- 78 zh ′ are exposed ( FIG. 31D C′). Their state is determined by the second mask pattern 38 ( 80 EB). With a single development step after all exposures, the desired opening pattern is formed on wafer. Compared with FIGS. 31 CA- 31 CC′, the first and second half openings 78 za - 78 zh , 78 za ′- 78 zh ′ here switch position. Note that during both exposure passes, the OPM 38 makes no displacement; however, at the beginning of each exposure pass, the wafer origin is displaced by ⁇ S (from WO to WO′), where ⁇ S is preferably equal to the wafer opening period P w .
- FIGS. 32 AA- 32 AB illustrate a preferred implementation of the litho-programmable deep-sub- ⁇ m openings through litho-“AND”. It comprises two LMP's 38 X, 38 Y. On the LMP 38 X, the LMA 50 x 2 is always clear, with another two LMA's 50 x 1 , 50 x 3 programmable ( FIG. 32A A); on the LMP 38 Y, the LMA's 50 y 1 , 50 y 3 are always clear, with another LMA 50 y 2 programmable ( FIG. 32A B). During exposure, two LMP's 38 X, 38 Y and an ODP 32 are aligned to each other. Wafer patterns are formed through litho-“AND” ( FIG.
- FIG. 32A C illustrates a preferred LC-LMP 38 LAX whose LMA 501 s 3 extends into the adjacent peripheral-circuit area. Its LMC is larger and more manufacturable.
- FIGS. 33 AA- 33 BB illustrate a field-inspectable programmable litho-system. It comprises an image sensor 30 v . It is placed into the exposure-light path after the OPM 30 t is configured but before the wafer 22 is exposed ( FIG. 33A A). Preferably, at the location of image sensor 30 v , the image from the OPM patterns has not been reduced by the litho-tool. Accordingly, the image sensors 30 v can use larger sensing cells. This will benefit the signal integrity and lower the sensor cost.
- the sensed signal 16 v (from the image sensor 30 v ) is compared with the configuration data 16 . If they match, the image sensor 30 v is removed from the exposure-light path and a wafer 22 is exposed ( FIG. 33A B); otherwise, the OPM 30 t needs to be checked.
- FIG. 33B A illustrates an OPM pattern during exposure. Based on the configuration data 16 , the light intensity on the LMC 50 sa ′- 50 sd ′ are varied; the ODP openings 70 sa ′- 70 sd ′ define the final shape of the wafer openings.
- FIG. 33B B is a preferred image sensor 30 v . It comprises a plurality of sensing cells 70 va ′- 70 vd ′ and a peripheral circuit 16 c .
- the sensing cells 70 va ′- 70 vd ′ can be based on conventional image-sensing techniques, such as CCD, CMOS imager.
- the peripheral circuit 16 c collects the sensed signal 16 v .
- the sensing cells 70 va ′ is aligned with the LMC 50 sa ′ ( FIG. 33A A), and preferably encompasses the pattern 70 pa ′ imaged by the ODP opening 70 sa ′ thereon.
- FIGS. 33 CA- 33 FC illustrate several preferred mask-repair means.
- FIGS. 33 CA- 33 CC illustrate a preferred mask-repair means based on litho-“OR”.
- the primary OPM 30 p works with a redundant OPM 30 r to form the desired wafer patterns.
- each redundant LMC i.e. the LMC on the redundant OPM 30 r , e.g. 40 r
- a primary LMC i.e. the LMC on the primary OPM 30 p , e.g. 40 _ 1
- the corresponding redundant LMC 40 r 2 is at the “OFF” state; for the defective primary LMC 40 _ 1 ( FIG.
- FIGS. 33 DA- 33 DB illustrate a preferred OPM with self-repair.
- the LMC 40 _ 1 on the OPM 30 is defective and is subsequently darkened; the LMC 40 _ 2 is non-defective.
- the OPM 30 is displaced relative to the wafer by ⁇ S and a redundant (second) exposure 20 R is performed.
- the image of the LMC 40 _ 2 formed on wafer is located at where the image of the LMC 40 _ 1 should have been during the primary exposure 20 P, and all LMC's corresponding to the non-defective primary LMC's are at the “OFF” state. Because the LMC 40 _ 2 carries the designated pattern for the defective LMC 40 _ 1 , the desired wafer patterns can be formed. The OPM self-repair needs only one mask.
- non-programmable (conventional) masks can be repaired based on pattern-distribution.
- the mask is repaired at the defect sites. Because a typical mask is “feature-dense”, this “repair-at-site” scheme will likely damage the adjacent “known-good” mask features and therefore, is error-prone. It is even more difficult to repair the PSM and OPC-masks.
- the present invention provides a “repair-through-redundancy” scheme for the defective mask.
- FIG. 33E A illustrates a pattern-distributed mask 88 . It comprises a primary mask region 88 P and a redundant mask region 88 R.
- the primary mask region 88 P comprises a plurality of darkened areas 40 _ 1 , 40 _ 3 . These darkened areas cover the defect sites and are preferably formed by, for example, filling a light-absorptive material 51 af on the defect sites ( FIG. 33E B).
- the redundant mask region 88 R comprises a plurality of correctional areas 40 r 1 , 40 r 2 . Each correctional area 40 r 1 corresponds to a darkened area 40 _ 1 in the primary mask region 88 P and it carries the designated patterns for the defect site 40 _ 1 ( FIG. 33E C).
- the patterns from these mask regions 88 P, 88 R are merged and form the desired pattern on wafer. It is to be understood that the primary mask region and redundant mask region can be located on two masks. Repair-through-redundancy is well suited to repair the PSM and OPC-mask.
- the OPM can also be used be repair a non-programmable mask.
- the advantage of the OPM-repair is that the OPM can be readily configured for the mask-repair purpose. This configuration step can be carried out in a short time. Accordingly, the field-repair for the defective opening masks becomes feasible.
- FIGS. 33 FA- 33 FC illustrate an alternate preferred mask-repair means based on litho-“AND”.
- the primary LMP 38 p comprises a defective LMC 40 _ 1 ( FIG. 33F A).
- the defect 51 ad ′ is cleared by, for example, a laser beam or FIB, and therefore, the LMC 40 _ 1 becomes always clear ( FIG. 33F B).
- a redundant LMP 38 r ′ is aligned with the primary LMP 38 p and the ODP 32 .
- the redundant LMC 40 r 1 ′ performs light-modulation for the defective primary LMC 40 _ 1 ; and other redundant LMC's corresponding to the non-defective primary LMC's are always at the “ON” state ( FIG. 33F C). This method can also be extended to the repair of non-programmable masks.
- FIGS. 34 AA- 34 BB illustrate a preferred method to avoid over-heating during the long-term exposure of an OPM.
- the LMP 38 LAX and the ODP 32 are located on two separate substrates. Between two exposures 20 E 1 , 20 E 2 , the LMP 38 LAX is displaced by MD while the location of the ODP 32 is fixed. Accordingly, during two exposures 20 E 1 , 20 E 2 to the LPM 38 LAX, the exposure light passes through different LMA areas 41 a , 41 b . Accordingly, each LMA area 41 a , 41 b receives less exposure-light intensity and the over-heating issue is alleviated. Because the location of the ODP 32 is fixed, the LMP displacement does not affect the final pattern formed on wafer.
- Low-cost lithography combines techniques such as nF-opening mask, programmable litho-system, and logic litho-system. It is ideal for the litho-programmable integrated circuits (LP-IC). Examples of LP-IC include litho-programmable SCIC (LP-SCIC) and litho-programmable ASIC (LP-ASIC). Low-cost lithography can also be used during the fabrication of conventional masks and master optical discs.
- LP-IC Litho-Programmable Integrated Circuits
- An LP-IC comprises a plurality of litho-programmable opening-related patterns (e.g. litho-programmable inter-level connections and litho-programmable segmented-lines). It can be implemented with an UOPM and optionally with an UMLM.
- litho-programmable opening-related patterns e.g. litho-programmable inter-level connections and litho-programmable segmented-lines. It can be implemented with an UOPM and optionally with an UMLM.
- UOPM litho-programmable opening-related patterns
- UOPM optionally with an UMLM.
- the completion of the same order involves making a new set of (conventional) custom masks.
- the manufacturing cost should at least be higher than the cost for these masks. Namely, the overall expected revenue of the conventional (non-litho-programmable) IC cannot be lower than the mask cost. Accordingly, the present invention differentiates the LP-IC from conventional IC through their expected revenues for a specific order.
- LP-IC litho-programmable SCIC
- LP-SCIC litho-programmable SCIC
- LP-SCIC litho-programmable SCIC
- LP-ROM litho-programmable ROM
- LP-PGA litho-programmable PGA
- LP-ASIC litho-programmable ASIC
- the front-end layers of LP-ASIC are fully customized, just like a conventional ASIC. This can reduce chip area and realize high-speed circuit.
- the back-end design needs to follow a more stringent ASIC-DFL: in at least one metal layer of the LP-ASIC, all metal lines are aligned along a first direction with their width and spacing preferably equal to 1F; in a metal layer next to said metal layer, all metal lines are aligned along a second direction with their width and spacing also preferably equal to 1F.
- GPM such as UOPM and UMLM
- all interconnect patterns can be formed without using custom masks.
- tens of custom masks are needed.
- these GPM's are shared in many LP-ASIC products, they add little cost to the ASIC chips.
- FIGS. 36 AA- 36 AB illustrate two preferred GPM's.
- FIG. 36A A illustrates a 2F-UOPM 30 U 2
- FIG. 36A B illustrates a 1F-UMLM 80 UM (also shown in FIG. 28B ).
- On the 2F-UOPM 30 U 2 its LMC size D o ′ and spacing S o ′ are equal to 2For at least around 2F
- the 2F-UOPM 30 U 2 has better manufacturability and can also implement segment-gaps and inter-level connections (referring to FIGS. 2A-2B ).
- the 1F-UOPM of FIG. 28A can be used.
- FIGS. 36 BA- 36 BC illustrate a preferred implementation of LP-ASIC using the GPM.
- the interconnects 00 as in FIG. 36B A are the typical interconnects encountered in an ASIC layout. They involve two metal levels and include a wide metal line 201 (with width equal to 2F), a bended line 203 / 203 ′ (its two sections 203 , 203 ′ are connected through via 203 v ), and a displaced line 202 (the line has a displacement along the x direction).
- a conventional process needs three custom masks, i.e. an upper-level metal mask, a lower-level metal mask and a via mask.
- the LP-ASIC only needs two GPM's, i.e.
- FIGS. 36 BB- 36 BC illustrate the LP-ASIC interconnects 00 lp equivalent to interconnects 00 as of FIG. 36B A.
- all upper-level metal lines 00 UM are aligned along the x direction
- all lower-level metal lines 00 LM are aligned along the y direction.
- FIG. 36B B uses two 1F upper-level metal lines 211 , 212 , which are shorted by the lower-level metal segments 221 ′, 222 ′ and a merged aiv 251 .
- FIG. 36B B stays the same.
- a conventional ASIC only uses a single lower-level metal line.
- the LP-ASIC segment along the x direction has to be implemented by the upper-level metal line 00 UM ( FIG. 36B B).
- the equivalence of the displaced line 202 includes three metal segments 222 ′′ (OOLM), 214 ′ (OOUM), 224 ′ (OOLM), and two aivs 253 , 254 .
- the UMLM 80 UM is placed along the y direction in the litho-tool.
- a first litho-“OR” is performed on the UOPM 30 U 2 (referring to FIGS. 26A-26C ).
- the UOPM 30 U 2 has a first opening configuration 230 LG (including openings 231 - 232 ) and its relative placement to the lower-level metal pattern (including metal lines 221 - 224 ) is illustrated in FIG. 36C A.
- the openings (e.g. 231 ) divide the metal lines (e.g. 221 ) into the segments (e.g. 221 ′, 221 ′′) of FIG. 36B B.
- the UMLM 80 UM is placed along the x direction in the litho-tool. Meanwhile, to realize the gaps between metal segments 213 ′ and 213 ′′, 214 ′ and 214 ′′, a second litho-“OR” is performed on the UOPM 30 U 2 .
- the UOPM 30 U 2 has a second opening configuration 240 UG (including openings 241 - 242 ) and its relative placement to the upper-level metal pattern (including metal lines 211 - 214 ) is illustrated in FIG. 36C B. Apparently, the openings (e.g. 241 ) divide the metal lines (e.g. 213 ) into the segments (e.g. 213 ′, 213 ′′) of FIG. 36B B.
- FIG. 36C C illustrates its third opening configuration 250 O (including openings 251 - 254 ) and its relative placement to the lower/upper-level metal patterns. These openings (e.g. 252 ) provide inter-level connections between the lower- and upper-level metal lines (e.g. 213 , 223 ). Note that all three opening patterns 230 LG, 240 UG, 250 O are generated by a single UOPM 30 U 2 .
- FIG. 36D illustrates an alternate preferred implementation of wide metal line 201 of FIG. 36B A. It uses a custom metal mask 80 CM.
- the desired metal line 201 is formed by performing litho-“AND” on said custom metal mask 80 CM and the UMLM 80 UM. During litho-“AND”, their relative placement is illustrated in FIG. 36D .
- the metal pattern 167 ′ is only needed at places corresponding to the wide metal lines 201 of FIG. 36B A, and its width only needs to be larger than the line-spacing 167 s ( ⁇ 1F).
- multi-exposure with displacement of FIGS. 30 CA- 30 CB can be used. Since the custom metal mask 80 CM only contains wide metal lines (>1F), which can tolerate large width and alignment error, the mask and processing costs are fairly low.
- FIG. 36E illustrates a preferred SoC chip 00 with an ASIC block 00 as and a plurality of functional blocks 00 fb .
- the functional blocks 00 fb usually contains IC blocks with third-party IP, such as memory blocks (RAM, ROM, etc) and processing blocks (CPU, DSP, etc).
- the SoC patterns can be implemented through litho-“OR” between two mask sets: one for the ASIC block 00 as (ASIC mask set), the other for the functional blocks 00 fb (functional-block mask set), as in the case of FIGS. 25A-25C .
- the ASIC mask set follows the LP-ASIC implementations.
- the functional-block mask set may be provided by IP-vendors, or may also follow the LP-ASIC implementations.
- FIG. 36F illustrates a preferred design flow of LP-ASIC. Similar to a conventional ASIC, it includes steps such as HDL description 00 H, netlist extraction 00 N, placement 00 P, routing 00 R, and tape-out 00 T. However, the routing 00 R of LP-ASIC needs to follow the ASIC-DFL. Moreover, only front-end layout needs to be taped out 00 T. The back-end output is not layout, but the state or location of openings. It has small data amount and can be delivered to the fab through the internet.
- QOPM Quasi-Opening Programmable Mask
- FIGS. 37A-37C illustrate a preferred process flow.
- FIG. 37A illustrates a preferred process flow to fabricate a QOPM from an OPM. It is similar to conventional lithographic process. However, the image carrier here is not a wafer, but a mask blank 80 SP coated with photoresist (QOPM blank).
- the QOPM 80 SP comprises a plurality of QOPM units 39 a - 39 p . Each QOPM unit corresponds to the exposure field of the OPM during one exposure.
- the QOPM blank 80 SP steps and the QOPM units 39 a - 39 p are exposed one-by-one with respect to the OPM 30 . Between exposures, the OPM patterns are adjusted based on the configuration data.
- the OPM 30 has a first pattern 30 ( 80 Ea) and the LMC 50 sb is at the “OFF” state ( FIG. 37B A); during the exposure 80 Eb to the QOPM unit 39 b , the OPM 30 has a second pattern 30 ( 80 Eb) and the LMC 50 sb is at the “ON” state ( FIG. 37B B). Accordingly, on the QOPM 80 SP, no opening is formed at location 72 b , and an opening is formed at location 72 b ′ ( FIG. 37C ).
- openings 72 b ′ is controlled by the ODP openings 70 sa - 70 sd , 70 sa ′- 70 sd ′.
- ODP openings 70 sa - 70 sd , 70 sa ′- 70 sd ′ can also be used during the fabrication of the QOPM.
- the LMC period P o on the OPM 30 is R times the opening period P q on the QOPM 80 SP. If a same litho-tool is used to expose the QOPM 80 SP to a wafer, P o can be R 2 times the wafer opening period P w .
- imaging twice first from an OPM to a QOPM, then from the QOPM to a wafer
- the image reduction ration from the OPM to the wafer is R 2 .
- the LMC can be 16 ⁇ -25 ⁇ larger than P w . For example, at the 0.13 ⁇ m node, an LMC could be ⁇ 5 ⁇ m.
- the LMC of this size is highly manufacturable and reliable.
- the QOPM openings have a size of ⁇ 1 ⁇ m.
- the openings of this size can be formed by a conventional optical litho-tool and configured by an LC-LMC (e.g. an off-shelf LCD from the micro-display industry). Accordingly, a QOPM can be fabricated in-house. It has a short turn-around time and offers better user-configurability. In sum, the QOPM is a very practical intermediate step for low-cost lithography.
- Low-cost lithography can also be used to fabricate master optical discs.
- This process is similar to the fabrication of the QOPM, except that the image carrier now is a master optical disc 86 D.
- the master optical disc 86 D is circular and has spiral tracks. The spacing between each turn of spiral is S s ( FIG. 38A ). Digital “0” and “1” is represented through the existence and absence of pits.
- An OPM 30 DM can be used to fabricate the master optical disc 86 D.
- the LMC's 50 da - 50 dg on the OPM 30 DM form an arc (FIGS. 38 BA- 38 BB). It controls the existence of pits within a degree ⁇ on the master optical disc. In this preferred embodiment, ⁇ is 90°.
- the master optical disc steps in a programmable litho-tool and is exposed one section after another. At each exposure, the OPM 30 DM adjusts its pattern according to the configuration data.
- the OPM 30 DM has a first pattern 30 DM( 80 EM 1 ) (e.g. the LMC 50 de is at the “ON” state) ( FIG.
- FIG. 38B A illustrates the disc section 86 DA and the disc section 86 DA is exposed.
- FIG. 38C A illustrates the position and orientation of the master optical disc 86 D during the exposure 80 EM 1 .
- the OPM 30 DM has a second pattern 30 DM( 80 EM 2 ) (e.g. the LMC 50 de is at the “OFF” state) ( FIG. 38B B) and the disc section 86 DB is exposed.
- FIG. 38C B illustrates the position and orientation of the master optical disc 86 D during the exposure 80 EM 2 .
- the master optical disc 86 D rotates around its origin 860 ( 80 EM 2 ) by ⁇ and displaced by ⁇ S (preferably equal to ⁇ /360° ⁇ S s ). In this preferred embodiment, at least four exposures are needed to form the whole master disc.
- the LP-IC preferably follows an internet business model. As is illustrated in FIG. 8A A, FIG. 35 and FIG. 39A , a customer 12 sends a set of customer data 17 to a fab 14 through a medium 18 , such as internet. In the fab 14 , wafers are preferably constantly exposed in a programmable litho-systems. Once a new order is received, the customer data 17 are processed by a data-processing unit 15 and converted into a set of configuration data 16 . The configuration data 16 are issued to the OPM and then coded into the wafer-under-exposure. Thus, the customer 12 has direct, remote and real-time control.
- the owners want to hide from the customers can be stored in a database 1 ddb at or near the fab 14 .
- the customer 12 sends pointers 1 pa , 1 pc associated with these files (e.g. by clicking a web-page 12 t ) and the data-processing unit 15 will fetch these files from the database 1 ddb .
- the upload time is more acceptable.
- the customer data 17 can be compressed.
- FIG. 39B A illustrates the data flow for a preferred secure LP-ROM.
- the customer Before sending it to the fab, the customer encrypts the customer data 17 at an encryption unit 4 e with a key 7 k . Subsequently, only encrypted data 17 ed are sent to the fab. The fab 14 plainly codes these data into a LP-ROM chip 9 , without any knowledge of their representation. After receiving chip 9 , the customer inputs the key 7 k and enables the chip 9 . As a result, the key 7 k never falls out of the customer's hands and excellent information security can be achieved during the chip manufacturing.
- a decryption engine 4 d and a key storage 7 m can be built on the same chip as the LP-ROM chip 9 .
- Three-dimensional read-only memory (3D-ROM) is well suited for this purpose.
- the 3D-ROM cells 101 - 103 are located above the substrate 00 and they do not occupy silicon real estate. Accordingly, the substrate 00 can accommodate a large number of transistors 5 and NVM 7 . They can be used to form the decryption engine 4 d and the key storage 7 m ( FIG. 39B C).
- the decryption process can be completely carried out inside the 3D-ROM chip 9 .
- the decrypted data 17 o can be directly forwarded to other functional blocks on the chip, such as D/A converter.
- the key is not exposed to the external world and excellent information security can be achieved.
Abstract
The low-cost lithography disclosed in the present invention lowers the lithographic cost by improving the mask re-usability, e.g. by using programmable litho-system and/or logic litho-system. The programmable litho-system, with an opening-programmable mask, can adjust its image patterns based on configuration data. The logic litho-system can combine image patterns from at least two mask regions into a single image on a wafer or a mask blank.
Description
- This patent application is a division of U.S. patent application Ser. No. 10/230,610, Filed Aug. 28, 2002. Said patent application Ser. No. 10/230,610 is related to the following domestic patent applications:
-
- 1. “Opening-Programmable Integrated Circuits”, provisional application Ser. No. 60/326,919, filed on Oct. 2, 2001;
- 2. “Litho-Programmable Integrated Circuits”, provisional application Ser. No. 60/339,334, filed on Dec. 13, 2001;
- 3. “Low-Cost Lithography”, provisional application Ser. No. 60/395,099, filed on Jul. 10, 2002,
- and the following foreign patent applications:
-
- 1. “Design of Three-Dimensional Read-Only Memory”, CHINA P. R., patent application Ser. No. 02113333.6, filed on Feb. 5, 2002;
- 2. “Programmable Litho-System and Applications”, CHINA P. R., patent application Ser. No. 02113475.8, filed on Mar. 20, 2002;
- 3. “Logic Litho-System and Applications”, CHINA P. R., patent application Ser. No. 02113476.6, filed on Mar. 20, 2002;
- 4. “Design, Fabrication and Business Model of Litho-Programmable Integrated Circuits”, CHINA P. R., patent application Ser. No. 02113477.4, filed on Mar. 20, 2002;
- 5. “Methods to Lower the Mask Cost in an Integrated Circuit”, CHINA P. R., patent application Ser. No. 02113792.7, filed on May 28, 2002;
- 6. “Logic Litho-System”, CHINA P. R., patent application Ser. No. 02113836.2, filed on Jun. 6, 2002;
- 7. “Litho-Programmable Application Specific Integrated Circuits”, CHINA P. R., patent application Ser. No. 02133303.3, filed on Jun. 18, 2002,
- all by the same inventor.
- 1. Technical Field of the Invention
- The present invention relates to the field of integrated circuits, and more particularly to low-cost lithography.
- 2. Related Arts
- Lithography is the process of creating patterns in an IC layer. It involves mask fabrication, lithographic and related processes. With the advancement of integrated circuits, masks become more and more expensive. At the 0.13 μm node, a conventional mask costs ˜$30,000, and well over $100,000 for a phase-shift mask (PSM); a typical mask set costs ˜$1 million. For medium- to small-volume production, mask cost becomes a significant portion of the overall IC cost. The present invention particularly addresses the lithographic costs associated with opening-related patterns (e.g. inter-level connection and segmented-line), high-precision mask (e.g. OPC-mask and PSM), SCIC (semi-custom IC) and ASIC (application-specific IC), and others.
- Before proceeding further, a clarification needs to be made here: the size, dimension, width, length used throughout this disclosure could be either a size, dimension, width, length on wafer, or a size, dimension, width, length on mask. They are, in general, not specified, but should become apparent from the context. For example, no extra efforts have been made to distinguish the minimum feature size on wafer Fw from the corresponding minimum feature size on mask Fm (Fm=Fw×R, where R is the image-reduction ratio of the reduction stepper). They are both referred to as F throughout this disclosure. In the context of wafer pattern (patterns on wafer), F means Fw; in the context of mask pattern (patterns on mask), F means Fm.
- 1. Opening-Related Patterns
- Opening-related pattern refers to the pattern at which an opening is formed in the photoresist during its manufacturing process. There are many types of opening-related patterns in an integrated circuit. The most common ones are inter-level connections and segmented-lines.
-
FIGS. 1A-1B illustrate a conventional inter-level connection (i.e.physical connection 50 va between upper- and lower-metal lines 162, 174). It is a 1F-via 50 va, i.e. its dimension (Dv) is equal to or less than 1F, which is the minimum width (Dm, Dl) ofmetal lines metal lines 162, 174) has small overlay tolerance. It incurs a high processing cost. -
FIG. 1B B illustrates a segmented-line 161S. As a comparison, acontinuous line 161C is illustrated inFIG. 1B A. This segmented-line 161S comprises twosegments 161′, 161″ separated by a segment-gap 161 g. This segment-gap 161 g is, in fact, a form of opening (referring toFIG. 26 ). Note that thesegments 161′, 161″ have the same width and if thesegment 161′ is extended to the right, it preferably coincides with thesegment 161″. - 2. High-Precision Mask
- High-precision masks such as OPC-mask (optical proximity correction) and PSM (phase-shift mask) are developed to extend optical lithography beyond the range of conventional imaging. Both provide the first-order correctional structures to mask patterns. The OPC adds serifs to mask features to recover the loss of shape fidelity due to diffraction and the PSM adds phase-shifter to mask features in such a way that pattern diffraction is partly cancelled. As a result, the imaged wafer patterns have more desired shapes. The correctional structures used by the OPC and the PSM are in direct contact with the zero-order pattern (the mask pattern that forms the majority portion the wafer pattern). Details on OPC and PSM can be found on “Silicon Processing for the VLSI Era”, Vol. 1, 2nd Ed., by Wolf and Tauber, pp. 628-37. Both techniques add significant cost to lithography.
- 3. Semi-Custom Integrated Circuit (SCIC)
- In an SCIC, customers are only involved in the design of a limited number of layers. SCIC manufacturers stock a large number of base wafers. On base wafers, only transistor patterns are finished. Interconnects between transistors are not processed until customer inputs are received. There are two key concepts in SCIC: one is SCIC family; the other is SCIC product. A SCIC family comprises a number of SCIC products. In a SCIC product, all chips have the same transistor and interconnect patterns; in a SCIC family, all SCIC products have the same transistor pattern, but chips from different SCIC products may have different interconnect pattern. The patterns used in SCIC include common patterns and custom patterns: the common patterns are shared in a SCIC family and created by common masks; the custom patterns are only used in a single SCIC product and conventionally created by custom masks. In the memory world, one exemplary SCIC is read-only memory (ROM); in the logic world, one exemplary SCIC is programmable gate-array (PGA).
- In a ROM, memory cell could be located at the intersection of horizontal and vertical metal lines. The bit stored in a memory cell is represented through the existence or absence of a via. Accordingly, vias are referred to as info-vias. The via configurations of FIGS. 1CA-1CB, if used in ROM, represent two ROM products: in
FIG. 1C A,ROM cells FIG. 1C B. One ROM of particular interest is three-dimensional read-only memory (3D-ROM), which is disclosed in U.S. Pat. No. 5,835,396. In the 3D-ROM, there is a 3D-ROM layer (a.k.a. quasi-conduction layer) between said vertical and horizontal lines (referring to FIG. 4 of U.S. Pat. No. 5,835,396). - In PGA, the connections between metal lines are configured by vias. Accordingly, vias are referred to as config-vias. If used in PGA, the via configuration of FIGS. 1CA-1CB creates two metal connections: in
FIG. 1C A,horizontal line 162 is connected withvertical line 174, whereas, inFIG. 1C B, it is connected withvertical line 173. - In PGA, routings can be configured through metal-line segmentation. For example, if the metal mask of
FIG. 1B B is used, thegap 161 g will segment the metal line 161S into twosegments 161′, 161″, each of which can be used for separate routing and has smaller capacitive load; on the other hand, if the metal mask ofFIG. 1B A is used, themetal line 161C will be a continuous line. The metal lines of FIGS. 1BA-1BB can be used in different configurations. - 4. Application-Specific Integrated Circuit (ASIC)
- In general, ASIC is small and fast. In prior arts, all masks used in an ASIC product are custom masks. The large number of custom masks makes medium- to small-volume ASIC expensive. Even in the shuttle programs provided by several foundries, a 5 mm×5 mm chip costs ˜$75,000. This price tag is difficult to accept for most design-houses.
- 5. Fabrication of Conventional Mask and Master Optical Disc
- In the prior art, the fabrication of a conventional mask is similar to lithographic process in IC. First, photoresist is coated on mask blank, and exposed by e-beam. Then the undesired Cr film is etched away. It is time-consuming and expensive. For PGA, ROM and others, the mask-making should take advantage of the fact that typical openings in these devices are regularly sized and spaced. The opening masks for these devices can be made in a shorter time and at a lower cost.
- Optical discs, such as CD, VCD, DVD, have a huge consumer market. An optical disc is fabricated by pressing a master optical disc on a disc blank. Currently, the fabrication of master optical disc is similar to the fabrication of mask in IC. It is time-consuming and expensive.
- It is a principle object of the present invention to provide a low-cost lithography.
- It is a further object of the present invention to lower the mask cost.
- It is a further object of the present invention to lower the cost of lithographic and related processes.
- It is a further object of the present invention to lower the cost of high-precision masks as well as improve the lithographic resolution.
- In accordance with these and other objects of the present invention, a low-cost lithography is disclosed.
- The low-cost lithography disclosed in the present invention is based on two approaches: 1. Use low-precision mask (e.g. nF-opening mask) to implement high-precision pattern (e.g. opening-related patterns); 2. Improve the mask re-usability (e.g. with programmable litho-system and/or logic litho-system). To take full advantage of these techniques, “design-for-litho-programming (DFL)” is preferred. Low-cost lithography can be used in litho-programmable integrated circuits (e.g. litho-programmable SCIC and litho-programmable ASIC), as well as the fabrication of conventional masks and master optical discs. On the other hand, pattern-distribution enables the mask-repair by redundancy. It further enables highly-corrected mask, which provides higher-order correctional structures for clear patterns on wafer.
- 1. nF-Opening-Related Patterns and Processes
- The present invention discloses means for implementing high-precision pattern through low-precision (thus low-cost) mask. This approach is particularly suitable to implement opening-related patterns (e.g. inter-level connection and segmented-line). For inter-level connection, the dimension of the opening perpendicular to the upper metal line is controlled by the width of the upper metal line; the dimension of the opening along the upper metal line can be larger than the width of the lower metal line. For segmented-line, the dimension of the opening (i.e. segment-gap) is preferably larger than the width of the metal line. Accordingly, the dimension of the opening used in these patterns can be larger than the width of the metal line it interacts with. Because the minimum metal width is 1F, the opening dimension could be nF, with n>1. In the other words, the nF-opening mask (n>1, feature size>1F) can be used to implement high-precision opening-related patterns (
feature size ˜ 1F). It offers the following benefits: 1. With a large feature size, the nF-opening mask costs less; 2. With a large toleration on the pattern shape, the nF-opening mask can be made with low-precision tools, even in-house with a conventional litho-tool; 3. The nF-opening mask can tolerate large alignment errors to the upper/lower-level metal patterns. The associated processing cost is lower. - In the present invention, the inter-level connection manufactured from the nF-opening mask is referred to as aiv. During its manufacturing process, damascene, particularly dual-damascene technique is preferably used. Dual damascene can take the form of embedded nf-opening, nF-opening-first-trench-second, trench-first-nF-opening-second. On the other hand, segmented-line can be implemented through litho-“OR” between an nF-opening mask and a continuous-line mask.
- 2. Programmable Litho-System
- A programmable litho-system can be used to improve the mask re-usability. Its core technology is a programmable mask. Being a “soft” mask, a programmable mask can adjust the pattern thereon based on a set of configuration data. Accordingly, the configuration data are coded into an image carrier (i.e. the object that receives the exposure light in a litho-tool, e.g. wafer, mask blank, or master disc. Unless being specifically mentioned, wafer is used as an example). Opening-programmable mask (OPM) is one type of programmable mask that is well suited to adjust the light intensity at openings.
- An OPM comprises at least an opening-defining plane (ODP) and a light-modulating plane (LMP). The ODP defines the final shape of openings on wafer; the LMP controls light intensity at said opening. Preferably, the ODP and the LMP are located on separate surfaces. This arrangement offers more design freedom, better manufacturability and longer exposure endurance. The LMP comprises a plurality of light-modulating cells (LMC). They include liquid-crystal-LMC (LC-LMC), MEMS-type-LMC (MEMS-LMC), and emissive-LMC. The LC-LMC and the MEMS-LMC can be either transmissive or reflective. The LC-LMC is similar to liquid-crystal display (LCD). The MEMS-LMC comprises at least one movable element, whose position controls the state of opening (“ON” or “OFF”). Typical movable elements are slider, rotor, roller-shade, digital micro-mirror, and digital light-valve. The emissive-LMC controls light emission at each cell. The LMC can be built in three-dimension (multi-level) to improve its density. On the other hand, the peripheral circuit of an LMC preferably comprises a transistor and may use technologies developed in SOI (e.g. backside grinding, smart-cut).
- 3. Logic Litho-System
- In a logic litho-system, wafer pattern is generated through a series of litho-logic operations between mask images. Typical litho-logic operations include litho-“OR” and litho-“AND”. Litho-“OR” can be implemented through multiple exposures on a wafer. Litho-“AND” can be implemented through multiple filterings to the exposure light.
- One important consequence of the logic litho-system is pattern-distribution. With pattern-distribution, wafer patterns are distributed on a plurality of mask, or in a plurality of mask regions on a single mask (a.k.a. pattern-distributed mask). After performing a litho-logic operation to the patterns from these masks (regions), the desired wafer pattern can be obtained. Pattern-distribution can be used to improve the mask re-usability. It can further enable the mask-repair through redundancy and highly-corrected masks.
- In some IC designs, one portion of the circuit is quite mature (mature circuit), with another often subject to change (volatile circuit). In prior arts, a small circuit change translates to a costly new order for the whole mask. On the other hand, with pattern-distribution, the wafer patterns can be distributed on two masks: one for mature circuit (mature mask) and the other for volatile circuit (volatile mask). The mature mask can be used in a number of products—an improvement of the mask re-usability. Moreover, the data amount on the volatile mask is typically small and therefore, its fabrication is much less time-consuming and less expensive.
- A. Mask-Repair Through Redundancy
- Pattern-distribution enables the mask-repair through redundancy. In prior arts, the defective primary mask (i.e. the mask supposed to carry the patterns to be formed on wafer) is repaired at the defect sites. To be more specific, the defect sites are first cleared on the primary mask then the correctional structures are formed in the cleared space. Because a typical mask is “feature-dense”, “repair-at-site” will likely damage the adjacent “known-good” mask features and therefore, is error-prone. The situation becomes even worse for the OPC-mask and the PSM.
- On the other hand, during mask-repair through redundancy, after clearing or darkening the defect sites (depending on the logic litho-operation to be used), instead of “repair-at-site”, the correctional structures are formed in a redundant mask (region). These redundant patterns can form the desired wafer pattern through a litho-logic operation with the primary patterns. Because the correctional structures are formed in a separate area on the mask or on a different mask, this formation process will unlikely interfere with other “known-good” mask patterns. As a result, “repair-through-redundancy” is more reliable and robust. It is particularly suitable to repair the OPC-mask and PSM. Mask-repair through redundancy can improve the mask yield.
- B. Highly-Corrected Masks
- Another important application of pattern-distribution is in the area of highly-corrected masks. In prior arts, because the features are closely spaced, there is not much space to accommodate higher-order correctional structures. This is no longer true to a pattern-distributed mask. After pattern-distribution, the feature spacing on the pattern-distributed mask can be much larger than that on a conventional mask. This results in less proximity effect and less OPC-computing. Secondly and more importantly, the larger spacing between mask features can be used to accommodate highly-order correctional structures. As a result, even if the same litho-tool is used, the highly-corrected masks can achieve much better lithographic resolution. Moreover, the highly-corrected mask can still be a binary mask. This can greatly simplify the mask fabrication.
- 4. Design-for-Litho-Programming (DFL)
- Ideally, a few general-purpose masks (GPM) can be used in most lithographic processes. The GPM examples include uniform opening programming mask (UOPM) and uniform metal-line mask (UMLM). On an UOPM, all programmable openings have the same size and same spacing, preferably 1F or 2F; on an UMLM, all metal lines have the same width and same spacing, preferably 1F. To maximize their usage, IC layout preferably follows “design-for-litho-programming (DFL)”. One set of DFL rules require that: a. any inter-level connection on a wafer should correspond to the location of a programmable opening on the UOPM; b. at least the metal lines inside the programming area has the same width and same pitch, preferably with a smaller or equal corresponding width than and equal or half corresponding pitch to the programmable openings on the UOPM.
- 5. Composite Litho-System
- Composite litho-system combines programmable litho-system with logic litho-system. Besides programmable SoC and programmable lines, a composite litho-system enables the deep-sub-μm litho-programming based on manufacturable OPM. It can also improve the mask yield and offer longer exposure endurance to an OPM.
- The size of typical manufacturable LMC (preferably based on the mature LCD technology) is ˜5 μm. With R (image-reduction ratio of a reduction stepper) 4×-5× and assuming no ODP, the wafer opening could be as large as 1 μm. This is too large for any deep-sub-μm litho-programming. Fortunately, because the ODP opening is the opening that defines the final shape of the wafer opening, a small ODP opening size can make the final wafer opening small enough. However, the LMC size still dictates the wafer-opening period Pw. With a large Pw (˜1 μm), not all wafer openings can be litho-programmed at once. A practical solution is to use a composite litho-system, where a multi-pass exposure with displacement is adopted (i.e. inter-leaved exposure). In the multi-pass with displacement, a first number of openings are first exposed, then a displacement ΔS is made to the wafer or to the mask before a second number of openings are exposed. By setting ΔS to the Pw for that deep-sub-μm node, the Pw requirement can be met. Alternatively, the litho-tools with large R (e.g. 20) can be used. Another practical solution is by twice-imaging (referring to section “Quasi-opening-programmable mask”).
- During its usage, an OPM preferably goes through a field inspection to ensure a desired pattern is generated. An image sensor can be used for this purpose. On the other hand, to improve the mask yield, a redundant mask (region) can be used. The OPM is well suited for this purpose.
- With separate LMP and ODP, the OPM can endure long-term exposure. Between exposures, the location of the ODP is fixed, while the LMP is displaced. As a result, all regions on LMP are evenly heated and this prolongs the OPM lifetime.
- 6. Applications of Low-Cost Lithography
- Low-cost lithography combines techniques such as nF-opening mask, programmable litho-system, and logic litho-system. It is ideal for the fabrication of litho-programmable integrated circuits (LP-IC). The LP-IC comprises a plurality of litho-programmable opening-related patterns (e.g. inter-level connections and segmented-lines). It can be implemented with an UOPM and optionally with an UMLM. In an LP-IC flow, a customer first creates a set of customer data; then s/he sends to the fab an order, which has an order volume; the fab returns with a price quote. The overall expected revenue for this order, which is the product of the order volume and the price quote, can be smaller than the cost of the conventional custom opening-mask set corresponding to said opening-related patterns (custom patterns). In contrast, in prior arts, the completion of the same order involves making a new set of (conventional) custom masks. The manufacturing cost, including other processing and materials costs, should at least be higher than the cost for these masks. Namely, the overall expected revenue of the conventional (non-litho-programmable) IC cannot be lower than the mask cost.
- One example of LP-IC is litho-programmable SCIC (LP-SCIC). In an LP-SCIC, a limited number of custom layers are formed by litho-programming. The LP-SCIC includes litho-programmable ROM (LP-ROM) and litho-programmable PGA (LP-PGA). Another example of LP-IC—litho-programmable ASIC (LP-ASIC)—goes even further. In the LP-ASIC, no custom masks (at least no expensive custom masks) are used for the back-end interconnects. The LP-ASIC design needs to follow a more stringent ASIC-DFL: in at least one metal layer, metal lines are aligned along a first direction with their width and spacing preferably 1F; in a metal layer next to said metal layer, metal lines are aligned along a second direction with their width and spacing also preferably 1F. By repetitively using GPM's such as UOPM and UMLM, all interconnect patterns are formed. Shared in many LP-ASIC products, the GPM's add little cost to ASIC chip.
- Low-cost lithography, more particularly OPM, can be used to fabricate conventional masks. Accordingly, this type of conventional mask is referred to as quasi-opening programmable mask (QOPM). It is quasi-programmable because the configuration data can be easily coded into the QOPM in-house. After being coded by an OPM pattern, the QOPM is used to generate patterns on wafer. By “imaging twice” (first from an OPM to a QOPM, then from the QOPM to a wafer), the image-reduction ratio from the OPM to the wafer is R2 (R=4×−5×, R2=16×−25×). As a result, manufacturable OPM (preferably based on mature LCD with dimension ˜5 μm) can be used to create deep-sub-μm features.\
- Low-cost lithography can also be used to fabricate master optical disc. This process is similar to that of the QOPM. Note that pits on the master optical disc are on a spiral. Between exposures, the disc needs to be rotated and displaced.
- 7. Business Model
- The LP-IC preferably follows an internet business model, i.e. a customer send a set of customer data to the fab through internet. Here, the customer data may comprise a file pointer. Said file pointer points to a file in a database, which the fab has fast access to. Once a new order is received, a new set of configuration data is issued to the OPM and then coded into the wafers-under-exposure. Accordingly, the customer have direct, remote, real-time control over the wafers-being-processed.
- Using a conventional “hard” mask for coding, the prior-art ROM usually only stores “public” information (e.g. operating system). With the advent of litho-programming, litho-programmable ROM (LP-ROM) can be used to store “personal” information. To provide better information security, the LP-ROM data sent to the fab are preferably encrypted. Moreover, a decryption engine and a key storage are preferably formed on the same chip as the LP-ROM. After it is shipped back from the fab, user inputs the key to enable the chip. Thus, the key is not exposed to any third party, during the chip manufacturing or during the chip usage. This guarantees maximum data security.
- FIGS. 1A-1CB illustrate several opening-related patterns used in prior arts.
-
FIG. 2A illustrates a preferred nF-opening and its interaction with various metal lines;FIG. 2B illustrates the core and peripheral portions of said opening on an nF-opening mask. - FIGS. 3AA-3BB illustrate several preferred aivs.
- FIGS. 4AA-4CC illustrate several preferred dielectric structures used in aiv.
-
FIGS. 5A-5D (includingFIG. 5A ′) describe several preferred aiv processes based on the conventional metallization. - FIGS. 6A-6C′ describe several preferred aiv processes based on single damascene.
- FIGS. 7AA-7CE′ describe several preferred aiv processes based on dual damascene.
- FIGS. 8AA-8BC illustrate several preferred programmable litho-systems.
- FIGS. 9AA-9BE illustrate the structures and relative placements of the LMP and the ODP in several preferred opening-programmable masks.
- FIGS. 10AA-10CC illustrate the structures and peripheral circuits of a preferred liquid-crystal LMC (LC-LMC).
- FIGS. 11A-11MD illustrate the structures and peripheral circuits for several preferred sliders.
- FIGS. 12A-12EC illustrate the structures and peripheral circuits for several preferred rotors.
- FIGS. 13AA-13CB illustrate the structures and peripheral circuits for several preferred hinges.
- FIGS. 14A-14EB illustrate the structures and peripheral circuits of a preferred roller-shade LMC (RS-LMC).
-
FIGS. 15A-15C illustrate the structures of several preferred reflective LMC's (R-LMC). -
FIG. 16B illustrate the structure and circuit symbol of a preferred emissive LMC (E-LMC). - FIGS. 17AA-17BC illustrate the structures of several three-dimensional LMC (3D-LMC).
-
FIG. 18D describe a preferred process flow for a peripheral circuit in an LMC. -
FIG. 19C explains the concept of “OR” litho-system. - FIGS. 20AA-20EG illustrate several preferred “OR” litho-systems.
FIGS. 21A-21C explains the concept of “AND” litho-system. -
FIGS. 22A-22B illustrate two preferred “AND” litho-systems. - FIGS. 23AA-23DC illustrate several preferred correctional structures for vias on a highly-corrected mask.
- FIGS. 24AA-24BC illustrate several preferred correctional structures for line-spaces on a highly-corrected mask.
-
FIGS. 25A-25C illustrate a preferred implementation of vias on an SoC chip through litho-“OR”. - FIGS. 26A-26FC describe several preferred implementations of segmented-lines through litho-“OR”.
- FIGS. 27AA-27DB illustrate several preferred thin-film masks.
-
FIGS. 28A-28B illustrate two preferred general-purpose masks (GPM). - FIGS. 29A-29BC describe several preferred “design-for-litho-programming (DFL)”.
- FIGS. 30A-30CB illustrate several preferred programmable SoC opening patterns and preferred programmable line patterns.
- FIGS. 31AA-31DC′ illustrate several preferred implementations of the litho-programmable deep-sub-μm openings through litho-“OR”.
- FIGS. 32AA-32B illustrate several preferred implementations of the litho-programmable deep-sub-μm openings through litho-“AND”.
- FIGS. 33AA-33FC illustrate several preferred mask-inspection and mask-repair means.
- FIGS. 34AA-34BB illustrate a preferred OPM with long-term exposure endurance.
-
FIG. 35 illustrates a preferred flow for a litho-programmable integrated circuit (LP-IC). - FIGS. 36AA-36F illustrate several preferred implementations of litho-programmable ASIC.
-
FIGS. 37A-37C illustrate a preferred implementation of a quasi-opening-programmable mask. - FIGS. 38A-38CB illustrate a preferred implementation of master optical disc.
- FIGS. 39A-39BC illustrate several preferred business models for an LP-IC and a preferred litho-programmable ROM (LP-ROM).
- For the reason of simplicity, in this disclosure, the figure number with a missing appendix refers to all figures with that appendix. For example,
FIG. 11 refers to FIGS. 11A-17MD; andFIG. 11M refers toFIG. 11M A-11MD. - 1. nF-Opening-Related Patterns and Processes
- According to the present invention, low-precision masks (nF-opening masks) can be used to implement high-precision opening-related patterns (e.g. inter-level connections and segmented-lines).
- A. nF-Opening-Related Patterns
- Opening-related pattern refers to the pattern at which an opening is formed in the photoresist during its manufacturing process.
FIG. 2A illustrates an opening 50 o. It can interact with metal line 162 (and 174) adjacent to it. If themetal lines metal line 162 to formmetal segments 162 l, 162 r. Accordingly, inter-level connection and segmented-lines are referred to as opening-related patterns. For inter-level connection, Wo, Lo of the opening 50 o can be larger than Dm, Dl of themetal lines 162, 174 (˜1F); for segmented-lines, Wo of the opening 50 o can larger than Dm of the metal line 162 (˜1F). Namely, the dimension Wo (and Lo) of the opening pattern 50 o can be larger than the width Dm (and Dl) of the metal-line patterns it interacts with. Accordingly, the opening 50 o is referred to as nF-opening (with n>1, preferably 2). At the 0.13 μm node, the nF-opening mask can use masks from the 0.25 μm node. Apparently, they are much less expensive. -
FIG. 2B illustrates thecore portion 50 oc and theperipheral portion 50 op of the nF-opening 50 o on an nF-openingmask 50 om. During its lithographic process, only thecore portion 50 oc needs to be fully exposed. For theperipheral portion 50 op, there is little requirement on exposure dosage and image fidelity (as will become apparent as FIGS. 3AA-3BB and FIGS. 26A-26FC are explained). Without stringent requirements on the shape of the openings, the nF-opening masks can be made in-house, even in a conventional litho-tool. That further lowers the mask cost and shortens the turn-around time. Moreover, it is acceptable to have a large alignment tolerance between the nF-opening mask and the metal-line masks. This can lower the processing cost. - B. Aiv Structures
- To differentiate from a conventional 1F-via, the physical opening formed in the inter-level connection based on an nF-opening mask is referred to as aiv.
FIG. 3A A illustrates the relative placement of the nF-opening pattern vs. the upper-level metal pattern, andFIG. 3A B illustrates the relative placement of the nF-opening pattern vs. the lower-level metal pattern for twoaivs FIG. 3 and figures thereafter choose this aiv configuration to illustrate the invention. Here, the length direction of an aiv is perpendicular to the upper-level metal line; the width direction is along the upper-level metal line. The nF-openings level metal line 311 and the lower-level metal line 331, between the upper-level metal line 312 and the lower-level metal line 332, respectively. The aiv pattern on wafer is the intersection of nF-opening pattern and upper-level metal pattern.FIG. 3A C illustrates the cross-sectional view of aivs 321 a, 322 a along A1-A2. Along the width direction of the aiv 322 a, theaiv width 2 wa is equal to thewidth 2 wm of the upper-level metal line 312. Accordingly, at this direction, the precision of the aiv pattern is controlled by the upper-level metal mask. On the other hand, along the length direction of the aiv 321 a, theaiv length 1 la is equal to thelength 1 lo of the nF-opening 321 and it can be larger than thewidth 1 wl of the lower-level metal line 331. As long as the right edge lar of the aiv 321 a (corresponding to the right edge 1 r of nF-opening 321 inFIG. 3A A) does not touch the adjacent lower-level metal line 332, circuit performance will not be affected much. Accordingly, the layout of nF-openings is very flexible. - For the nF-openings with n>2,
adjacent openings 50 oa, 50 ob can be combined into a merged opening 50 o 2 (FIG. 3B A). It provides inter-level connection for the upper-level metal line 162 and two lower-level metal lines FIG. 3B B). As a reference, astandalone aiv 50 od (i.e. not merged with other aivs) is also illustrated inFIG. 3B B. The merged opening 50o 2 can help further lower the mask cost. - In FIGS. 2A-3BB, the inter-level connection is a bipolar connection (i.e. its resistance along both directions is low). It should be noted that, other forms of inter-level connections can also use the nF-opening mask. Examples include programmable inter-level connection (e.g. antifuse) and unipolar inter-level connection (i.e. its resistance is higher in one direction than in the other, e.g. 3D-ROM cell). In a programmable inter-level connection, aiv comprises an antifuse layer; in a unipolar inter-level connection, aiv comprises a ROM layer (a.k.a. quasi-conduction layer). Similarly, the aiv length in these devices can also be larger than the width of the lower-level metal line, and the aiv width can be equal to the width of the upper-level metal line. Their manufacturing process can be similar to the (bipolar) inter-level connection of FIGS. 2A-3BB.
- In aivs and the metal lines they connect (
FIG. 3A C andFIG. 3B B), the dielectric between the lower-level metal lines (e.g. 331, 332) is referred to as lower-level dielectric 400 l; the dielectric between the aivs (e.g. 321 a, 322 a) is referred to as inter-level dielectric 400 a; and the dielectric between the upper-level metal lines (e.g. 311, 312) is referred to as upper-level dielectric 400 m. FIGS. 4AA-4CC illustrate several preferred dielectric structures. - FIGS. 4AA-4AB illustrate several preferred lower-level dielectrics 400 l. In
FIG. 4A A, it comprises a single, uniform dielectric 400d 0. InFIG. 4A B, it comprises at least two dielectric films 400d 8, 400d 9. The dielectric film 400d 9 typically comprises low-κ dielectric (e.g. silicon dioxide, SiLK). The dielectric film 400d 8 can be used as an etchstop layer for the inter-level dielectric 400 a. It may comprise silicon nitride, high-ρ poly- or amorphous silicon. - FIGS. 4BA-4BC illustrate several preferred
inter-level dielectrics 400 a. InFIG. 4B A, it uses a single, uniform dielectric 400d 1. InFIG. 4B B, it comprises two dielectric films 400d 2, 400d 3. The dielectric film 400d 2 can be used as etchstop layer for the dielectric film 400d 3. It comprises silicon nitride, high-ρ poly- or amorphous silicon. The dielectric film 400d 3 comprises low-κ dielectric. InFIG. 4B C, the inter-level dielectric 400 a comprises three dielectric films 400d 4, 400d 5, 400 d 6. Each dielectric film can be an etchstop layer for the film located thereon. Examples are: the dielectric film 400d 5 comprises low-κ dielectric; the dielectric films 400d 4, 400 d 6 comprise silicon nitride, high-ρ poly- or amorphous silicon. - FIGS. 4CA-4CC illustrate several preferred upper-
level dielectrics 400 m. InFIG. 4C A, it uses a single, uniform dielectric 400 d 10. InFIG. 4C B, the upper-level dielectric 400 m comprises two dielectric films 400d 11, 400 d 12. The dielectric film 400 d 12 can be used as a hard-mask for the dielectric film 400d 11. Examples are: the dielectric film 400d 11 comprises low-κ dielectric; the dielectric film 400 d 12 comprises silicon nitride, high-ρ poly- or amorphous silicon. InFIG. 4C C, the upper-level dielectric 400 m comprises three dielectric films 400 d 13, 400d 14, 400d 15. Each dielectric film can be an etchstop layer for the film located thereon. Example are: the dielectric film 400d 14 comprises low-κ dielectric; the dielectric films 400 d 13, 400d 15 comprise silicon nitride, high-ρ poly- or amorphous silicon. Alternatively, the dielectric film 400 d 13 may comprise silicon nitride, etc; the dielectric film 400d 15 may comprise high-ρ poly- or amorphous silicon. - C. Aiv Processes
- FIGS. 5A-7CE′ illustrate several preferred aiv processes. They can be categorized according to the metallization process. They include conventional metallization, single damascene, and dual damascene.
- a. Conventional Metallization
-
FIGS. 5A-5D (includingFIG. 5A ′) describe several preferred aiv process flows based on conventional metallization. After the formation of the lower-level metal lines opening pattern 340 a is transferred (FIG. 5A ). After removing the inter-level dielectric 400 a, aconductive film 310 m is formed (FIG. 5B ). With another lithographic step, aconductive film 310 m forms upper-level metal lines 311, 312 (FIG. 5C ). Then an upper-level dielectric 400 m is filled in and planarized (FIG. 5D ).FIG. 5A ′ is a variation ofFIG. 5A . After the nF-opening pattern transfer, a tapered sidewall is formed in the inter-level dielectric 400 a′. It facilitates the etch of the upper-level metal lines. The taper sidewall can also be used in other aiv structures. - b. Single Damascene
- FIGS. 6A-6C′ describe several preferred aiv process flows based on single damascene. After forming an nF-opening in the inter-level dielectric 400 a, a single damascene step is performed, i.e. a
metal plug 400 p is formed in the nF-openings (FIG. 6A ). This is followed by the formation of a conductive film and a lithographic step. The conductive film is then etched to form upper-level metal lines metal plug 400 p (FIG. 6B ) or stop thereon (FIG. 6B ′). The last step is the fill-in of an upper-level dielectric and planarization (FIG. 6C ,FIG. 6C ′). - c. Dual Damascene
- Aiv process preferably takes full advantage of dual damascene. Dual damascene can take the form of embedded nF-opening (FIGS. 7AA-7AF, including
FIG. 7A A′ andFIG. 7A E′), nF-opening-first-trench-second (FIGS. 7BA-7BH), and trench-first-nF-opening-second (FIGS. 7CA-7CF, includingFIG. 7C E′). - FIGS. 7AA-7AF illustrate a preferred aiv process based on dual damascene with embedded nF-opening. The name “embedded nF-opening” is derived from the fact that the nF-opening pattern is embedded between the inter-level dielectric 400 a and the upper-
level dielectric 400 m. Its process flow is as follows. First, an inter-level dielectric 400 a is formed on the lower-level metal lines 331, 332 (FIG. 7A A). It may use the preferred dielectric ofFIG. 4B C, i.e. it comprises three dielectric films 400d 4, 400d 5, 400 d 6. The nF-opening pattern is transferred to the dielectric film 400 d 6 (FIG. 7A B). Then an upper-level dielectric 400 m is formed. It may use the preferred dielectric ofFIG. 4C A. This is followed by the pattern transfer of atrench mask 340 b (FIG. 7A C). Then a series of etches are performed: a first etch removes the upper-level dielectric 400 m and the dielectric film 400d 5 until the dielectric film 400d 4 is reached (FIG. 7A D); a second etch removes the remaining dielectric 400d 4 until the lower-level metal lines trenches FIG. 7A E). At last, a conductive material is filled in and planarized (FIG. 7A F). - Compared with the conventional borderless dual damascene, the aiv length 11 a is larger than the
width 1 wl of the lower-level metal line 331. To avoid over-etching the lower-level dielectric 400 l during said series of etches, an etchstop layer 400d 4 preferably covers the top surface of the lower-level dielectric 400 l (the preferred dielectric ofFIG. 4B C), or there is an etchstop layer 400d 8 along both sides of the top surface of the lower-level metal line 331 (the preferred dielectric ofFIG. 4A B). -
FIG. 7A A′,FIG. 7A E′ illustrate an alternate preferred aiv process with embedded nF-opening. In this preferred embodiment, the inter-level dielectric 400 a and upper-level dielectric 400 m are both single, uniform dielectrics. Preferably they comprise different dielectrics (for example, 400 a comprises nitride, 400 m comprises oxide). Other processing steps are similar to those in FIGS. 7AA-7AF. - In
FIG. 7A , the nF-opening pattern-transfer occurs between the formation of the inter-level dielectric and the upper-level dielectric. InFIG. 7B andFIG. 7C , all pattern transfers occur after these dielectrics are formed. The difference betweenFIG. 7B andFIG. 7C is the order in which the masks are applied. - FIGS. 7BA-7BH illustrate a preferred aiv process based on dual damascene with the nF-opening-first-trench-second. First, an inter-level dielectric 400 a and an upper-
level dielectric 400 m are formed on the lower-level metal lines 331, 332 (FIG. 7B A). Here, the inter-level dielectric 400 a uses the dielectric ofFIG. 4B B, and the upper-level dielectric 400 m uses the dielectric in the first example ofFIG. 4C C. Next, the nF-openingpatterns FIG. 7B B). The etched dielectric film 400d 15 can be used as a hard-mask for subsequent processing. Then a pattern-transfer is performed to atrench mask 340 b (FIG. 7B C). This is followed by a series of etches: a first etch removes the exposed dielectric film 400d 14 until 400 d 13 is reached (FIG. 7B D); a second etch removes the exposed dielectric films 400d 15, 400 d 13 until 400d 3, 400d 14 are reached (FIG. 7B E); a third etch removes the exposed dielectric films 400d 3, 400d 14 until 400d 2, 400 d 13 are reached (FIG. 7B F); photoresist is then removed and a fourth etch removes the exposed dielectric films 400d 2, 400 d 13, 400d 15 until 400d 3, 400d 14 are reached (FIG. 7B G). At last, a conductive material is filled in and planarized (FIG. 7B H). - FIGS. 7CA-7CF illustrate a preferred aiv process based on dual damascene with trench-first-nF-opening-second. Similar to
FIG. 7B A, an inter-level dielectric 400 a and an upper-level dielectric 400 m are formed on top of the lower-level metal lines FIG. 7B A, thetrench patterns d 15 first (FIG. 7C A). Then, the nF-opening pattern 340 a is transferred to photoresist (FIG. 7C B). In addition to photoresist, the dielectric film 400d 15 can be used as a hard-mask. This is followed by a series of etches: a first etch removes the exposed dielectric film 400d 14 until 400d 15 is reached (FIG. 7C C); a second etch removes the exposed dielectric film 400 d 13 until 400d 3, 400d 15 are reached (FIG. 7C C); then photoresist 340 a is removed and a third etch removes the exposed dielectric films 400d 3, 400d 14 until 400d 2, 400 d 13, 400d 15 are reached (FIG. 7C D); a fourth etch removes the exposed dielectric films 400d 2, 400 d 13, 400d 15 until 400d 3, 400d 14 are reached (FIG. 7C E). At last, a conductive material is filled in and planarized (FIG. 7C F). - After finishing said fourth etch of
FIG. 7C E, adielectric spacer 400 sp can be formed on the sidewall of the aiv and the trench (FIG. 7C E′). Saiddielectric spacer 400 sp ensures electrical isolation between the aiv and the adjacent lower-level metal line. Apparently, a dielectric spacer can also be used in the damascene structures ofFIGS. 5C, 6B , 6B′, 7AE, 7AE′, 7BG. InFIGS. 5C, 6B , 6B′, the dielectric spacer is formed along both sides of the nF-opening; in FIGS. 7AE, 7AE′, 7BG, it is formed along both sides of the aiv. - In
FIG. 7 , there are a plurality of etch-stop layers. In fact, timed etch could also be used. For the timed etch, some etchstop layers may not be needed in the aiv structure. - 2. Programmable Litho-System
- A programmable litho-system can be used to improve the mask re-usability. Its core technology is a programmable mask. Being a “soft” mask, a programmable mask can adjust the pattern thereon based on a set of configuration data. The configuration data are coded into an image carrier (i.e. the object that receives the exposure light in a litho-tool, e.g. wafer, mask blank, or master disc. Unless being specifically mentioned, wafer is used as an example). Opening-programmable mask (OPM) is one type of programmable mask that is well suited to adjust the brightness of openings.
-
FIG. 8A A illustrates the flow ofcustomer data 17 from a customer 12 to a fab 14 (e.g. a foundry). Thecustomer data 17 can be encrypted or in plain-text. They are delivered to the fab 14 through a medium 18. The medium 18 includes internet, hard-disk drive (HDD), optical disc and other means. After necessary data processing in the fab 14, thecustomer data 17 are converted into a set ofconfiguration data 16. Theconfiguration data 16 are then hard-coded into the image carrier by the programmable litho-system 20. -
FIG. 8A B illustrates the hierarchy of a programmable litho-system 20. Its core portion is anOPM 30. An OPM comprises at least an opening-defining plane (ODP) 32 and a light-modulating plane (LMP) 38. TheODP 32 defines the final shape of openings on a wafer, while theLMP 38 controls the light intensity at said opening. TheODP 32 comprises a plurality ofODP openings 70 and theLMP 38 comprises a plurality of light-modulating cells (LMC) 40. EachLMC 40 comprises a light-modulating area (LMA) 50 and aperipheral circuit 60. - FIGS. 8BA-8BC illustrate three preferred programmable litho-system: transmissive, reflective and emissive. In
FIG. 8B A, a transmissive programmable litho-system 20 comprises alight source 26, atransmissive OPM 30 t and aprojector 24. After the light passes through theOPM 30 t, its intensity varies according to the patterns on saidOPM 30 t, which is controlled by theconfiguration data 16.FIG. 8B B illustrates a preferred reflective programmable litho-system 20. It is well suited for the litho-system using ultra-violet light (UVL). The light is modulated by areflective OPM 30 r before being projected onto thewafer 22. The reflecting/non-reflecting pattern of thereflective OPM 30 r is controlled by theconfiguration data 16. InFIG. 8B C, an emissive programmable litho-system comprises anemissive OPM 30 e. Theemissive OPM 30 e comprises of a plurality of light-emitting cells. By selectively turning on or off these cells, theconfiguration data 16 can be passed to thewafer 22. Theemissive OPM 30 e is similar to the multiple parallel electron guns used in an e-beam litho-system. Besides optical light, X-ray, e-beam or ion beam can also be used in the programmable litho-systems. - A. Opening-Programmable Mask (OPM)
- The OPM preferably has a programmable opening corresponding to every cross-point between vertical and horizontal metal lines in the ROM or PGA.
FIG. 9A A is a plan view of aLMP 38. It controls the exposure intensity atopenings 70 aa-70 bb (FIG. 9A B). In this preferred embodiment, theLMP 38 comprises a configuration-data bus 16 and a 2×2 light-modulating matrix. The light-modulating matrix comprises an array of LMC's 40 aa-40 bb, a row-decoder 16 a and acolumn decoder 16 b. The LMC is the basic building block ofLMP 38. EachLMC 400 aa-40 bb comprises anLMA 50 aa-50 bb and aperipheral circuit 60 aa-60 bb. The LMA has a dimension of Dc, a spacing of Sc and a period of Pc. Its state is controlled byaddress line 42 a-42 b anddata line 44 a-44 b. At its “ON” state, the LMA can transmit light (for thetransmissive OPM 30 t) or reflect light to a pre-determined direction (for thereflective OPM 30 r); at its “OFF” state, it cannot. InFIG. 9A A and figures thereafter, if the crosshatch in an LMA is sparse (as inLMA 50 ba), the state of this LMA is un-defined; if the crosshatch is dense (as inLMA 50 aa), this LMA is at the “OFF” state; if there is no crosshatch (as inLMA 50 ab), this LMA is at the “ON” state.FIG. 9A B is a plan view of theODP 32. It defines the final shape of the opening on wafer. Every opening is aligned with and preferably encompassed by an LMA (e.g. 70 aa is aligned to 50 aa, referring to FIGS. 9BA-9BE). The making of theODP 32 is a standard mask-making process. It may use the advanced mask-making techniques, such as optical proximity correction (OPC) and phase-shift mask (PSM). - Referring now to FIGS. 9BA-9BE, the relative placements of several preferred ODP's and LMP's in an OPM are illustrated. In these figures, because it can better demonstrate the state of the LMC, a movable element—
slider 51 a—is used as example. In most cases, when theslider 51 a covers theLMA 50 aa, theLMC 40 aa is at the “OFF” state; otherwise, it is at the “ON” state. InFIG. 9B A, theLMP 32 and theODP 38 are merged and there is no physical distinction between them. In FIGS. 9BB-9BC, theODP 32 and theLMP 38 are located on separate surfaces. This arrangement offers more design freedom, better manufacturability and longer exposure endurance (referring to FIGS. 34AA-34BB). InFIG. 9B B, theODP 32 and theLMP 38 are located at two sides of themask substrate 36. In FIGS. 9BC-9BE, theODP 32 and theLMP 38 are located on twodifferent substrates FIG. 9B D can be used in a reflective-OPM or an emissive-OPM. For the reflective-OPM, theODP 32 performs light reflection at eachopening 32 r; theLMP 38 can be built on a light-absorptivemembrane 36 m. For the emissive-OPM, theemissive plane 32 emits light at everyopening 32 r; theLMP 38 controls the intensity of light passing through. The preferred embodiment ofFIG. 9B E can be used in a reflective-OPM. Compared withFIG. 9B D, the placements of theODP 32 and theLMP 38 are exchanged. Themovable element 51 a comprises a reflective film. Apparently, the LMC inFIG. 9B E may use various preferred embodiments ofFIGS. 15A-15C . - B. Light-Modulating Cell (LMC)
- LMC is the basic building block of an OPM. It adjusts its light intensity according to the configuration data. It can borrow many design ideas and process ideas from the display industry. FIGS. 10AA-16B illustrate the structures and peripheral circuits of various preferred LMC's.
- a. Liquid-Crystal LMC (LC-LMC)
- Liquid-crystal display (LCD) technology is very mature. It can be readily applied to the liquid-crystal LMC (LC-LMC). FIGS. 10AA-10AB illustrate a preferred LC-
LMC 40. The LC-LMC 40 comprises aswitch 60 s and a liquid-crystal LMA (LC-LMA) 50. It is aligned with anODP opening 70 and preferably encompasses it. InFIG. 10A A and figures thereafter, the dashedODP openings 70 shown in theLMC 40 is actually the projected image of theODP opening 70 on theLMC 40, in the case theOPD opening 70 and theLMC 40 are not located on the same plane. The LC-LMC 40 comprises two opposingsubstrates electrodes alignment layers liquid crystal layer 36 c. For the transmissive cell, there are two opposing polarizers on both sides of the liquid crystal. To those of ordinary skills in the art, light transmission through liquid crystal can be modulated by a voltage between theelectrodes LMA 50 can occupy most area of the LMC 40 (FIG. 10A A). - The circuit symbol representing the LC-LMC is a capacitor 50 c 0 (
FIG. 10B ). Its peripheral circuits are illustrated in FIGS. 10CA-10CC. The peripheral circuit ofFIG. 10C A is a dynamic circuit. It uses a DRAM-type circuit 60 dp. When the voltage on theaddress line 42 rises to high, theswitch 60 s is turned on. The correspondingconfiguration bit 44 is sent to the capacitor 50 c 0 and determines the state of the LMC. FIGS. 10CB-10CC are static circuits. For static circuits, leakage current in the capacitor will not affect the LMC state. This is particularly useful for long-term exposure (no refresh is needed). The preferred circuit inFIG. 10C B is an SRAM-type circuit 60sp 1. It comprises twoswitches i 1 b. Its operation is similar to that ofFIG. 10C A. The preferred circuit inFIG. 10C C uses a non-volatile-memory (NVM)-type circuit 60sp 2. It comprises aNVM cell 60 nvm and aswitch 60 sp. Its operation includes two steps: a programming step and an exposure step. During the programming step (i.e. before exposure), the configuration bit is stored in theNVM cell 60 nvm. Theswitch 60 sp is turned on, and voltages are applied to theaddress line 42 and the configuration-bit line 44. The threshold voltage of thecell 60 nvm is varied according to the configuration bit. During exposure, the capacitor 50c 0 is first discharged. At this time, alladdress lines 42 and the configuration-bit line 44 are grounded with theswitch 60 sp on. Then theswitch 60 sp is turned off, and the voltages on alladdress lines 42 and the configuration-bit line 44 rise to appropriate values. If its threshold voltage is high, theNVM cell 60 nvm is still off and the capacitor 50c 0 is not charged; if its threshold voltage is low, theNVM cell 60 nvm is on and the capacitor 50c 0 becomes charged. As a result, the light passing through the LMC is modulated. - b. MEMS-LMC
- MEMS-LMC can directly modulate the exposure intensity at each opening. At its “ON” state, because the exposure light does not have to pass any additional medium, its intensity loss is minimized. The MEMS-based programmable litho-system can achieve comparable throughput to a conventional litho-tool. In addition, because the MEMS structure physically blocks the light path, the MEMS-based OPM is insensitive to the wavelength of the exposure light. It can be used in DUV, EUV, X-ray, e-beam, ion-beam and other litho-systems. Examples of MEMS-LMC include: slider, rotor, hinge, roller-shade, digital micro-mirror, and digital light-valve.
- Slider
- Slider is a simple MEMS structure with good manufacturability. FIGS. 11AA-11MD illustrate various preferred translational light-modulating cells (T-LMC). Its core element is a
slider 51 a. InFIG. 11A A, theslider 51 a is at the “OFF” state, i.e. it covers theopening 70; whereas inFIG. 11A B, theslider 51 a is at the “ON” state, i.e. it moves away from theopening 70. Being translational, the relative position of the four corners WXYZ ofslider 51 a does not change during the movement. - FIGS. 11CA-11GC illustrate a first preferred T-LMC type. This preferred T-LMC type comprises a floating slider and its driving forces are capacitive. A first preferred embodiment of the first T-LMC type is illustrated in FIGS. 11CA-11CC. Besides the
slider 51 a, it further comprises two flange pairs 51 p 1 a/51 m 1 a and 51p 1 b/51m 1 b. These two flange pairs cover the outer edge of theslider 51 a. At the “OFF” state, theslider 51 a aligns with the first flange pair 51 p 1 a/51 m 1 a. At the “ON” state, theslider 51 a aligns with the second flange pair 51p 1 b/51m 1 b. The cross-sectional view along BB′, CC′ are illustrated in FIGS. 11CB-11CC, respectively. Being constrained by the flange pair 51 p 1 a/51 m 1 a on both sides, theslider 51 a can only move along the y direction on the surface of thesubstrate 36. The inner surfaces of the flanges 51 p 1 a, 51 m 1 a are lined with a dielectric 51 b, which prevents electrical shorting between theslider 51 a and the neighboring flanges 51 p 1 a, 51 m 1 a. - FIGS. 11DA-11DC illustrate a preferred manufacturing sequence for the first preferred embodiment of the first T-LMC type. A first sacrificial layer 51
s 1 and theslider layer 51 a are formed onsubstrate 36. They are etched to form a first slider stack 51 t 1 (FIG. 11D A). Theslider layer 51 may comprise poly-silicon or metals such as aluminum. In the case of poly-silicon, the sacrificial layer 51s 1 may comprise silicon oxide; in the case of metals, the sacrificial layer 51s 1 may comprise polymeric materials (e.g. photo-resist). Then a second sacrificial layer 51s 2 is formed on top of the first slider stack 51 i 1 (FIG. 11D B). Preferably, the second sacrificial layer 51s 2 is planarized. It may comprise the same material as the first sacrificial layer 51s 1. Afterwards, the second sacrificial layer 51s 2 is etched to form a second slider stack 51t 2. This is followed by deposition of dielectric 51 b and the flange layer. They are etched to form flange pair 51 p 1 a/51 m 1 a (FIG. 11D C). Finally, theslider 51 a is released by removing the sacrificial layers 51s 1, 51s 2 in an aqueous or plasma environment. - FIGS. 11EA-11EB illustrate several alternate preferred embodiments of the first preferred T-LMC type. In
FIG. 11E A, an insulatingspacers 51 c is formed along the vertical edges of the flanges 51 p 1 a, 51 m 1 a. It provides better electrical isolation between theslider 51 a and the flanges 51p 1, 51m 1. InFIG. 11E B, dimples 51 d are added to the under-edge of theslider 51 a. They reduce the friction between theslider 51 a and thesubstrate 36. They can be fabricated by etching, preferably isotropically, a portion of the first sacrificial layer 51s 1 before theslider layer 51 a is deposited.FIG. 11E C further discloses a preferred embodiment using comb-drives. A plurality of interleavedfingers 51f 1 a, 51f 1 b are attached to theslider 51 a. They increase the capacitive driving forces exerted on theslider 51 a. Thus, it would take less time for theslider 51 a to switch position. As a result, the throughput of the programmable litho-system can be improved. Apparently, further improvement in throughput can be achieved if the comb-drives and the dimples are combined. -
FIG. 11F is a circuit symbol representing the preferred T-LMC illustrated in FIGS. 11CA-11CC and FIGS. 11EA-11EC. It comprises two capacitors 50 c 1 a, 50c 1 b. Each flange pair forms a capacitor: the flange pair 51 p 1 a/51 m 1 a forms a first capacitor 50 c 1 a; the flange pair 51p 1 b/51m 1 b forms a second capacitor 50c 1 b. Theslider 51 a is represented by a floating electrode. The capacitors 50 c 1 a, 50c 1 b are out-of-phase: when the capacitor 50 c 1 a is charged up, the capacitor 50c 1 b becomes discharged. Theslider 51 a is driven into the charged capacitor.FIG. 11G A illustrates a preferred peripheral circuit. It uses a DRAM-type circuit and comprises aswitch 61 s and aninverter 61 i. FIGS. 11GB-11GC are static peripheral circuits. Except for theadditional inverters i 1 b between two capacitors 50 c 1 a, 50c 1 b, these peripheral circuits are similar to those in FIGS. 10CA-10CC. - FIGS. 11HA-11I illustrate a second preferred T-LMC type. This preferred T-LMC type comprises a floating slider and its driving forces are both capacitive and elastic.
FIG. 11H A is a first preferred embodiment of this type. The driving force for its “OFF” state is provided by the flange pair 51p 2, 51m 2. However, the driving force for its “ON” state is an elastic force, which is generated by aspring 51 sp. One end of thespring 51 sp is attached to theslider 51 a and the other to the substrate by ananchor 51 sa. After the driving capacitor is discharged, the elastic force of thespring 51 sp pulls theslider 51 a away from theopening 70.FIG. 11H B illustrates a second preferred embodiment of this type. In this preferred embodiment, a comb-drive is used to increase the driving force for the “ON” state.FIG. 11I is the circuit symbol representing the second preferred T-LMC type. It is a capacitor 50 c 2 and can use the peripheral illustrated in FIGS. 10CA-10CC. - FIGS. 11JA-11MD illustrate a third preferred T-LMC type. In contrast to the first two T-LMC types, the slider in the third preferred T-LMC type is shorted to an external electrical signal. The driving forces for this T-LMC type are capacitive. It comprises a
flange pair 51 e and two opposing electrodes 51p 3, 51 m 3 (FIG. 11J A). Limited by theflange pair 51 e, theslider 51 a can only move along the y direction.FIG. 11J B is a cross-sectional view of the preferred embodiment along DD′. The T-LMC 40 comprises abase pair 51 g, which provides mechanical support as well as electrical contact to theslider 51 a. To reduce friction, dimples may also be used under theslider 51 a. Compared with other preferred T-LMC types, the inner surface of the flange pair in this preferred embodiment is not coated with a dielectric.FIG. 11K illustrates the circuit symbol representing the third preferred T-LMC type. It comprises twocapacitors 51 c 3 a, 51 c 3 b in series. The middle terminal corresponds to theslider 51 a.FIG. 11L is a preferred peripheral circuit. The two end terminals 51p 3 and 51m 3 are tied to VDD and GND, respectively. The voltage on the middle terminal 51 a is controlled by theconfiguration bit 44. This peripheral circuit is a dynamic circuit. Static circuits in FIGS. 10CB-10CC can also be used. - FIGS. 11MA-11MD illustrate a preferred process flow of the preferred embodiment in FIGS. 11HA-11HB. Compared with the process flow of the first preferred T-LMC type (FIGS. 11DA-11DC), an additional step is performed to form a
base pair 51 g (FIG. 11M A) before the first sacrificial layer 51s 1 is formed. - Rotor
-
FIG. 12E C illustrate various preferred in-plane rotational light-modulating cells (IPR-LMC). Its core element is arotor 52 a. All four corners STUV of therotor 52 a can rotate aroundaxle 52 b. When therotor 52 a covers theopening 70, it is at the “OFF” state (FIG. 12A ); when it rotates away from theopening 70, therotor 52 a is at the “ON” state (FIG. 12B ). - FIGS. 12CA-12CC illustrate a first preferred IPR-LMC type. This preferred IPR-LMC type comprises a floating rotor and its driving forces are capacitive. The
rotor 52 a is anchored to thesubstrate 36 by theaxle 52 b. It is further extended on two edges to form two fingers 52 f 1 a, 52f 1 b. These two fingers 52 f 1 a, 52f 1 b act as the floating electrodes for two capacitors 50 c 4 a, 40 c 4 b (formed by two electrode pairs 52 p 1 a/52 m 1 a, 52p 1 b/52m 1 b,FIG. 12C A).FIG. 12C B is a cross-sectional view of the floatingrotor 52 a and itsaxle 52 b along EE′. Limited by theflange 52 c on theaxle 52 b, therotor 52 a can only rotate in the x-y plane. Its inner surface is lined with a dielectric 52 d. It provides electrical isolation between therotor 52 a and theaxle 52 b.FIG. 12C C represents the circuit symbol for this preferred IPR-LMC type. It comprises two capacitors 50 c 4 a, 50 c 4 b. With a voltage on the capacitor 50 c 4 a but no voltage on the capacitor 50 c 4 b, therotor 52 a is driven into the capacitor 50 c 4 a and covers theopening 70. Accordingly, the IPR-LMC is at the “OFF” state. Otherwise, the IPR-LMC is at the “ON” state. The process flow for this preferred IPR-LMC type is similar to that in FIGS. 11BA-11BC. - FIGS. 12DA-12DD illustrate a second preferred IPR-LMC type. In this preferred IPR-LMC type, the rotor is shorted to an external electrical signal and the driving forces are capacitive. The first preferred embodiment in
FIG. 12D A andFIG. 12D B uses straight capacitor electrodes 52p 2, 52m 2. Their edges are lined with a dielectric 52 d. It provides electrical isolation between the electrodes 52p 2, 52m 2 and therotor 52 a.FIG. 12D C illustrates an alternate preferred embodiment of the second IPR-LMC type. Instead of straight capacitor, it uses fingered capacitor. The electrode fingers 52 f 2 a, 52 f 2 b form two capacitors 50 c 5 a, 50 c 5 b with the claw-like electrodes 52p 2 and 52m 2. These fingered capacitors provide more driving forces to therotor 52 a. The circuit symbol representing the second preferred IPR-LMC type is illustrated inFIG. 12D D. Its peripheral circuits are similar to those used by the third preferred T-LMC type. - FIGS. 12EA-12EC illustrate a preferred process flow for the preferred IPR-LMC of FIGS. 12DA-12DB. A first sacrificial layer 52
s 1 and arotor layer 52 a are deposited onsubstrate 36. They are etched to form arotor stack 52 t. Then a selective over-etch is performed on the sacrificial layer 52s 1. Not affecting therotor layer 52 a, this over-etch creates an undercut underneath therotor layer 52 a (FIG. 12E A). Afterwards, a second sacrificial layer 52s 2 is deposited around this structure and etched to expose a portion of substrate 36 (FIG. 12E B). This is followed by the formation of aflange layer 52 c and a capacitor finger 52m 2. To prevent electrical shorting between the capacitor fingers and therotor 52 a, a dielectric 52 d is formed around the capacitor finger 52 m (FIG. 12E C). - Hinge
- FIGS. 13AA-13CB illustrate various out-of-plane rotational light-modulating cells (OPR-LMC). Its core element is a
hinge 53 a. Thehinge 53 a rotates around ahub 53 h, which is confined by a staple 53 b. The four corners of thehinge 53 a are labeled as OPQR. At its “OFF” state, thehinge 53 a lays on the substrate and covers the opening 70 (FIGS. 13AA-13AB). At its “ON” state, thehinge 53 a rotates away from theopening 70. There are two possibility: a) it rotates ˜90 o from its “OFF” state in the x-z plane (FIG. 13A C); b) it rotates ˜180° from its “OFF” state in the x-z plane (FIG. 13A E) and corners QR move from the right-hand side of OP to their left-hand side (FIG. 13A D). - FIGS. 13BA-13BC illustrate a first preferred OPR-LMC.
FIG. 13B A is its plan view andFIG. 13B B is its cross-sectional view along I-I′. In this preferred embodiment, thehinge 53 a rotates ˜90° around itshub 53 h when it is switched from “OFF” to “ON” state. Thehinge 53 a and the staple 53 b are both located on a base 53 c, which provides electrical connection to thehinge 53 a. There are two electrodes 53p 1 and 53m 1 in the vicinity of thehinge 53 a. Besides driving thehinge 53 a, the electrode 53p 1 also acts as a stop that limits the degree of the hinge rotation. It comprises apost 53 ps and anarm 53 ar. Thearm 53 ar is enclosed by a dielectric 53 d. This dielectric provides electrical isolation between the electrode 53p 1 and thehinge 53 a. The circuit symbol representing this preferred embodiment comprises twocapacitors 53 c 6 a and 53 c 6 b (FIG. 13B C). They share onecommon electrode 53 a. Its peripheral circuits are similar to those of the third preferred T-LMC type. - The process flow of this preferred embodiment is similar to the third preferred T-LMC type. However, after the formation of the
staple layer 53 b, a third sacrificial layer 53s 3 is formed on top (FIG. 13B D). A via is formed inside the third sacrificial layer 53s 3 and filled with a conductor. After another pattern transfer, the electrode 53p 1 is formed. Finally, all sacrificial layers are removed and the whole structure is released. - FIGS. 13CA-13CB illustrate a second preferred OPR-LMC.
FIG. 13C A is a plan view andFIG. 13C B is a cross-sectional view along J-J′. In this preferred embodiment, thehinge 53 a rotates ˜180° from its “OFF” state to “ON” state. The electrodes 53p 2, 53p 2 are more symmetrical. The circuit symbol and peripheral circuit for this preferred embodiment are similar to those of the first preferred OPR-LMC. - Roller-Shade
-
FIGS. 14A-14C illustrate a preferred roller-shade LMC (RS-LMC). At its “OFF” state, theroller shade 54 a covers theopening 70 and anchors to thesubstrate 36 by aflange 54 f (FIG. 14A ). Theroller shade 54 a further comprises at least twothermal layers FIG. 14B ). They have different thermal expansion coefficients γ. Aresistor 54 r sits on the top surface of the roller-shade 54 a. When a current passes through theresistor 54 r and heats up the roller-shade 54 a, the γ difference between thethermal layers shade 54 a (FIG. 14C ). Accordingly, the RS-LMC switches to its “ON” state. - The roller-
shade 54 a can be modeled as a two-terminal resistor 54 r (FIG. 14D ). In its “ON” state, preferably a current runs through the roller-shade 54 a. Being resistive, its peripheral circuit is different from capacitive LMC. A first preferred circuit is illustrated inFIG. 14E A. Compared with the DRAM-style circuit inFIG. 10C A, the capacitor 50c 0 is replaced by a PMOS 64s 2 and aresistor 54 r. The gate voltage of the PMOS 64s 2 controls the current flow through theresistor 54 r. Its operation is similar toFIG. 10C A except that the RS-LMC switches to “ON” state when 44 is low. Similarly, the static circuits in FIGS. 10CB-10CC can also be used.FIG. 14E B illustrates a second preferred circuit. It comprises an NVM cell 64 nvm and its operation includes two steps. In the first step, the NVM cell 64 nvm is programmed by the configuration bit. At this time, the voltage on 64 g is high. This turns on the switch 64s 4 but turns off 64s 5. Thus, no programming current flows through theresistor 54 r. In the second step, the state of the NVM cell 64 nvm translates to the current flow through theresistor 54 r. At this time, 64 g is grounded. This turns off the switch 64s 4 but turns on 64s 5. As a result, appropriate voltages are applied on the address line 43 and the configuration-bit line 44. If the threshold voltage of the NVM cell 64 nvm is high, no current will flow through theresistor 54 r. On the other hand, if its threshold voltage is low, the cell 64 nvm is turned on and a current will flow through theresistor 54 r. Consequently, the roller-shade 54 a is rolled up. - Reflective LMC
- Much progress has been made in the reflective display. Two examples are digital micro-mirror display (DMD) and digital light valve (DLV). All these technologies can be used in reflective-OPM.
FIG. 15C illustrate several preferred reflective LMC (R-LMC). Preferably, it comprises areflector 55 a. On its four corners are four spring arms 55 sp and four anchors 55 sa. The cross-sectional views of these preferred embodiments along LL′ are illustrated inFIG. 15C , respectively. For DUV applications, the top surface of thereflector 55 a can be coated with interleaved silicon-molybdenum layers. The first preferred embodiment (FIG. 15B ) is a DMD. By adjusting the voltage on theelectrodes reflector 55 a is tilted. If there is no tilt, the incident light will be reflected straight back; otherwise, it will be reflected to a different direction. An alternate preferred embodiment (FIG. 15C ) is a digital light valve. Here, thereflector 55 a is a membrane. Portion of the incident light is reflected from its surface, with another portion being reflected by the substrate 36 (or thelower electrode 55 b). When there is no voltage on thelower electrode 55 b, thereflector 55 a is atlocation 55C; with a voltage applied on thelower electrode 55 b, thereflector 55 a is pulled tolocation 55D. Through different interference, the reflected light changes its intensity. - As mentioned earlier, reflective liquid-crystal can also be used for the R-LMC. Since its substrate is in the optical path, the peripheral circuit of liquid-crystal-based R-LMC can be built on a single-crystalline wafer. Meanwhile, the
reflector 55 a can be stacked on top of the peripheral circuit. Accordingly, the reflector (LMA) area is close to the LMC area, i.e. the fill ratio is nearly ideal. - c. Emissive-LMC
- Much works have been performed on the emissive display. Two examples are vertical-cavity surface emitting laser (VCSEL) and field-emission display (FED). They can also be used in emissive-LMC (E-LMC).
FIG. 16B illustrate a preferred E-LMC. The core element in this E-LMC is aVCSEL 56 a. It comprises two opposingelectrodes Bragg reflectors p-i-n laser medium 56 c-56 d. The VCSEL can be integrated with TFT's, which act as its peripheral circuit. The equivalent circuit of a VCSEL is a diode, which is a non-linear resistor (FIG. 16B ). Its peripheral circuits are similar to those of RS-LMC. They can be built in silicon or GaAs wafers. - C. 3D-LMC
- Three-dimensional LMC (3D-LMC) can improve the LMC density. In a 3D-LMC, the MEMS structures are built in multiple levels and can overlap each other. Thus the spacing between the LMC's can be reduced and the LMC's density be improved. FIGS. 17AA-17AC, FIGS. 17BA-17BC illustrate a preferred 3D-slider and 3D-rotor, respectively.
- FIGS. 17AA-17AC illustrate a preferred LMC with 3D-slider. For the reason of simplicity, only the core element of the LMC is shown in these figures. In
FIG. 17A A, two adjacent LMC's 40 x, 40 y are both in their “OFF” state. Note that the LMC disclosed in the earlier portion of the present invention has only one slider. In this preferred embodiment, theLMC 40 x comprises twosliders 51xa xa 2. Closing from its upper and lower sides, thesliders 51xa xa 2 cover theopening 70 x. TheLMC 40 y has a similar structure. InFIG. 17A B, the LMC's 40 x, 40 y are both at their “ON” state. Theslider 51xa 2 moves towards the lower side of theopening 70 x, while theslider 51 ya 1 moves towards the upper side. Since they are located at twodifferent levels 51A, 51B, thesliders 51xa FIG. 17A C). With a three-dimensional arrangement of the sliders, the spacing So between the openings can be reduced and the OPM can achieve a high density. - FIGS. 17BA-17BC illustrate a preferred LMC with 3D-rotor. Only the core element is shown in these figures. In
FIG. 17B A, two adjacent LMC's 40 x, 40 y are both in their “OFF” state. Note that the LMC disclosed in the earlier portion of the present invention has only one rotor. In this preferred embodiment, theLMC 40 x comprises four rotors 52 xa 1-51xa 4. Closing from its four corners, the rotors 52 xa 1-52xa 4 cover theopening 70 x. TheLMC 40 y has a similar structure. InFIG. 17B B, the LMC's 40 x, 40 y are both at their “ON” state. The rotors 52xa 3, 52xa 4 rotates ˜90° around their respective axles 52xb 3, 52xb 4, and the rotors 52 ya 1, 52 ya 2 rotates ˜90° around their respective axles 52yb 1, 52yb 2. Located at different levels 52A-52D (FIG. 17B C), the rotors 52xa 3, 52xa 4, 52 ya 1, 52 ya 2 can overlap each other. With a three-dimensional arrangement of rotors, the spacing So between the openings can also be reduced and the OPM can achieve a high density. - D. Manufacturing of the OPM Peripheral Circuit
- The manufacturing of the OPM peripheral circuit (i.e. TFT) may take advantage of the techniques developed in SOI (silicon-on-insulator) technology. The performance of the single-crystalline-silicon (sc-Si)-based TFT is better than α- or p-Si-based TFT.
FIG. 18D illustrate a preferred process flow for a sc-Si-based peripheral circuit. The starting material is an SOI wafer 350SOI (FIG. 18A ). It comprises asubstrate 350 s, a buried oxide film 350 o, and a silicon film 350 si. The SOI wafer 350SOI has a first surface 350 us and a second surface 350 ls. On the first surface 350 us, aquartz substrate 352 is thermally adhered to the SOI wafer 350SOI (FIG. 18B ). Then the backside of the SOI wafer 350SOI is ground from its second surface 350 ls until the buried oxide film 350 o is reached. This is followed by an etch of the buried oxide film 350 o, which exposes the silicon film 350 si (FIG. 18C). As a result, an sc-Si film 350 si is formed on top of thequartz substrate 352. This sc-Si film 350 si can be used as the substrate for the OPM peripheral circuit (FIG. 18D ). Apparently, other technologies developed in SOI (e.g. smart-cut) can also be used to form an sc-Si film on the mask substrate. Besides silicon, other semiconductor materials can also be used for peripheral circuits. - 3. Logic Litho-System
- In a logic litho-system, wafer pattern is generated through a series of litho-logic operations between mask patterns. Litho-logic operation can be performed between conventional masks, between OPM's, or between conventional mask and OPM. Typical litho-logic operations include litho-“OR” and litho-“AND”.
- One important consequence of the logic litho-system is pattern-distribution. With pattern-distribution, wafer patterns are distributed on a plurality of mask, or in a plurality of mask regions on a single mask. After performing a litho-logic operation to the images from these masks (regions), the desired wafer pattern can be obtained. Pattern-distribution can be used to improve the mask re-usability. It can further enable the mask-repair through redundancy (referring to FIGS. 33CA-33FC) and highly-corrected masks.
- A. “OR” Litho-System
-
FIG. 19C explain the concept of “OR” litho-system.FIG. 19B illustrate the images of mask patterns 88AP, 88BP projected on a wafer during exposure.FIG. 19C illustrates the final wafer pattern 88OLP after the photoresist development, which is the union of the mask patterns 88AP, 88BP. This litho-logic operation is referred to as litho-“OR”. During litho-“OR”, the reference point OA of the mask pattern 88AP coincides with the reference point OB of the mask pattern 88BP. - FIGS. 20AA-20EG illustrate several preferred “OR” litho-systems. The preferred embodiment in
FIG. 20C may need only one exposure pass, while all others need two exposure passes (without photoresist development between exposures). The preferred embodiments in FIGS. 20B-20EG are seamless multiple-exposure tools, i.e. mask patterns can self-align to each other during multiple exposures. It can achieve a higher throughput. - The preferred embodiments in FIGS. 20AA-20AB use a conventional litho-tool 120O1. It comprises a single projector. Two exposure passes 88EA, 80EB are performed to the
same wafer 22. During exposure pass 88EA, the image of themask 88A (i.e. the mask pattern 88AP) is projected on thewafer 22; during exposure pass 88EB, the image of themask 88B (i.e. the mask pattern 88BP) is projected on thewafer 22; and the wafer needs to be aligned between exposure passes. After all exposure passes are performed, photoresist is developed in a single step. - The litho-tool 120O2 in
FIG. 20B comprises twoprojectors 20A, 20B with a sharedstage 21M. Awafer 22 is exposed first to theprojector 20A. Then it steps forward and is exposed to the projector 20B. The relative placement of themasks mask 88A in theprojector 20A, thewafer 22 becomes self-aligned to themask 88B when it steps into the projector 20B. - The litho-tool 120O3 in
FIG. 20C comprises twoprojectors 20C, 20D with a 50/50beam splitter 24 s. Here, half of the light entering thebeam splitter 24 s is reflected with another half passing through. The image formed on thewafer 22 combines the images of themasks mask 88A passes through thebeam splitter 24 s; the images of themask 88B is reflected by thebeam splitter 24 s. In this preferred embodiment, only one exposure (flash) may be needed. It is acceptable to expose anotherwafer 22′ at the same time on theother side 120 d of thebeam splitter 24 s. This improves the throughput. - In FIGS. 20DA-20DB, a mask-steppable litho-tool 120O4 is used. It comprises one projector. Here, the
masks holder 88H and their relative placement is fixed. Besides precisely controlling the wafer stepping, this litho-tool 120O4 can precisely control the stepping of the mask-holder 88H. Similarly, wafer alignment between exposure passes may not be needed. - The preferred embodiment of FIGS. 20EA-20EG is an extension of FIGS. 20DA-20DB. Similar to FIGS. 20DA-20DB, it also uses a mask-steppable litho-tool 120O5 and comprises one projector. Unlike
FIG. 20D A-20DB where the mask patterns 88AP, 88BP come from twomasks FIG. 20E C, the mask patterns 88AP, 88BP come from twomask regions 88A′, 88B′ of aSINGLE mask 88. Accordingly, thismask 88 is referred to as pattern-distributed mask. On a pattern-distributed mask, that wafer patterns are distributed over a plurality of mask regions. Note that at least onemask regions 88A′, 88B′ can nearly fill thefull aperture 25 of the projector, and the combined range of thesemask regions 88A′, 88B′ exceeds that of thefull aperture 25. Here, the origin OA of themask region 88A′ (also designated as the origin MO of the mask 88) has a spacing Sx to the origin OB of themask region 88B′. With the help of the pattern-distributed mask, the control of the mask stepping can be simplified. - The pattern-distributed
mask 88 might be larger and heavier than a conventional mask. If gravitational sagging is a concern, asupport beam 88 s may be added thereunder between themask regions 88A′, 88B′. It provides mechanical support to themask 88 and will not interfere with the lithographic process. Note that thesupport beam 88 s can be used in the preferred embodiments ofFIG. 23A B,FIG. 24A B, andFIG. 33E A. For the reason of simplicity, it is not shown in these figures. - The exposure process in the mask-steppable litho-tool 12O5 is similar to that in FIGS. 20DA-20DB. Two exposure passes 80EA, 80EB are performed. During the first exposure pass 80EA, the
aperture 25 is aligned with themask region 88A′, e.g. OA coincides with the origin OO of the aperture 25 (FIG. 20E D). Dies 38 a-38 d are exposed one-by-one to themask region 88A′ (FIG. 20E F). Between two exposure passes, themask 88 makes a displacement of ΔS (ΔS=Sx) along the OX direction. Accordingly, during the second exposure pass 80EB, theaperture 25 is aligned with themask region 88B′, e.g. OB coincides with OO (FIG. 20E E). Similar, dies 38 a-38 d are then exposed one-by-one to themask region 88B′ (FIG. 20E G). At the beginning of two exposure passes 80EA, 80EB, the wafer origins WO, WO′ coincide. After exposures, a single development step forms wafer pattern. - B. “AND” Litho-System
-
FIGS. 21A-21C explain the concept of “AND” litho-system.FIGS. 21A-21B illustrate the first and second mask patterns 88AP, 88BP.FIG. 21C illustrates the final wafer pattern 88ALP, which is the intersection between mask patterns 88AP and 88BP. The litho-logic operation is referred to as litho-“AND”. During litho-“AND”, the reference point OA of the mask pattern 88AP coincides with the reference point OB of the mask pattern 88BP. -
FIGS. 22A-22B illustrate two preferred “AND” litho-systems.FIG. 22A is a transmissive “AND” litho-system 120A1. It uses twomasks masks FIG. 22B is a reflective “AND” litho-system 120A2. Images are only formed in areas where both themasks - C. Highly-Corrected Masks
- With the help of pattern-distribution, the feature spacing on a mask becomes larger. Accordingly, the OPC-computing can be reduced and more complex, higher-order correctional structures can be accommodated on the mask. This enables highly-corrected masks. FIGS. 23A-24BC illustrate several preferred highly-corrected masks.
- FIGS. 23AA-23AC illustrate a pattern-distributed mask to implement high-density vias and its related lithographic process.
FIG. 23A A illustrates the desired via patterns 18SI on wafer. The via shown here only means that this is a possible via location. If it is drawn in solid line (e.g. 18 a), the via exists; if it is drawn in dashed line (e.g. 18 b), there is no via. Typically, the via dimension Dv and spacing Sv are ˜1F - To implement the via patterns of
FIG. 23A A, a pattern-distributed mask 18MS with fourmask regions 18D (FIG. 23A B) and a logic litho-system employing four exposure passes can be used. On each mask region, there are only a fraction of via patterns. For example, themask region 18A only comprises viapatterns 18 e′, 18 g′, 18 m′, 18 o′. An exposure sequence is detailed inFIG. 23A C: duringexposure step 1, the origin O1 of themask region 18A coincides with OO, the displacement ΔS of the mask 18MS is (0, 0), and vias 18 e, 18 g, 18 m, 18 o are exposed on wafer; duringexposure step 2, the origin O2 of themask region 18B coincides with OO, ΔS=(−Sx, 0), and vias 18 a, 18 c, 18 k are exposed (no via at 18 i); duringexposure step 3, the origin O3 of themask region 18C coincides with OO, ΔS=(−Sx, Sy), and via 18 l is exposed (no vias at 18 b, 18 d, 18 j); duringexposure step 4, the origin O4 of themask region 18D coincides with OO, ΔS=(0, Sy), and vias 18 f, 18 p are exposed (no vias at 18 h, 18 n). - On the pattern-distributed mask 18MS, the via spacing Sv3 is ˜3F. This is three times larger than that on a conventional mask. In general, if a pattern-distributed mask comprises n2 mask regions, its via spacing could be (2n−1)× larger than that on a conventional mask. The pattern-distributed mask provides several benefits: First, the proximity effect between adjacent features is much less. This translates to less OPC computing and lower mask cost. Secondly and more importantly, the larger feature spacing can be used to accommodate higher-order correctional structures, thus enabling highly-corrected masks. In contrast, these higher-order correctional structures cannot be accommodated on conventional masks, because the feature spacings on these masks are much smaller and if these mask features were placed at the minimum spacing, their correctional structures would overlap. As a result, even if the same litho-tool is used, the highly-corrected masks can achieve much better lithographic resolution. Moreover, the highly-corrected mask can still be a binary mask. FIGS. 23BA-23DC illustrate several preferred highly-corrected masks.
- FIGS. 23BA-23BC illustrate a rim-shift PSM. Here, via 18 g′ is a zero-order clear pattern and the phase-
shifter 18 ps around the via 18 g′ is its first-order correctional structure. In prior arts, the width WCS of the phase-shifter 18 ps (Wcs is the spacing between the outer edge of the highest-order correctional structures and the outer edge of the zero-order clear pattern) cannot exceed F/2, because the spacing SV between adjacent vias could be 1F. This severely limits the design of the correctional structures. On a pattern-distributed mask, the via spacing Sv3 is much larger (≧3F) and Wcs increases by more than three-fold (˜3F/2). Accordingly, the phase-shifter 18 ps can be better sized and better lithographic resolution can be achieved. - With a much larger Wcs, higher-order correctional structures can be accommodated. FIGS. 23CA-23CC and FIGS. 23DA-23DC illustrate two
masks correctional ring 18 psa in FIGS. 23CA-23CB is separated from via 18 g′ by aspacer film 18 sf. Thespacer film 18 sf may comprise chrome, phase-shifter or even just a trench. Although it may comprise phase-shifter, thecorrectional ring 18 psa in FIGS. 23CA-23CB does not comprise phase-shifter and it is a clear pattern. Namely, themask 18A is a binary mask. Its fabrication is easier and costs less. From the E-field diagram ofFIG. 23C C, the E-field 18 psaE from the second-ordercorrectional ring 18 psa nearly cancels out the first-order diffraction maximum of the E-field 18 gE from the zero-order clear pattern (via 18 g′). The final exposure light 18 cE can render a good profile. - The preferred embodiments in FIGS. 23DA-23DB comprises a first-order
correctional ring 18 ps′ and a second-ordercorrectional ring 18 ps″ around the via 18 g′. In this preferred embodiment, the first-ordercorrectional ring 18 ps′ may comprise a phase-shifter, and the second-ordercorrectional ring 18 ps″ may not. From the E-field diagram ofFIG. 23D C, the addition ofE-field components 18 psE′, 18 psE″ from these two correctional structures can almost completely cancel out the first-order diffraction maximum of the E-field 18 gE. As a result, the final exposure light 18 cE′ can render an excellent profile. In fact, this preferred embodiment is an example of the second-order Fresnel plate. - Besides achieving better via resolution, pattern-distribution can achieve better line resolution. The high-
density line patterns 28 a-28 c ofFIG. 24A A can be distributed on a pattern-distributed mask 28MS ofFIG. 24A B. Here, only clear patterns, i.e. line-spaces (space between lines, a zero-order clear pattern), are distributed. Themask region 28A comprises line-space pattern 29 a′, 29 c′, while themask region 28B comprises the remaining line-space pattern 29 b′, 29 z′. The exposure sequence follows that in FIGS. 20EA-20EG. - The spacing Sm3 between the line-spaces on a pattern-distributed mask is much larger than the spacing Sm on a conventional mask. It can also accommodate high-order correctional structures. FIGS. 24BA-24BC illustrate several preferred correctional structures.
FIG. 24B A is similar toFIG. 23B A. Mask 28MSP comprises a first-order correctional structure 29 ps (a phase-shifter) along the edges of the line-space 29 b′. Its Wcs can exceed F/2. Similar toFIG. 23B B,mask 28B inFIG. 24B B comprises a second-order correctional structure 29 psa. It is a binary mask.FIG. 24B C is similar toFIG. 23B C. Mask 28B′ comprises first- and second-order correctional structures 29 ps′, 29 ps″. - D. Mask with Improved Re-Usability
- Logic litho-system can also improve the mask re-usability. For the IC with mature circuit and volatile circuit, wafer patterns can be distributed on at least two masks (or mask regions): one for mature circuit (mature mask) and the other for volatile circuit (volatile mask). Through litho-“OR”, the desired wafer pattern can be formed. The mature mask can be used in a number of products—an improvement of its re-usability. On the other hand, the data amount on the volatile mask is typically small and therefore, its fabrication is much less time-consuming and less expensive.
- a. System-on-a-Chip (SoC)
- Many SoC products comprise mask-programmable IC (MPIC). They can be integrated with other IC to implement many functions.
FIG. 25A illustrates the via patterns 80SOC in an SoC chip (SoC via patterns), which comprises an on-chip MPIC 80 mp and an on-chip ASIC 80 as. Note that the via patterns in theMPIC 80 mp may change frequently. Here, the SoC via patterns can be formed from two masks (or mask regions): an ASIC via mask 80ASO (FIG. 25B ) and an MPIC via mask 30MPO (FIG. 25C ). The ASIC via mask 80ASO comprises ASIC via patterns 90 aa, 90 ab, 90 ba, but not MPIC via patterns 90 bb-90 cc. The MPIC via mask 30MPO comprises MPIC via patterns 90 bb-90 cc, but not ASIC via patterns 90 aa, 90 ab, 90 ba. The desired SoC via pattern 80SOC can be formed through litho-“OR” between the ASIC via mask 80ASO and the MPIC via mask 30MPO. Apparently, besides via patterns, other layer patterns in an SoC chip can be formed in the same way. - b. Segmented-Lines
- By changing the locations of segment-gap, e.g. 161 g, the length of the segmented-
lines 161′, 161″ can be customized (FIG. 26A ). The segmented-lines can be implemented through litho-logic operation on two masks (regions): a continuous-line mask and a segment-gap mask.FIGS. 26B-26C illustrate several preferred implementations. -
FIGS. 26B-26C illustrate a continuous-line mask 80M and a segment-gap mask 80G. Theline patterns line mask 80M are dark patterns; the opening patterns 161 o, 162 o on the segment-gap mask 80G are clear patterns. Their relative position on wafer is illustrated inFIG. 26C . Through litho-“OR”, these twomasks FIG. 26A . By controlling the position of openings, the length of each segmented-line can be adjusted according to the customer's needs. Note that the extension 161 o of the opening 161 o over theline 161 has no effect on the final shape of segment-gap. Accordingly, the shape of the openings 161 o can be quite flexible (referring toFIG. 2B ). - A first preferred segmented-line process is illustrated in FIGS. 26DA-26DC (along C1-C2 of
FIG. 26A ). It is based on conventional metallization. During the first exposure,photoresist 18 pr is exposed to the continuous-line mask 80M. That exposure exposes everywhere exceptareas 161, 162 (FIG. 26D A). During the second exposure,photoresist 18 pr is exposed to theopening mask 80G, when the area 161 (i.e. inside segment-gap 161 g) is exposed (FIG. 26D B). After development, only photoresist in thearea 162 remains. - A second preferred segmented-line process is based on damascene technique. In damascene, a trench needs to be formed before the metal-filling. A
conventional trench mask 80T (FIG. 26E ) is complementary to the continuous-line mask 80M and is not suitable for litho-“OR”. To accommodate the need from damascene, negative photoresist is preferably used during the lithographic process. With negative resist, the same mask set (i.e. the continuous-line mask 80M and the segment-gap mask 80G) can be used to form the trench pattern required by damascene. The associated process flow (FIGS. 26FA-26FC) is similar to that in FIGS. 26DA-26DB, except thatphotoresist 18 pr is only removed in thearea 162 but remains in all other areas. Apparently, this process flow results in the same segmented-line pattern as FIGS. 26DA-26DC. - E. Thin-Film Mask
- Logic litho-system can also be used in thin-film mask (e.g. X-ray mask, e-beam mask). Thin-film mask is built on a fragile thin film (e.g. silicon nitride). In order to improve the mask's durability, support beams are desired under the thin-film mask. To accommodate supporting structures such as support beams, a pattern-distributed mask is to be used, i.e. wafer patterns are distributed over multiple mask regions. Within each mask region, there are invalid exposure areas. These invalid exposure areas contains can be used to build support beams. The final wafer patterns are formed by performing litho-logic operation on these mask regions.
- FIGS. 27AA-27BB illustrate a first preferred thin-film mask. It comprises a
first mask regions 135A and asecond mask region 135B. FIGS. 27AA-27AB are the plan view and cross-sectional views of thefirst mask region 135A. Support beam 138s 1 is built in thefirst mask region 135A. In this preferred embodiment, the area within the support beam 138s 1 is the invalid exposure area. The wafer patterns in the invalid exposure area reside on thesecond mask region 135B. FIGS. 27BA-27BB are the plan view and cross-sectional view of thesecond mask region 135B. The patterns of the support-beams 138s 2, 138s 3 complements the pattern of the support beam 138s 1. Through litho-“OR”, themask patterns 137 b′, 137 c on thesecond mask region 135B and themask patterns first mask region 135A form the desired wafer pattern. In this preferred embodiment, there is no mask pattern in the invalid exposure areas 138 s 1-138s 3. - FIGS. 27CA-27DB illustrate a second preferred thin-film mask. Compared with the first preferred thin-film mask, the invalid exposure area 138
s 1′ in the second preferred thin-film mask is defined by the mask pattern 138s 1′, but not by the support beam 138s 1. Thus, the invalid exposure area 131s 1′ is more accurately defined. Moreover, there is more design freedom for support beams. For example, straight support beam 138s 1′ can be used. - 4. Design-for-Litho-Programming (DFL)
- Ideally, a few general-purpose masks (GPM) can be used in most lithographic processes. To maximize the usage of the GPM, the IC layout preferably follows “design-for-litho-programming (DFL)”.
- A. General-Purpose Masks (GPM)
- Examples of GPM include uniform opening-programmable mask (UOPM) and uniform metal-line mask (UMLM). On an UOPM, all programmable openings have the same size Do and same spacing So, preferably 1F or 2F (
FIG. 28A ); On an UMLM, all metal lines are continuous and have the same width Dm and same spacing Sm, preferably 1F (FIG. 28B ). One advantage of the UMLM is that it is highly regular and can fully utilize the advanced mask-making techniques such as alternative PSM. To maximize the usage of the GPM, the IC layout preferably follows the DFL. The DFL includes via DFL and metal-line DFL. - B. Via DFL
- A preferred via DFL is illustrated in
FIG. 29A . It can be used to implement the SoC via pattern inFIG. 25A . Note that inFIG. 25A , the via 90 ba is not aligned with its adjacent vias. In order to use theUOPM 30U, the via 90 ba has to be displaced by δ so that it coincides with its nearestprogrammable opening 50 ba. Because the spacing So between programmable openings is ˜1F on theUOPM 30U, δ is no larger than ˜F/2. Namely, the via DFL has small effect on the via layout. - C. Line DFL
- The implementation of segmented-lines requires the alignment of the continuous-
line patterns 80M and the segment-gap patterns 80G. The segment-gap patterns 80G can be generated by anUOPM 30U. Accordingly, the continuous-line patterns, at least the continuous-line patterns subject to programming, can coincide with programmable openings on theUOPM 30U. If theline 166 is wider than 1F (FIG. 29B A), it is preferably split into afew sub-lines 168, 169 (FIG. 29B B) or at least afew sub-lines programming area 166 pa (FIG. 29B C). The width of these sub-lines is smaller than or equal to that of the programming openings, preferably equal to 1F; the pitch of these sub-lines is equal to the period of the programming openings, preferably 2F Combined withopenings 50 bb, 50 cb, the desired segmented-lines can be generated. - 5. Composite Litho-System
- Composite litho-system combines programmable litho-system with logic litho-system. Besides programmable SoC and programmable lines, the composite litho-system enables the application of manufacturable OPM in advanced lithography. It can also improve the mask yield and offer longer exposure endurance to OPM.
- A. Programmable SoC
- In the preferred embodiment of
FIG. 25C , the MPIC via patterns are formed from a custom opening mask. In fact, it can be created from the OPM 80MPO′ ofFIG. 30A . In theASIC area 80 as, all corresponding programmable openings are at the “OFF” state; only in theMPIC area 80 mp, the OPM 80MPO′ generates valid opening patterns. Accordingly, the OPM 80MPO′ offers programmability to SoC chips. - B. Programmable Line Pattern
- Line patterns can be formed by merging a plurality of square openings and they can be programmable.
FIG. 30B A illustrates a line pattern, i.e. merged opening 50o 3. It can be formed by a single OPM 30O3 in an “OR” litho-system. To be more specific, it can be formed by multi-pass exposures with displacement. Here, two exposure passes are performed and the OPM 30O3 is displaced relative to the wafer by ΔS between the exposure passes. The first exposure pass forms afirst opening 50 oa (FIG. 30B B); the second exposure pass forms asecond opening 50 ob (FIG. 30B C). These opening patterns are merged to form the desired line pattern 50o 3. More details on multi-pass exposure with displacement will be disclosed in FIGS. 31CA-31DC′. The programmable line pattern can also be used to formgap 166 g in wide metal lines (FIG. 29B A). As illustrated in FIGS. 30CA-30CB, two exposure passes are performed and the OPM is displaced relative to the wafer by ΔS between the exposure passes. The combinedopenings 50 bb, 50 bb′ cut thewider metal line 166. - C. Deep-Sub-μm Litho-Programming Based on Manufacturable OPM
- In a composite litho-system, litho-programmable deep-sub-μm features (˜0.25 μm) can be rendered by manufacturable OPM (˜5 μm). FIGS. 31AA-32B illustrate several preferred implementations of the litho-programmable deep-sub-μm openings through litho-logic operation.
- FIGS. 31AA-31AB illustrate a preferred implementations of the litho-programmable deep-sub-μm openings through litho-“OR”. It uses two OPM's 30Z, 30W. Each OPM comprises a plurality of LMC's 40 z 1-40
z 3, 40 w 1-40w 3. The LMC 40z 2 on OPM 30Z is always dark, with another two LMC's 40z 1, 40z 3 programmable (FIG. 31A A); The LMC's 40w 1, 40w 3 onOPM 30W are always dark, with another LMC 40w 2 programmable (FIG. 31A B). On wafer, the pattern from each LMC's 40 z 1-40z 3 is aligned to and combined with pattern from each LMC's 40 w 1-40w 3. Although the LMC 40 z 2 (40w 1, 40 w 3) is always dark, its counterpart LMC 40 w 2 (40z 1, 40 z 3) on theOPM 30W (30Z) can still program the corresponding wafer opening. As a result, every wafer opening is still programmable. - The LMC 40
z 2 in FIGS. 31AA-31AB is always set to dark. This can be easily accomplished by removing the ODP opening at this “always-dark” LMC 40z 2. Accordingly, no structure needs to be built for this “always-dark” LMC 40z 2 and an adjacent LMC can extend into its area. Occupying more area, this adjacent LMC is easier to design and manufacture. -
FIG. 31B A illustrates a preferred LC-OPM 30LOX whose LMC extends into the adjacent cells. Here, LMC 401 a 3 extends to an adjacent “always-dark” LMC (such as 40z 2 inFIG. 31A A). If it can extend to three “always-dark” LMC's, the dimension of this LC-LMC could be 2R×Pwo. For a 0.25 μm opening and a conventional 4× litho-tool, this value could be as large as 4 μm. The LMC of this size is highly manufacturable and reliable. On the other hand, because the openings imaged on wafer are separately controlled by theODP opening 70 la 3, they can still be small and have fine features.FIG. 31B B illustrates a preferred MEMS-OPM 30MOX whose LMC extends into the adjacent cells. Similarly, its LMC can use a larger, more manufacturablemovable elements 51 a. - In the preferred embodiments of FIGS. 31AA-31BB, two OPM's 30Z, 30W are used. In fact, one OPM is all needed to form the desired wafer pattern. FIGS. 31CA-31DC′ illustrate two preferred implementations. These implementations are based on multi-exposure with displacement. This method is also referred to as inter-leaved stepping.
- The preferred implementation in FIGS. 31CA-31CC′ is based on a multi-exposure with mask displacement. It is similar to FIGS. 20EA-20EB, except that mask in this embodiment is an
OPM 38. During the first exposure pass 80EA, theOPM 38 coincides with theaperture 38A of the litho-tool, and it has a first mask pattern 38(80EA) (FIG. 31C A). Dies 38 a-38 d onwafer 22 are exposed one-by-one to the first mask pattern 38(80EA) (FIG. 31C B). The first exposure pass 80EA exposes a first half of the wafer openings 78 za-78 zh (FIG. 31C C). Their state is determined by the first mask pattern 38(80EA). At the beginning of second exposure pass 80EB, theOPM 38 is displaced by ΔS (ΔS is preferably equal to the mask opening period Po) relative to theaperture 38A, i.e. its origin moves from MO to MO′. Meanwhile, theOPM 38 acquires a second mask pattern 38(80EB) (FIG. 31C A′). The second exposure pass exposes a second half of the wafer openings 78 za′-78 zh′ (FIG. 31C C′). Their state is determined by the second mask pattern 38(80EB). Note that, at the beginning of each exposure pass, the wafer origin WO makes no displacement (FIG. 31C B′). With a single development step after all exposures, the desired opening pattern is formed on wafer. - The preferred implementation in FIGS. 31DA-31DC′ is based on a multi-pass exposure with wafer displacement. During the first exposure pass 80EA, the
OPM 38 has a first mask pattern 38(80EA) (FIG. 31D A). Dies 38 a-38 d onwafer 22 are exposed one-by-one to the first mask pattern 38(80EA) (FIG. 31D B). The first exposure pass 80EA exposes a first half of the wafer openings 78 za-78 zh (FIG. 31D C). Their state is determined by the first mask pattern 38(80EA). During the second exposure pass 80EB, theOPM 38 acquires a second mask pattern 38(80EB) (FIG. 31D A′) and a second half of the wafer openings 78 za′-78 zh′ are exposed (FIG. 31D C′). Their state is determined by the second mask pattern 38(80EB). With a single development step after all exposures, the desired opening pattern is formed on wafer. Compared with FIGS. 31CA-31CC′, the first and second half openings 78 za-78 zh, 78 za′-78 zh′ here switch position. Note that during both exposure passes, theOPM 38 makes no displacement; however, at the beginning of each exposure pass, the wafer origin is displaced by ΔS (from WO to WO′), where ΔS is preferably equal to the wafer opening period Pw. - FIGS. 32AA-32AB illustrate a preferred implementation of the litho-programmable deep-sub-μm openings through litho-“AND”. It comprises two LMP's 38X, 38Y. On the
LMP 38X, the LMA 50 x 2 is always clear, with another two LMA's 50 x 1, 50 x 3 programmable (FIG. 32A A); on theLMP 38Y, the LMA's 50y 1, 50y 3 are always clear, with another LMA 50y 2 programmable (FIG. 32A B). During exposure, two LMP's 38X, 38Y and anODP 32 are aligned to each other. Wafer patterns are formed through litho-“AND” (FIG. 32A C). For the “always-clear” LMA 50 x 2, it does not modulate light and therefore, does not need peripheral circuit. Accordingly, its peripheral-circuit area can be used by the adjacent LMC 50 x 1.FIG. 32B illustrates a preferred LC-LMP 38LAX whose LMA 501s 3 extends into the adjacent peripheral-circuit area. Its LMC is larger and more manufacturable. - D. Mask Inspection and Repair
- During its usage, an OPM preferably go through a field inspection so as to ensure the desired pattern is generated. FIGS. 33AA-33BB illustrate a field-inspectable programmable litho-system. It comprises an
image sensor 30 v. It is placed into the exposure-light path after theOPM 30 t is configured but before thewafer 22 is exposed (FIG. 33A A). Preferably, at the location ofimage sensor 30 v, the image from the OPM patterns has not been reduced by the litho-tool. Accordingly, theimage sensors 30 v can use larger sensing cells. This will benefit the signal integrity and lower the sensor cost. The sensedsignal 16 v (from theimage sensor 30 v) is compared with theconfiguration data 16. If they match, theimage sensor 30 v is removed from the exposure-light path and awafer 22 is exposed (FIG. 33A B); otherwise, theOPM 30 t needs to be checked. -
FIG. 33B A illustrates an OPM pattern during exposure. Based on theconfiguration data 16, the light intensity on theLMC 50 sa′-50 sd′ are varied; theODP openings 70 sa′-70 sd′ define the final shape of the wafer openings.FIG. 33B B is apreferred image sensor 30 v. It comprises a plurality of sensingcells 70 va′-70 vd′ and aperipheral circuit 16 c. Thesensing cells 70 va′-70 vd′ can be based on conventional image-sensing techniques, such as CCD, CMOS imager. Theperipheral circuit 16 c collects the sensedsignal 16 v. During field inspection, thesensing cells 70 va′ is aligned with theLMC 50 sa′ (FIG. 33A A), and preferably encompasses thepattern 70 pa′ imaged by theODP opening 70 sa′ thereon. - Logic litho-system can be used to improve the mask yield. The primary mask (i.e. the mask that is supposed to form wafer patterns) likely has defects. A redundant mask (region) can remedy these defects through litho-logic operation. OPM is well suited for the redundant mask (region). FIGS. 33CA-33FC illustrate several preferred mask-repair means.
- FIGS. 33CA-33CC illustrate a preferred mask-repair means based on litho-“OR”. In this preferred embodiment, the
primary OPM 30 p works with aredundant OPM 30 r to form the desired wafer patterns. In the “OR” litho-system, each redundant LMC (i.e. the LMC on theredundant OPM 30 r, e.g. 40 r) corresponds to a primary LMC (i.e. the LMC on theprimary OPM 30 p, e.g. 40_1). For the non-defective primary LMC 40_2, the corresponding redundant LMC 40r 2 is at the “OFF” state; for the defective primary LMC 40_1 (FIG. 33C A), its correctional pattern is now carried by the redundant LMC 40 r 1 (FIG. 33C C). Meanwhile, means such as FIB (focused ion beam) is used to darken the defective LMC 40_1 (FIG. 33C B) by, for example, filling a light-absorptivematerial 51 af to thedefect site 51 ad. - In fact, the OPM can perform self-repair. This involves multi-exposure with displacement. FIGS. 33DA-33DB illustrate a preferred OPM with self-repair. Here, the LMC 40_1 on the
OPM 30 is defective and is subsequently darkened; the LMC 40_2 is non-defective. After a primary (first)exposure 20P, theOPM 30 is displaced relative to the wafer by ΔS and a redundant (second)exposure 20R is performed. At this time, the image of the LMC 40_2 formed on wafer is located at where the image of the LMC 40_1 should have been during theprimary exposure 20P, and all LMC's corresponding to the non-defective primary LMC's are at the “OFF” state. Because the LMC 40_2 carries the designated pattern for the defective LMC 40_1, the desired wafer patterns can be formed. The OPM self-repair needs only one mask. - Besides the OPM-repair, non-programmable (conventional) masks can be repaired based on pattern-distribution. In prior arts, the mask is repaired at the defect sites. Because a typical mask is “feature-dense”, this “repair-at-site” scheme will likely damage the adjacent “known-good” mask features and therefore, is error-prone. It is even more difficult to repair the PSM and OPC-masks. The present invention provides a “repair-through-redundancy” scheme for the defective mask. After clearing or darkening the defect sites (depending on the logic litho-operation to be used), instead of “repair-at-site”, the correctional structures are formed in another (redundant) region on the mask or on a different (redundant) mask. This repair step will unlikely interfere with other “known-good” mask patterns. As a result, “repair-through-redundancy” is more reliable and robust.
-
FIG. 33E A illustrates a pattern-distributedmask 88. It comprises aprimary mask region 88P and aredundant mask region 88R. Theprimary mask region 88P comprises a plurality of darkened areas 40_1, 40_3. These darkened areas cover the defect sites and are preferably formed by, for example, filling a light-absorptivematerial 51 af on the defect sites (FIG. 33E B). Theredundant mask region 88R comprises a plurality of correctional areas 40r 1, 40r 2. Each correctional area 40r 1 corresponds to a darkened area 40_1 in theprimary mask region 88P and it carries the designated patterns for the defect site 40_1 (FIG. 33E C). Through litho-“OR”, the patterns from thesemask regions - Alternatively, the OPM can also be used be repair a non-programmable mask. The advantage of the OPM-repair is that the OPM can be readily configured for the mask-repair purpose. This configuration step can be carried out in a short time. Accordingly, the field-repair for the defective opening masks becomes feasible.
- FIGS. 33FA-33FC illustrate an alternate preferred mask-repair means based on litho-“AND”. The
primary LMP 38 p comprises a defective LMC 40_1 (FIG. 33F A). Thedefect 51 ad′ is cleared by, for example, a laser beam or FIB, and therefore, the LMC 40_1 becomes always clear (FIG. 33F B). Aredundant LMP 38 r′ is aligned with theprimary LMP 38 p and theODP 32. The redundant LMC 40r 1′ performs light-modulation for the defective primary LMC 40_1; and other redundant LMC's corresponding to the non-defective primary LMC's are always at the “ON” state (FIG. 33F C). This method can also be extended to the repair of non-programmable masks. - E. Long-Term Exposure Endurance
- During long-term exposure, an OPM may become over-heated. FIGS. 34AA-34BB illustrate a preferred method to avoid over-heating during the long-term exposure of an OPM. In this preferred embodiment, the LMP 38LAX and the
ODP 32 are located on two separate substrates. Between two exposures 20E1, 20E2, the LMP 38LAX is displaced by MD while the location of theODP 32 is fixed. Accordingly, during two exposures 20E1, 20E2 to the LPM 38LAX, the exposure light passes throughdifferent LMA areas LMA area ODP 32 is fixed, the LMP displacement does not affect the final pattern formed on wafer. - 6. Applications of Low-Cost Lithography
- Low-cost lithography combines techniques such as nF-opening mask, programmable litho-system, and logic litho-system. It is ideal for the litho-programmable integrated circuits (LP-IC). Examples of LP-IC include litho-programmable SCIC (LP-SCIC) and litho-programmable ASIC (LP-ASIC). Low-cost lithography can also be used during the fabrication of conventional masks and master optical discs.
- A. Litho-Programmable Integrated Circuits (LP-IC)
- An LP-IC comprises a plurality of litho-programmable opening-related patterns (e.g. litho-programmable inter-level connections and litho-programmable segmented-lines). It can be implemented with an UOPM and optionally with an UMLM. In an LP-IC flow (
FIG. 35 ), a customer first creates a set of customer data; then s/he sends to the fab an order, which has an order volume; the fab returns with a price quote. The overall expected revenue for this order, which is the product of the order volume and the price quote, can be smaller than the cost of the conventional custom opening-mask set corresponding to said opening-related patterns. In contrast, in prior arts, the completion of the same order involves making a new set of (conventional) custom masks. The manufacturing cost, including other processing and materials costs, should at least be higher than the cost for these masks. Namely, the overall expected revenue of the conventional (non-litho-programmable) IC cannot be lower than the mask cost. Accordingly, the present invention differentiates the LP-IC from conventional IC through their expected revenues for a specific order. - One example of LP-IC is litho-programmable SCIC (LP-SCIC). In an LP-SCIC, a limited number of custom layers are formed by litho-programming. The LP-SCIC includes litho-programmable ROM (LP-ROM) and litho-programmable PGA (LP-PGA). Another example of LP-IC—litho-programmable ASIC (LP-ASIC)—goes even further. By taking full advantage of low-cost lithography, its back-end process eliminates the needs for custom masks (at least expensive custom masks). The front-end layers of LP-ASIC are fully customized, just like a conventional ASIC. This can reduce chip area and realize high-speed circuit. The back-end design needs to follow a more stringent ASIC-DFL: in at least one metal layer of the LP-ASIC, all metal lines are aligned along a first direction with their width and spacing preferably equal to 1F; in a metal layer next to said metal layer, all metal lines are aligned along a second direction with their width and spacing also preferably equal to 1F. By repetitively using the GPM such as UOPM and UMLM, all interconnect patterns can be formed without using custom masks. To accomplish the same task in a conventional ASIC, tens of custom masks are needed. Moreover, these GPM's are shared in many LP-ASIC products, they add little cost to the ASIC chips.
- FIGS. 36AA-36AB illustrate two preferred GPM's.
FIG. 36A A illustrates a 2F-UOPM 30U2 andFIG. 36A B illustrates a 1F-UMLM 80UM (also shown inFIG. 28B ). On the 2F-UOPM 30U2, its LMC size Do′ and spacing So′ are equal to 2For at least around 2F The 2F-UOPM 30U2 has better manufacturability and can also implement segment-gaps and inter-level connections (referring toFIGS. 2A-2B ). Alternatively, the 1F-UOPM ofFIG. 28A can be used. - FIGS. 36BA-36BC illustrate a preferred implementation of LP-ASIC using the GPM. The
interconnects 00 as inFIG. 36B A are the typical interconnects encountered in an ASIC layout. They involve two metal levels and include a wide metal line 201 (with width equal to 2F), abended line 203/203′ (its twosections FIG. 36A A) and an UMLM (FIG. 36A B). FIGS. 36BB-36BC illustrate the LP-ASIC interconnects 00 lp equivalent to interconnects 00 as ofFIG. 36B A. Here, all upper-level metal lines 00UM are aligned along the x direction, and all lower-level metal lines 00LM are aligned along the y direction. For thewide metal line 201 ofFIG. 36B A,FIG. 36B B uses two 1F upper-level metal lines level metal segments 221′, 222′ and amerged aiv 251. For thebended line 203/203′,FIG. 36B B stays the same. For the displacedline 202, a conventional ASIC only uses a single lower-level metal line. However, according to the ASIC-DFL, the LP-ASIC segment along the x direction has to be implemented by the upper-level metal line 00UM (FIG. 36B B). Accordingly, the equivalence of the displacedline 202 includes threemetal segments 222″ (OOLM), 214′ (OOUM), 224′ (OOLM), and twoaivs - To implement the lower-
level metal lines 221′-224′ of FIGS. 36BB-36BC, the UMLM 80UM is placed along the y direction in the litho-tool. To realize the gaps betweenmetal segments 221′ and 221″, 222′ and 222″, 223′ and 223″, a first litho-“OR” is performed on the UOPM 30U2 (referring toFIGS. 26A-26C ). During the first litho-“OR”, the UOPM 30U2 has a first opening configuration 230LG (including openings 231-232) and its relative placement to the lower-level metal pattern (including metal lines 221-224) is illustrated inFIG. 36C A. Apparently, the openings (e.g. 231) divide the metal lines (e.g. 221) into the segments (e.g. 221′, 221″) ofFIG. 36B B. - To implement the upper-level metal lines 211-214′ of FIGS. 36BB-36BC, the UMLM 80UM is placed along the x direction in the litho-tool. Meanwhile, to realize the gaps between
metal segments 213′ and 213″, 214′ and 214″, a second litho-“OR” is performed on the UOPM 30U2. During the second litho-“OR”, the UOPM 30U2 has a second opening configuration 240UG (including openings 241-242) and its relative placement to the upper-level metal pattern (including metal lines 211-214) is illustrated inFIG. 36C B. Apparently, the openings (e.g. 241) divide the metal lines (e.g. 213) into the segments (e.g. 213′, 213″) ofFIG. 36B B. - Finally, to implement the inter-level connections of FIGS. 36BB-36BC, the UOPM 30U2 is again used.
FIG. 36C C illustrates its third opening configuration 250O (including openings 251-254) and its relative placement to the lower/upper-level metal patterns. These openings (e.g. 252) provide inter-level connections between the lower- and upper-level metal lines (e.g. 213, 223). Note that all three opening patterns 230LG, 240UG, 250O are generated by a single UOPM 30U2. -
FIG. 36D illustrates an alternate preferred implementation ofwide metal line 201 ofFIG. 36B A. It uses a custom metal mask 80CM. The desiredmetal line 201 is formed by performing litho-“AND” on said custom metal mask 80CM and the UMLM 80UM. During litho-“AND”, their relative placement is illustrated inFIG. 36D . On the custom metal mask 80CM, themetal pattern 167′ is only needed at places corresponding to thewide metal lines 201 ofFIG. 36B A, and its width only needs to be larger than the line-spacing 167 s (˜1F). To implement gaps onwide metal line 201, multi-exposure with displacement of FIGS. 30CA-30CB can be used. Since the custom metal mask 80CM only contains wide metal lines (>1F), which can tolerate large width and alignment error, the mask and processing costs are fairly low. - The LP-ASIC implementations in FIGS. 36AA-36CC not only can be used in a standalone ASIC, but also in SoC designs with embedded ASIC.
FIG. 36E illustrates apreferred SoC chip 00 with anASIC block 00 as and a plurality offunctional blocks 00 fb. The functional blocks 00 fb usually contains IC blocks with third-party IP, such as memory blocks (RAM, ROM, etc) and processing blocks (CPU, DSP, etc). The SoC patterns can be implemented through litho-“OR” between two mask sets: one for theASIC block 00 as (ASIC mask set), the other for thefunctional blocks 00 fb (functional-block mask set), as in the case ofFIGS. 25A-25C . The ASIC mask set follows the LP-ASIC implementations. The functional-block mask set may be provided by IP-vendors, or may also follow the LP-ASIC implementations. -
FIG. 36F illustrates a preferred design flow of LP-ASIC. Similar to a conventional ASIC, it includes steps such asHDL description 00H,netlist extraction 00N,placement 00P, routing 00R, and tape-out 00T. However, therouting 00R of LP-ASIC needs to follow the ASIC-DFL. Moreover, only front-end layout needs to be taped out 00T. The back-end output is not layout, but the state or location of openings. It has small data amount and can be delivered to the fab through the internet. - B. Quasi-Opening Programmable Mask (QOPM)
- Low-cost lithography, more particularly OPM, can also be used to fabricate conventional masks, particularly the conventional mask with regularly-sized and -spaced openings, as in the case ROM, PGA and others. Accordingly, this type of conventional mask is referred to as quasi-opening programmable mask (QOPM).
FIGS. 37A-37C illustrate a preferred process flow. -
FIG. 37A illustrates a preferred process flow to fabricate a QOPM from an OPM. It is similar to conventional lithographic process. However, the image carrier here is not a wafer, but a mask blank 80SP coated with photoresist (QOPM blank). The QOPM 80SP comprises a plurality ofQOPM units 39 a-39 p. Each QOPM unit corresponds to the exposure field of the OPM during one exposure. In the programmable litho-system, the QOPM blank 80SP steps and theQOPM units 39 a-39 p are exposed one-by-one with respect to theOPM 30. Between exposures, the OPM patterns are adjusted based on the configuration data. For example, during the exposure 80Ea to theQOPM unit 39 a, theOPM 30 has a first pattern 30(80Ea) and theLMC 50 sb is at the “OFF” state (FIG. 37B A); during the exposure 80Eb to theQOPM unit 39 b, theOPM 30 has a second pattern 30(80Eb) and theLMC 50 sb is at the “ON” state (FIG. 37B B). Accordingly, on the QOPM 80SP, no opening is formed atlocation 72 b, and an opening is formed atlocation 72 b′ (FIG. 37C ). Note the shape of theseopenings 72 b′ is controlled by theODP openings 70 sa-70 sd, 70 sa′-70 sd′. Besides simple side-by-side stepping, inter-leaved stepping of FIGS. 31CA-31DC′ can also be used during the fabrication of the QOPM. - From
FIGS. 37A-37C , the LMC period Po on theOPM 30 is R times the opening period Pq on the QOPM 80SP. If a same litho-tool is used to expose the QOPM 80SP to a wafer, Po can be R2 times the wafer opening period Pw. By “imaging twice” (first from an OPM to a QOPM, then from the QOPM to a wafer), the image reduction ration from the OPM to the wafer is R2. With atypical R 4×-5×, the LMC can be 16×-25× larger than Pw. For example, at the 0.13 μm node, an LMC could be ˜5 μm. The LMC of this size is highly manufacturable and reliable. Moreover, the QOPM openings have a size of ˜1 μm. The openings of this size can be formed by a conventional optical litho-tool and configured by an LC-LMC (e.g. an off-shelf LCD from the micro-display industry). Accordingly, a QOPM can be fabricated in-house. It has a short turn-around time and offers better user-configurability. In sum, the QOPM is a very practical intermediate step for low-cost lithography. - C. Master Optical Disc
- Low-cost lithography, more particularly OPM, can also be used to fabricate master optical discs. This process is similar to the fabrication of the QOPM, except that the image carrier now is a master
optical disc 86D. The masteroptical disc 86D is circular and has spiral tracks. The spacing between each turn of spiral is Ss (FIG. 38A ). Digital “0” and “1” is represented through the existence and absence of pits. - An OPM 30DM can be used to fabricate the master
optical disc 86D. The LMC's 50 da-50 dg on the OPM 30DM form an arc (FIGS. 38BA-38BB). It controls the existence of pits within a degree θ on the master optical disc. In this preferred embodiment, θ is 90°. Similar to the QOPM, the master optical disc steps in a programmable litho-tool and is exposed one section after another. At each exposure, the OPM 30DM adjusts its pattern according to the configuration data. During exposure 80EM1, the OPM 30DM has a first pattern 30DM(80EM1) (e.g. theLMC 50 de is at the “ON” state) (FIG. 38B A) and the disc section 86DA is exposed.FIG. 38C A illustrates the position and orientation of the masteroptical disc 86D during the exposure 80EM1. During exposure 80EM2, the OPM 30DM has a second pattern 30DM(80EM2) (e.g. theLMC 50 de is at the “OFF” state) (FIG. 38B B) and the disc section 86DB is exposed.FIG. 38C B illustrates the position and orientation of the masteroptical disc 86D during the exposure 80EM2. Relative to the exposure 80EM1, the masteroptical disc 86D rotates around its origin 860(80EM2) by θ and displaced by ΔS (preferably equal to θ/360°×Ss). In this preferred embodiment, at least four exposures are needed to form the whole master disc. - 7. Business Model
- The LP-IC preferably follows an internet business model. As is illustrated in
FIG. 8A A,FIG. 35 andFIG. 39A , a customer 12 sends a set ofcustomer data 17 to a fab 14 through a medium 18, such as internet. In the fab 14, wafers are preferably constantly exposed in a programmable litho-systems. Once a new order is received, thecustomer data 17 are processed by a data-processingunit 15 and converted into a set ofconfiguration data 16. Theconfiguration data 16 are issued to the OPM and then coded into the wafer-under-exposure. Thus, the customer 12 has direct, remote and real-time control. - For data which are frequently needed or whose source code the owners want to hide from the customers (e.g. copyrighted materials such as audio/video materials), they can be stored in a
database 1 ddb at or near the fab 14. To select theinterested files 1 da, 1 dc, the customer 12 sendspointers 1 pa, 1 pc associated with these files (e.g. by clicking a web-page 12 t) and the data-processingunit 15 will fetch these files from thedatabase 1 ddb. Because the fab 12 can have fast access to thedatabase 1 ddb, the upload time is more acceptable. Alternatively, thecustomer data 17 can be compressed. - Using “hard” mask for coding, the prior-art ROM usually only stores “public” information. Shared by many users, “public” information does not need to be encrypted. However, with the advent of litho-programming, litho-programmable ROM (LP-ROM) will more likely store “personal” information. Accordingly, information security will become a concern.
FIG. 39B A illustrates the data flow for a preferred secure LP-ROM. Before sending it to the fab, the customer encrypts thecustomer data 17 at anencryption unit 4 e with a key 7 k. Subsequently, onlyencrypted data 17 ed are sent to the fab. The fab 14 plainly codes these data into a LP-ROM chip 9, without any knowledge of their representation. After receivingchip 9, the customer inputs the key 7 k and enables thechip 9. As a result, the key 7 k never falls out of the customer's hands and excellent information security can be achieved during the chip manufacturing. - Besides high security during manufacturing, it is also desired to maintain a high security during the chip usage. Preferably, a
decryption engine 4 d and akey storage 7 m can be built on the same chip as the LP-ROM chip 9. Three-dimensional read-only memory (3D-ROM) is well suited for this purpose. As illustrated inFIG. 39B B, the 3D-ROM cells 101-103 are located above thesubstrate 00 and they do not occupy silicon real estate. Accordingly, thesubstrate 00 can accommodate a large number oftransistors 5 andNVM 7. They can be used to form thedecryption engine 4 d and thekey storage 7 m (FIG. 39B C). Accordingly, the decryption process can be completely carried out inside the 3D-ROM chip 9. The decrypted data 17 o can be directly forwarded to other functional blocks on the chip, such as D/A converter. During the chip usage, the key is not exposed to the external world and excellent information security can be achieved. - While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. For example, many preferred embodiments use metal lines. In fact, other conductive lines (e.g. poly-silicon lines) can also be used. These low-cost lithography concepts can be readily extended to next-generation lithography (e.g. X-ray, e-beam, ion-beam). The invention, therefore, is not to be limited except in the spirit of the appended claims.
Claims (20)
1. An opening-programmable mask system for forming at least one opening image on an image carrier, comprising:
an opening-defining plane with at least an opening for defining the shape of said opening image on said image carrier; and
a light-modulating plane with at least a light-modulating cell for modulating the light intensity through said opening under the control of a set of configuration data.
2. The opening-programmable mask system according to claim 1 , wherein said opening-defining plane and said light-modulating plane are located on two separate surfaces or two separate substrates.
3. The opening-programmable mask system according to claim 1 , wherein said image carrier is a wafer, or a mask blank, or a master optical disc.
4. The opening-programmable mask system according to claim 1 , wherein said light-modulating cell is a light-modulating cell selected from a group including liquid-crystal light-modulating cell, MEMS light-modulating cell, emissive light-modulating cell and three-dimensional light-modulating cell.
5. The opening-programmable mask system according to claim 4 , wherein said MEMS light-modulating cell further comprises at least one of the following (A)-(C) structures:
(A) an MEMS structure selected from a group including slider, rotor, hinge, roller-shade, digital micro-mirror, and digital light-valve; or
(B) an electrically floating MEMS structure and/or an electrically shorted MEMS structure; or
(C) a capacitive driving structure and/or an elastic driving structure and/or a thermal driving structure.
6. The opening-programmable mask system according to claim 1 , wherein said light-modulating cell comprises a peripheral circuit having at least a transistor.
7. The opening-programmable mask system according to claim 1 , further comprising means for forming at least a first and second plurality of opening images on said image carrier under the control of said configuration data, wherein said first plurality of opening images interleave said second plurality of opening images.
8. The opening-programmable mask system according to claim 1 , further comprising means for changing the relative placement between said opening-defining plane and said light-modulating plane.
9. The opening-programmable mask system according to claim 1 , further comprising means for sensing and inspecting the opening images formed by said light-modulating plane.
10. A logic litho-system, comprising:
a stage for holding and moving an image carrier in a controlled manner;
a first mask region for forming a first image on said image carrier during a first exposure; and
a separate second mask region for forming a second image on said image carrier during a second exposure;
whereby said first and second images interleave.
11. The logic litho-system according to claim 10 , wherein photolithographic alignment is performed only once during said first and second exposures.
12. The logic litho-system according to claim 10 , wherein photoresist development is performed after said first and second exposures.
13. The logic litho-system according to claim 10 , wherein said image carrier is a wafer, or a mask blank, or a master optical disc.
14. The logic litho-system according to claim 10 , further comprising:
a mask comprising said first and second mask regions; and
means for moving said mask in a controlled manner.
15. The logic litho-system according to claim 10 , further comprising:
a first mask comprising said first mask region;
a second mask comprising said second mask region;
a mask-holder for holding said first and second masks; and
means for moving said mask-holder in a controlled manner.
16. The logic litho-system according to claim 10 , further comprising:
a first projector holding a first mask comprising said first mask region and performing said first exposure; and
a second projector holding a second mask comprising said second mask region and performing said second exposure;
wherein photolithographic alignment is performed only once during said first and second exposures, and photoresist development is performed after said first and second exposures.
17. The logic litho-system according to claim 10 , wherein:
said first mask region is a primary mask region having at least a defect site; and
said second mask region is a redundant mask region having a correctional structure for said defect site.
18. A litho-programmable integrated circuit (LP-IC), comprising at least a litho-programmable layer having a plurality of opening-related patterns, wherein said opening-related patterns are defined by a set of customer data and no conventional custom opening-mask set is used to form said opening-related patterns during manufacturing.
19. The LP-IC according to claim 18 , wherein a method for forming said opening-related patterns includes the steps of:
A) sending an order with an order volume for said LP-IC to a vendor;
B) receiving a price quote for said order from said vendor;
wherein, the overall expected revenue for said order, being equal to the product of said order volume and said price quote, is lower than the price of a conventional custom opening-mask set to form said opening-related patterns.
20. The LP-IC according to claim 18 , wherein a method for forming said opening-related patterns includes the step of sending said customer data to said vendor through a medium, said medium including internet, disc, and hard-disk drive.
Priority Applications (1)
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US11/163,864 US20060038746A1 (en) | 2001-10-02 | 2005-11-02 | Low-Cost Lithography |
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US33933401P | 2001-12-13 | 2001-12-13 | |
CNB021133336A CN1310311C (en) | 2002-02-05 | 2002-02-05 | Design of 3D ROM |
CN02113333.6 | 2002-02-05 | ||
CN02113475 | 2002-03-20 | ||
CN02113476 | 2002-03-20 | ||
CN02113476.6 | 2002-03-20 | ||
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CN02113477.4 | 2002-03-20 | ||
CN02113475.8 | 2002-03-20 | ||
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CN02113792.7 | 2002-05-28 | ||
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050038684A1 (en) * | 2003-08-14 | 2005-02-17 | Chung-Wen Wang | System and method of demand and capacity management |
US20090271019A1 (en) * | 2003-08-14 | 2009-10-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method of demand and capacity management |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7640529B2 (en) * | 2002-07-30 | 2009-12-29 | Photronics, Inc. | User-friendly rule-based system and method for automatically generating photomask orders |
US6667531B1 (en) * | 2002-08-29 | 2003-12-23 | Micron Technology, Inc. | Method and apparatus for a deposited fill layer |
US7071097B2 (en) * | 2004-07-09 | 2006-07-04 | International Business Machines Corporation | Method for improved process latitude by elongated via integration |
US7660823B2 (en) * | 2004-12-30 | 2010-02-09 | Sas Institute Inc. | Computer-implemented system and method for visualizing OLAP and multidimensional data in a calendar format |
CN104090466B (en) * | 2005-04-26 | 2019-06-14 | 瑞萨电子株式会社 | Semiconductor device and its manufacturing method, optical proximity processing method |
US20070046917A1 (en) * | 2005-08-31 | 2007-03-01 | Asml Netherlands B.V. | Lithographic apparatus and device manufacturing method that compensates for reticle induced CDU |
US7994564B2 (en) * | 2006-11-20 | 2011-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-volatile memory cells formed in back-end-of line processes |
US20080172517A1 (en) * | 2007-01-11 | 2008-07-17 | Guobiao Zhang | Mask-Programmable Memory with Reserved Space |
KR101769258B1 (en) * | 2007-01-18 | 2017-08-17 | 가부시키가이샤 니콘 | Scanner based optical proximity correction system and method of use |
US7859025B2 (en) * | 2007-12-06 | 2010-12-28 | International Business Machines Corporation | Metal ion transistor |
JP5350681B2 (en) | 2008-06-03 | 2013-11-27 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US9245792B2 (en) * | 2008-07-25 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming interconnect structures |
US8722445B2 (en) | 2010-06-25 | 2014-05-13 | International Business Machines Corporation | Planar cavity MEMS and related structures, methods of manufacture and design structures |
US8635765B2 (en) | 2011-06-15 | 2014-01-28 | International Business Machines Corporation | Method of forming micro-electrical-mechanical structure (MEMS) |
US8609540B2 (en) | 2011-06-20 | 2013-12-17 | Tessera, Inc. | Reliable packaging and interconnect structures |
US8759234B2 (en) | 2011-10-17 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Deposited material and method of formation |
US8883638B2 (en) * | 2012-01-18 | 2014-11-11 | United Microelectronics Corp. | Method for manufacturing damascene structure involving dummy via holes |
US9230854B2 (en) | 2013-04-08 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US20140342553A1 (en) * | 2013-05-14 | 2014-11-20 | United Microelectronics Corp. | Method for Forming Semiconductor Structure Having Opening |
US9431343B1 (en) * | 2015-03-11 | 2016-08-30 | Samsung Electronics Co., Ltd. | Stacked damascene structures for microelectronic devices |
CN106502040B (en) * | 2016-11-18 | 2019-06-04 | 中国电子科技集团公司第四十一研究所 | Lithography mask version for chemical milling process production gold plated copper strip micro-force sensing line |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6664808B2 (en) * | 2001-08-07 | 2003-12-16 | Xilinx, Inc. | Method of using partially defective programmable logic devices |
US7299203B1 (en) * | 2001-04-19 | 2007-11-20 | Xilinx, Inc. | Method for storing and shipping programmable ASSP devices |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4656732A (en) * | 1984-09-26 | 1987-04-14 | Texas Instruments Incorporated | Integrated circuit fabrication process |
US4653860A (en) * | 1985-01-07 | 1987-03-31 | Thomson Components-Mostek Corporation | Programable mask or reticle with opaque portions on electrodes |
US4954789A (en) * | 1989-09-28 | 1990-09-04 | Texas Instruments Incorporated | Spatial light modulator |
JP2616660B2 (en) * | 1993-06-21 | 1997-06-04 | 日本電気株式会社 | Exposure apparatus for thick film wiring pattern and method for forming thick film |
USH1525H (en) * | 1993-04-08 | 1996-04-02 | The United States Of America As Represented By The Secretary Of The Army | Method and system for high speed photolithography |
US5539567A (en) * | 1994-06-16 | 1996-07-23 | Texas Instruments Incorporated | Photolithographic technique and illuminator using real-time addressable phase shift light shift |
JPH085815A (en) * | 1994-06-20 | 1996-01-12 | Toppan Printing Co Ltd | Production of color filter |
US5466639A (en) * | 1994-10-06 | 1995-11-14 | Micron Semiconductor, Inc. | Double mask process for forming trenches and contacts during the formation of a semiconductor memory device |
US5703728A (en) * | 1994-11-02 | 1997-12-30 | Texas Instruments Incorporated | Support post architecture for micromechanical devices |
US6495470B2 (en) * | 1994-11-18 | 2002-12-17 | Intel Corporation | Contact and via fabrication technologies |
JPH0936222A (en) * | 1995-07-19 | 1997-02-07 | Fujitsu Ltd | Semiconductor device and its manufacture |
US6420786B1 (en) * | 1996-02-02 | 2002-07-16 | Micron Technology, Inc. | Conductive spacer in a via |
US5870176A (en) * | 1996-06-19 | 1999-02-09 | Sandia Corporation | Maskless lithography |
US5966632A (en) * | 1997-01-21 | 1999-10-12 | Mosel Vitelic Inc. | Method of forming borderless metal to contact structure |
US6097361A (en) * | 1997-01-29 | 2000-08-01 | Advanced Micro Devices, Inc. | Photolithographic exposure system and method employing a liquid crystal display (LCD) panel as a configurable mask |
JP3032170B2 (en) * | 1997-02-05 | 2000-04-10 | 株式会社東芝 | Charged beam drawing equipment |
US5801094A (en) * | 1997-02-28 | 1998-09-01 | United Microelectronics Corporation | Dual damascene process |
US5912094A (en) * | 1997-05-15 | 1999-06-15 | Lucent Technologies, Inc. | Method and apparatus for making a micro device |
US5874778A (en) * | 1997-06-11 | 1999-02-23 | International Business Machines Corporation | Embedded power and ground plane structure |
US5891799A (en) * | 1997-08-18 | 1999-04-06 | Industrial Technology Research Institute | Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates |
US6246708B1 (en) * | 1997-08-27 | 2001-06-12 | Xerox Corporation | Semiconductor laser with associated electronic components integrally formed therewith |
US5976968A (en) * | 1997-10-14 | 1999-11-02 | Industrial Technology Research Institute | Single-mask dual damascene processes by using phase-shifting mask |
KR100280832B1 (en) * | 1997-12-02 | 2001-04-02 | 정선종 | Programmable mask for lithography |
TW359008B (en) * | 1997-12-20 | 1999-05-21 | United Microelectronics Corp | Double metal embedding |
US6140226A (en) * | 1998-01-16 | 2000-10-31 | International Business Machines Corporation | Dual damascene processing for semiconductor chip interconnects |
US5998069A (en) * | 1998-02-27 | 1999-12-07 | Micron Technology, Inc. | Electrically programmable photolithography mask |
JP3798908B2 (en) * | 1998-05-07 | 2006-07-19 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
JP3087726B2 (en) * | 1998-05-25 | 2000-09-11 | 日本電気株式会社 | Patterning method in manufacturing process of semiconductor device |
US6080661A (en) * | 1998-05-29 | 2000-06-27 | Philips Electronics North America Corp. | Methods for fabricating gate and diffusion contacts in self-aligned contact processes |
US6323118B1 (en) * | 1998-07-13 | 2001-11-27 | Taiwan Semiconductor For Manufacturing Company | Borderless dual damascene contact |
JP2000047367A (en) * | 1998-07-17 | 2000-02-18 | Texas Instr Inc <Ti> | Method and system for improving pattern formation in manufacture of microlithography |
JP3276007B2 (en) * | 1999-07-02 | 2002-04-22 | 日本電気株式会社 | Mixed LSI semiconductor device |
TW451449B (en) * | 2000-08-17 | 2001-08-21 | United Microelectronics Corp | Manufacturing method of dual damascene structure |
-
2002
- 2002-08-28 US US10/230,610 patent/US6989603B2/en not_active Expired - Fee Related
- 2002-09-29 WO PCT/CN2002/000702 patent/WO2003054628A1/en not_active Application Discontinuation
- 2002-09-29 AU AU2002344502A patent/AU2002344502A1/en not_active Abandoned
-
2005
- 2005-11-02 US US11/163,864 patent/US20060038746A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7299203B1 (en) * | 2001-04-19 | 2007-11-20 | Xilinx, Inc. | Method for storing and shipping programmable ASSP devices |
US6664808B2 (en) * | 2001-08-07 | 2003-12-16 | Xilinx, Inc. | Method of using partially defective programmable logic devices |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050038684A1 (en) * | 2003-08-14 | 2005-02-17 | Chung-Wen Wang | System and method of demand and capacity management |
US7483761B2 (en) * | 2003-08-14 | 2009-01-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method of demand and capacity management |
US20090271019A1 (en) * | 2003-08-14 | 2009-10-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method of demand and capacity management |
US9870547B2 (en) | 2003-08-14 | 2018-01-16 | Chung-Wen Wang | System and method of demand and capacity management |
Also Published As
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AU2002344502A1 (en) | 2003-07-09 |
US6989603B2 (en) | 2006-01-24 |
US20030061958A1 (en) | 2003-04-03 |
WO2003054628A1 (en) | 2003-07-03 |
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