Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20060043484 A1
Publication typeApplication
Application numberUS 10/989,639
Publication dateMar 2, 2006
Filing dateNov 17, 2004
Priority dateMay 11, 2000
Also published asUS6987050, US20020022366, US20020031909
Publication number10989639, 989639, US 2006/0043484 A1, US 2006/043484 A1, US 20060043484 A1, US 20060043484A1, US 2006043484 A1, US 2006043484A1, US-A1-20060043484, US-A1-2006043484, US2006/0043484A1, US2006/043484A1, US20060043484 A1, US20060043484A1, US2006043484 A1, US2006043484A1
InventorsCyril Cabral, Kevin Chan, Guy Cohen, Christian Lavoie, Ronnen Roy, Paul Solomon
Original AssigneeInternational Business Machines Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk mosfets and for shallow junctions
US 20060043484 A1
Abstract
A method (and resulting structure) for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide phase, reacting the silicon cap layer to form a second silicide phase, for the semiconductor device, and etching any unreacted silicon. The substrate can be either a silicon-on-insulator (SOI) substrate or a bulk silicon substrate.
Images(7)
Previous page
Next page
Claims(10)
1-13. (canceled)
14. A semiconductor device, comprising:
a silicon substrate;
a raised source-drain structure, including a silicided portion formed with an amorphous silicon, formed on said substrate without selective epitaxy processing,
said raised source-drain structure having a surface which is facet-free and has a crystallographic shape which is arbitrary.
15. The device of claim 14, wherein said substrate comprises a bulk silicon substrate.
16. The device of claim 14, wherein said substrate comprises a silicon-on-insulator (SOI) substrate.
17. The device of claim 14, wherein said silicided portion includes a metal comprising one of Co, Ti and Ni.
18. The device of claim 17, wherein said metal includes cobalt having a film thickness in a range of approximately 7 nm to approximately 8 nm.
19. The device of claim 18, wherein a W cap is formed on said metal for preventing oxidation during a subsequent anneal processing.
20. The device of claim 18, wherein a TiN cap is formed on said metal for preventing oxidation during a subsequent anneal processing.
21. The device of claim 14, wherein said raised source-drain structure is free of crystal orientation constraints.
22. The device of claim 14, wherein said raised source-drain structure is non-aligned with a crystallographic direction of said substrate.
Description
    CROSS-REFERENCE TO RELATED APPLICATIONS
  • [0001]
    The present application is a continuation-in-part of U.S. patent application Ser. No. 09/569,306, to Chan et al., having IBM Docket No. YO999-408, filed on May 11, 2000, incorporated herein by reference.
  • U.S. GOVERNMENT RIGHTS IN THE INVENTION
  • [0002]
    The subject matter of the present Application was at least partially funded under the Grant No. N66001-97-1-8908 from the U.S. Defense Advanced Research Projects Agency (DARPA).
  • BACKGROUND OF THE INVENTION
  • [0003]
    1. Field of the Invention
  • [0004]
    The present invention generally relates to bulk MOSFETS and silicon-on-insulator (SOI) MOSFETs and specifically, a self-aligned silicide (salicide) process for thin film SOI MOSFETs having low resistivity contacts and a self-aligned silicide (salicide) process for shallow junctions.
  • [0005]
    2. Description of the Related Art
  • [0006]
    Conventionally, a reduction of a short channel effect in a silicon-on-insulator (SOI) MOSFET has been addressed by using ultra-thin silicon films (e.g., having a thickness substantially within a range of about 50 nm to about 3 nm). However, using an ultra-thin SOI film can result in high source/drain series resistance. A portion of the high source/drain series resistance can be reduced by using a self-aligned silicide (salicide) contact (e.g., for a discussion of salicides, see Lisa T. Su et al., “Optimization of the series resistance in sub-0.2 μm SOI MOSFET's”, Electron Device Letters, 15(9), p. 363, September 1994).
  • [0007]
    The conventional salicide process has been limited to bulk or thick SOI films (e.g., for purposes of the invention, a “bulk” or “thick” SOI film is thicker than 100 nm). Reduction of a SOI film thickness to an estimated 10 nm precludes the use of conventional salicide. That is, if the amount of silicon consumed by the formation of the silicide alloy becomes a large portion of the initial SOI film thickness, then the contact area will decrease, leading to an increase in the contact resistance. Further, even if a conventional salicide was used with thin films, there is no guarantee of low parasitic resistance because an ultra-thin silicon film may be completely consumed during the silicide formation. Further, the conventional salicide process can form a metal-rich silicide which is characterized by higher resistance, if there is not enough silicon to complete the reaction that forms the low resistivity silicide phase.
  • [0008]
    In the case of a thin SOI film, the percentage of the SOI consumed by the silicide considerably affects the series resistance. It has been demonstrated that when 80% or more of the SOI layer is consumed, the series resistance begins to increase as a result of a reduction in the contact area (e.g., see Su et al., supra).
  • [0009]
    Alternatively, if the silicide layer is made extremely thin (e.g., less than 30 nm) to avoid consuming the thin SOI film, then the silicide layer loses its efficiency in reducing the series resistance. For example, if the silicide is in the thick regime, then a reduction of the silicide thickness would roughly yield a proportional increase in the series resistance. This linear behavior would hold down to about 20 nm (depending on the silicide metal). A thinner silicide film may exhibit nucleation problems and some of the phases may not form. All of this would lead to a very steep increase in the contact resistance.
  • [0010]
    The series parasitic resistance must be minimized in order to facilitate the fabrication of high performance thin film SOI MOSFETs. The conventional salicide process is not applicable to the production of ultra-thin SOI MOSFETs, and therefore a new salicide process is required to overcome the problems of the conventional method.
  • [0011]
    Further, the conventional method and structures are deficient in their silicide/SOI interface roughness.
  • [0012]
    Yet another problem of the conventional structures and methods is associated with shallow junctions used in both bulk and SOI MOSFET structures. That is, shallow junctions provide many benefits when used with the fabrication of submicron MOSFET. For example, they allow for a large punch-through voltage. That is, the lateral spread of the source and drain depletion regions below the surface layer makes a MOSFET more prone to punch-through. Therefore, shallow source and drains effectively suppress subsurface punch-through path.
  • [0013]
    Additionally, shallow junctions provide better short-channel behavior, and in particular less VT roll-off (e.g., see S. Wolf, Silicon Processing for the VLSI Era, Volume 3—The Submicron MOSFET, Lattice Press, 1995).
  • [0014]
    Additionally, such shallow junctions allow for steeper junction (dopant) profiles. For example, low energy implants are used to form shallow junctions. The lateral projection range decreases with the implant energy, and therefore more abrupt junctions can be obtained.
  • [0015]
    To reduce the series resistance to the source and drain, a self-aligned (salicide) process is used in the fabrication of the MOSFET device. The top surface of the source and drain regions are silicided, by converting some of the superficial Si into silicide phases such as CoSi2, or TiSi2. The conventional salicide process typically consist of the following main steps.
  • [0016]
    First, blanket deposition of a metal such as Co, Ti or Ni, is performed. For example, the typical required film thickness for Co is about 8 nm. The Co deposition is followed by a TiN cap deposition of about 20 nm thick, to prevent oxidation during anneals.
  • [0017]
    Then, a first rapid thermal anneal (RTA) is performed to form the CoSi, C49 TiSi2, or NiSi phase. For example, a 525C anneal would react the deposited Co with the underlay Si, converting some of the Si into CoSi.
  • [0018]
    Thereafter, selective etching of the unreacted metal is performed. For example, Co that was deposited over non-Si surfaces, such as the dielectric sidewall spacers of the device, cannot react with the Si during the anneal, and therefore would not convert into CoSi. The unreacted Co is etched selectively, leaving the CoSi regions intact.
  • [0019]
    Finally, a second RTA is performed to form the CoSi2 or C54 TiSi2 low resistive phase. For example, the CoSi is annealed at about 750 C, to form the CoSi2 phase. It is noted that the formation of the CoSi2 phase requires additional consumption of Si from the source and drain regions. The NiSi2 phase has a higher resistivity than NiSi. Thus, a second RTA is not applied in the case of Nickel.
  • [0020]
    The silicide forms a junction with the source or drain silicon. The location of the Silicide/Si junction plays an important role as will be explained below.
  • [0021]
    FIG. 7(a) shows a band diagram of a silicide/n-type Si junction. At the junction, there is a potential barrier referred to as the Schottky barrier. The Schottky barrier is not desirable, since it leads to a rectifying contact. For example, the Schottky barrier height of CoSi2 on n-type silicon is about 0.64 eV. If the silicon doping is made very high (e.g., such as 51019 cm−3), the potential barrier narrows, and electrons can easily tunnel through the thin barrier into the semiconductor (e.g., as shown in FIG. 7(b)). The contact is then referred to as a “tunneling contact”, which performs as an ohmic contact.
  • [0022]
    Referring to the structure 800 in FIG. 8, to make a good ohmic contact to the source 801 and drain 802, it is therefore essential that the silicide/Si junction form at the peak concentration of the dopants in the source 801 and drain 802. It is also imperative that the silicide/Si junction would not be deeper than the source/drain junction depth, or otherwise a leakage path forms. These requirements are summarized in FIG. 8.
  • [0023]
    Combining the shallow junction requirement with the requirements associated with the silicide/Si junction position is not trivial. As explained above, the salicide process converts some of the source and drain silicon into silicide.
  • [0024]
    For example, the silicon film thickness that is consumed in the formation of CoSi2 alloy is 3.64 times thicker than the initial as deposited Co film. A Co film of 8 nm thick would yield a CoSi2 film of about 28 nm, and would consume about 29 nm of silicon. On the other hand, the source and drain junction depth (Xj) is projected to be 20-40 nm for devices with a 100 nm gate length (e.g., see the International Technology Roadmap for Semiconductors, 1999 Edition, Semiconductor Industry Association, Executive Summary).
  • [0025]
    As may be seen by this example, if the junction is made very shallow as required by the semiconductor road map, the silicide film thickness, Xsil, and therefore the silicide/Si junction position, may even exceed the source/drain junction depth. Since the silicide film cannot be made thinner, due to the resistance constraint, the conventional salicide process must be modified to accommodate the shallow junction technology requirement.
  • SUMMARY OF THE INVENTION
  • [0026]
    In view of the foregoing and other problems, drawbacks and disadvantages of the conventional methods and structures, an object of the present invention is to provide a new salicide process applicable to the production of ultra-thin SOI and bulk MOSFETs (e.g., having a SOI thickness substantially within a range of about 3 nm to about 100 nm), and to MOSFETS with shallow source-drain junctions.
  • [0027]
    It is a further object to provide a new salicide process in which less of the thin SOI film is consumed, produces a thicker SOI film in, a source/drain region, and is a self-aligned process.
  • [0028]
    Additionally, a further object of the invention is to stay within the thermal budget allowed for the production of conventional MOSFETs using the conventional salicide process. The thermal budget consists of both the temperature and the time length at which the wafer was held at a given temperature. Typically, to minimize the thermal budget the wafer is annealed by rapid thermal annealing (RTA) to form the silicide alloy. For example, to form the CoSi2 phase from the CoSi phase the wafer is annealed at about 750 C. for 60 seconds.
  • [0029]
    A further object is to form a silicide over a shallow source-drain region in a controlled form, and in which the silicide is contained within the source-drain junction.
  • [0030]
    In a first aspect of the invention, a method for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide phase, reacting the silicon cap layer to form a second silicide phase, for the semiconductor device, and etching any unreacted silicon.
  • [0031]
    With the invention, either SOI substrates or bulk silicon substrates can be advantageously employed.
  • [0032]
    In a second aspect of the invention, a method for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a bulk silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide phase, reacting the silicon cap layer to form a second silicide phase, for the semiconductor device, and etching any unreacted silicon. Thus, the invention is advantageously used with bulk silicon substrates.
  • [0033]
    In a third aspect of the invention, a method for fabricating a silicide for a semiconductor device, includes depositing a buried oxide layer on a substrate, applying a silicon layer to the buried oxide layer, and depositing a metal on portions of the silicon layer, thereby to form the silicide for the semiconductor device. Thus, the invention is advantageously used with silicon-on-insulator (SOI) substrates.
  • [0034]
    In a fourth aspect of the present invention, a silicide processing method for a thin silicon region, includes depositing a metal formed in a silicon film, reacting the metal at a first temperature with the silicon film to form a first alloy, selectively etching the unreacted layer of the metal, depositing a Si film on the first alloy, reacting the Si film at a second temperature to form a second alloy, and selectively etching the unreacted layer of the Si film.
  • [0035]
    In yet another aspect of the invention, the structure formed by the inventive method includes a silicon substrate, and a raised source-drain structure, including a silicided portion formed with an amorphous silicon, formed on said substrate without selective epitaxy processing, said raised source-drain structure having a surface which is facet-free and has a crystallographic shape which is arbitrary. Such a structure is advantageous over conventional structures formed, for example, by selective epitaxy in terms of conformality and coverage of the metal. Further, the structure is free of any rotational considerations with respect to patterning the wafer.
  • [0036]
    In the method of the present invention, preferably a thin-film of cobalt (Co) or a cobalt-siliocn mixture (Co1-xSix) is deposited on a substrate and is reacted with silicon (Si) at a low temperature to form an alloy of Co2Si (e.g., having a metal-rich phase). The Co which is not reacted is removed by selective etching. This step is similar to the etching step in the conventional salicide processing, but in the conventional process, a higher temperature anneal is used so the etching is usually performed at the CoSi formation stage. After the etching step, a non-crystalline film of Si or poly-Si is deposited and subsequently annealed to form the alloy (CoSi2) followed by selective etching of the unreacted silicon.
  • [0037]
    In this manner, a reaction of Co to initially form Co2Si, minimizes the silicon consumption of the thin SOI film. The consumption of the thin SOI film is additionally reduced by the deposition of a silicon or poly-silicon film on the Co2Si.
  • [0038]
    The present invention extends the use of a salicide-like process to thin SOI films, which are expected to be used in future SOI MOSFETs. Such thin-film SOI films will be advantageous in making the devices smaller, reducing the source/drain to substrate overlap capacitance, and eliminating the floating body voltage.
  • [0039]
    Further, the invention provides a superior solution to the alternative method(s) which include a raised source/drain by epitaxy.
  • [0040]
    Further, with the invention, it is further possible to obtain good control in forming a silicide over the source and drain in bulk crystalline silicon structures as well as thin film SOI structures.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0041]
    The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
  • [0042]
    FIGS. 1-6 illustrate a self-aligned method for forming low resistivity contacts to thin film SOI MOSFETs, and more specifically:
  • [0043]
    FIG. 1 shows a conventional MOSFET device to be silicided;
  • [0044]
    FIG. 2 shows a thin film of metal (e.g., Co) deposited on the device of FIG. 1;
  • [0045]
    FIG. 3 shows the formation of an alloy including the cobalt after exposure to a low-temperature processing;
  • [0046]
    FIG. 4 shows an amorphous Si film deposition on the alloy;
  • [0047]
    FIG. 5 shows the device after an annealing step at high temperature; and
  • [0048]
    FIG. 6 shows the device after unreacted silicon has been removed by selective etching;
  • [0049]
    FIG. 7(a) illustrates a band diagram of a silicide/n-type Si junction that forms a Schottky barrier;
  • [0050]
    FIG. 7(b) illustrates a band diagram of a silicide/n++-type Si junction that forms an ohmic contact by tunneling;
  • [0051]
    FIG. 8 illustrates requirements for obtaining a structure 800 in which good ohmic contact is made to the source 801 and drain 802 and that the silicon/Si junction is not deeper than the source/drain junction depth; and
  • [0052]
    FIGS. 9A and 9B illustrate the novelty fo the inventive structure.
  • DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION
  • [0053]
    Referring now to the drawings, and more particularly to FIGS. 1-9B, there is shown a preferred embodiment of the method of making of a self-aligned silicide which is applicable to the standard MOSFET structure, and also to non-conventional MOSFETs and structures according to the present invention. Such structures include low resistivity contacts and/or shallow junctions.
  • [0054]
    Referring now to FIG. 1, a conventional MOSFET structure 100 is shown having a substrate 1 formed of silicon, a buried oxide layer 2 (e.g., silicon oxide layer), an SOI layer 3 which thickness noted by tsi, a gate dielectric 6A (e.g., SiO2), sidewall spacers 6B formed of nitride or oxide, a gate 7 (e.g. doped poly-Si, or metal), and a source 4 and a drain 5 made into the SOI film 3, typically by an implant.
  • [0055]
    The inventive method is directed to making a self-aligned silicide which is applicable to the standard MOSFET structure, and also to non-conventional MOSFETs and structures. For ease of discussion, the present invention will be applied to the conventional MOSFET of FIG. 1.
  • [0056]
    However, although the process flow is demonstrated using a conventional MOSFET structure, it is applicable to a wide variety of structures. Metals, other than Co, that are used for silicides (e.g., Ti, Ni, Pd, Pt and alloys thereof) can be used with the present invention.
  • [0057]
    Referring to FIG. 2, a metal 20 (e.g., Co, Ni, Ti, Pd, Pt or alloys thereof) is deposited in a thickness within a range of about 7-8 nm. A TiN cap or a W cap (not shown in the Figure) is deposited over the metal 20 to prevent oxidation during the anneal. The metal 20 is reacted with silicon in the source 4, drain 5, and gate 7 regions at a low temperature T1. It is noted that if the temperature is too low, no reaction will take place. On the other hand, if the temperature is too high, then the monosilicide phase of CoSi will be formed. Since the temperature window over which the metal-rich phase Co2Si is formed is narrow, it is difficult to achieve only this phase during the first anneal. To extend the temperature window, a mixture of 80% Co and 20% Si may be deposited (e.g., by co-sputtering or evaporation from a Si0.2Co0.8 target). The temperature window for the formation of the Co2Si out of the Si0.2Co0.8 mixture is about 337 C. to about 487 C. The use of a 80% Si and 20% Co to extend the temperature window is described in U.S. patent application Ser. No. 09/515,033, Cyril Cabral et. al, “METHOD FOR SELF-ALIGNED FORMATION OF SILICIDE CONTACTS USING METAL SILICON ALLOYS FOR LIMITED SILICON CONSUMPTION AND FOR REDUCTION OF BRIDGING”, filed on Mar. 6, 2000, having IBM Docket No. YOR900-0044, incorporated herein by reference.
  • [0058]
    As shown in FIG. 3, the alloy Co2Si 30 is formed, as a result of applying the low temperature (e.g., T1) in the anneal process to the structure of FIG. 2. (The thickness depends on the initial Co film thickness. One angstrom of Co yields 1.47 angstroms of Co2Si. The typical Co film thickness is about 7 nm. Using the conversion ratio stated above, a 10.3 nm thick film of Co2Si will be obtained after the first anneal.) An upper layer of the cobalt 20 (e.g., over the alloy Co2Si 30) is unreacted Co 20.
  • [0059]
    That is, in the standard process, all of the Co which is deposited over a Si surface will react with the silicon surface and will form a silicide. On the other hand, the Co that was deposited over dielectric surfaces such as the oxide or nitride sidewalls cannot react with the Si surface and will remain as unreacted Co.
  • [0060]
    FIG. 3 demonstrates a case in which some Co is left unreacted on top of the silicide. As described above, this is not desirable in a manufacturing process. Yet, even if this does happen, the overall process of the invention will not be affected except that the silicide film will be thinner than targeted. As such, the robustness of the process is clearly demonstrated. It is noted that in most cases, there will be no unreacted Co.
  • [0061]
    For example, the unreacted cobalt 20 has a thickness dependent on the anneal time/temperature, and is removed through selective etching. That is, a too short anneal may leave some of the Co unreacted. If the temperature is too low, then the Co will not react with the SOI film. This step is similar to the etching step in the conventional salicide process with the exception that in the conventional salicide process the un-reacted Co is etched at the stage where CoSi is formed. It is noted that the deposition of the a-Si may be carried out over the CoSi phase. However, by forming the CoSi phase, much more of the Si in the SOI layer will be consumed. An example of a selective etching solution is 10:1H2O2:H2SO4 at 65 C.
  • [0062]
    Next, referring to FIG. 4, an amorphous Si (a-Si) or a poly-Si film 40 is deposited over the alloy Co2Si 30. The a-Si film thickness depend on the initial Co film thickness. One unit of Co would require 0.91 units of Si to form Co2Si, 1.82 units of Si to form CoSi and 3.64 units of Si to form CoSi2. For example, suppose the process starts with a 7 nm Co film which are then reacted with the SOI film to form 10.3 nm film of Co2Si. Assuming that all the Co will diffuse into the top deposited a-Si, then it requires the a-Si film to be about 19 nm thick. A more realistic assumption is that more than half but not all the Co will diffuse into the top film, so that a thinner film is actually needed. The amorphous silicon or polysilicon film 40 is annealed at a high temperature T2, (e.g., T2>T1). The temperature window for the formation of CoSi is about 481 C. to about 625 C. (at about 625 C., CoSi2 will start to form). Typical annealing temperature (T2) for the second anneal is about 750 C. These temperatures may vary slightly depending on the doping species and concentration that were implanted into the SOI film.
  • [0063]
    Hereinbelow, the amount of required Si in angstroms per angstroms of metal is described. Forming 1 angstrom of Co2Si will take 0.91 angstrom of Si, CoSi will take 1.82 angstroms of Si, and CoSi2 will take 3.64 angstrom of Si. If the a-Si layer is deposited on top of the Co2Si film, then the Si consumption may be reduced by at least a half, since the Co2Si film would be reacting on both top and bottom interfaces. It is important to clean the top surface of the Co2Si and remove any native oxide before the a-Si film deposition. The existence of such an oxide at the interface may prevent the Co2Si to react with the deposited a-Si layer. The cleaning of the surface and the stripping of a native oxide may be achieved by Ar (argon) sputtering in the a-Si deposition chamber or by a short dip in a diluted HF acid.
  • [0064]
    As shown in FIG. 5, as a result of the annealing operation at a high temperature T2, a layer of CoSi2 50 is formed under an unreacted layer/portion 40A of the amorphous silicon or polysilicon film 40. The thickness of the layer of un-reacted amorphous silicon/polysilicon layer 40A depends on the initial thickness of the top a-Si layer 40. It is desirable that all of the Co2Si is transformed into CoSi2, without consuming the entire a-Si layer. The unreacted layer/portion 40A results from the supply of Si from the a-Si exceeding that which is needed to form CoSi2. In other words, the a-Si layer was too thick.
  • [0065]
    FIG. 6 illustrates the selective etching of the layer of un-reacted a-Si or poly-Si film 40 in a last phase.
  • [0066]
    Thus, with the invention, the reacting of the metal (e.g., cobalt) in an annealing operation to initially form the alloy Co2Si 30 minimizes the silicon consumption of the SOI film 3.
  • [0067]
    Additionally, the deposit of the amorphous silicon or the polysilicon film 40 on top of the alloy Co2Si 30 further reduces consumption of the SOI film 3 by a factor of two since at least half of the Co contained he Co2Si 30 will diffuse into the top amorphous silicon/polysilicon film layer 40 at the high temperature anneal which forms the CoSi2.
  • [0068]
    The diffusivity of cobalt in polysilicon may be larger than in single crystal (mono-crystal) silicon. Due to this diffusivity difference between polysilicon and single crystal silicon, the high temperature anneal will consume more of the top polysilicon layer than that of the bottom single crystal SOI film.
  • [0069]
    In an alternative embodiment, the invention can be modified so that the first anneal is at an intermediate temperature, T3 (e.g., T3 is about 550 C.), where CoSi is formed (T1<T3<T2). The anneal process at this temperature will consume more of the SOI film than a Co2Si formation. However, it may provide a larger temperature window for the anneal.
  • [0070]
    The larger the temperature window, the easier it is to form a given silicide phase without the risk of obtaining a mix phase. The temperature window for Co2Si is about 20 C. wide if pure Co is used. It may be widened to about 100 C. by using Co0.8Si0.2. The window may shift and vary depending on the SOI doping. This makes it difficult to obtain the Co2Si phase if the window is narrow. If pure Co rather than Co0.8Si0.2 is used, then it is easier to form CoSi due to its large temperature window of about 150 C.
  • [0071]
    Also, the etch selectivity of CoSi, with respect to Co, is higher than that of Co2Si with respect to Co. The advantages of this selectivity include better reliability and precision of the resulting product. After the Co is reacted to form CoSi, the unreacted Co must be etched away. Otherwise, the source/drain regions will be shortened to the gate. The etchant should be selective to CoSi. That is, it should only remove the Co and leave the CoSi alloy intact. The etching selectivity is typically higher if the alloy contains less Co and more Si. Thus, CoSi is expected to be more resistant to the etch of Co than Co2Si. The remainder of the steps in the process are the same.
  • Second Embodiment
  • [0072]
    The second embodiment of the present invention employs substantially the same process as described above. However, while the process described above has been applied to Silicon-On-Insulator (SOI) MOSFETs, the process is also equally applicable to bulk MOSFETs, as discussed below.
  • [0073]
    Thus, the second embodiment uses substantially the same process. For the reader's greater clarity, the process steps are summarized below.
  • [0074]
    First, a blanket deposition of a metal such as Co, Ti or Ni, is performed. For example, the typical required film thickness for Co is about 7-8 nm. The Co deposition is followed by a TiN cap deposition of about 20 nm thick, that prevent oxidation during anneals.
  • [0075]
    Then, a first rapid thermal anneal (RTA) is performed to form the CoSi, C49 TiSi2, or NiSi phase. For example, a 525C anneal would react the deposited Co with the underlay Si, converting some of the Si into CoSi.
  • [0076]
    Then, the unreacted metal is selectively etched. For example, Co that was deposited over non-Si surfaces, such as the dielectric sidewall spacers of the device, cannot react with the Si during the anneal and therefore would not convert into CoSi. The unreacted Co is etched selectively, leaving the CoSi regions intact.
  • [0077]
    Then, a blanket deposition of a silicon film is performed. For example, the silicon may be sputtered or evaporated. Following the example outlined above, the typical required Si film thickness would be 15 nm or thicker to ensure that the top Si film would have sufficient silicon to form the di-silicide, CoSi2. The top mono-silicide surface should be cleaned, so that the deposited silicon would be free to react with the underlay mono-silicide.
  • [0078]
    Thereafter, a second RTA is performed to form the CoSi2 or C54 TiSi2 low resistive phase. For example, the CoSi is annealed at about 750 C, to form the CoSi2 phase. It is noted that the silicon consumption from the substrate is reduced due the supply of Si from the deposited Si cap layer. As mentioned earlier in the case of Nickel, the NiSi is lower resistivity phase, and thus a second RTA is not used.
  • [0079]
    Further, the unreacted silicon is selectively etched. For example, tetramethylammonium hydroxide (TMAH) may be used to etch the silicon and stop on the CoSi2 film.
  • [0080]
    The silicon consumption may be further reduced if a mixture of Co and Si is deposited in the first step above. The process of using Co alloys was first disclosed in the above copending application Ser. No. 09/515,033. Thus, instead of a pure Co deposition (step 1), Co is co-deposited with Si. The use of such a mixture of Co1-xSix, is limited to about x<0.3, or otherwise bridging from source/drain to gate would occur. The reduction in the Si consumption from the wafer is achieved due to the following reasons:
  • [0081]
    First, the temperature window in which the metal rich phase, Co2Si, is formed is broadened to about 100 C. This makes it possible to replace the first anneal (step 2) that forms the mono-silicide phase, CoSi, with an anneal that would form the metal rich phase, Co2Si. The formation of the metal rich phase would consume only half of the Si that would have been consume by the mono-silicide phase. Now, the cap silicon layer may be deposited over the metal rich phase (after the etching of the unreacted Co—step 3). Thus, the silicide formation is carried out with a second source of silicon on top of the silicide film almost from the very beginning. This reduces the consumption of Si from the substrate.
  • [0082]
    Secondly, some of the silicon which is required to form the silicide phase is already contained in the deposited mixture, and thus the substrate consumption is reduced.
  • [0083]
    Additionally, there are other alternative approaches to the invention discussed above including raised source/drain by selective epitaxial growth of Si, and deposition of CoSi mixture.
  • [0084]
    That is, alternative conventional methodologies (e.g., which are less desirable when contrasted to the embodiments of the invention described above), include thickening a SOI layer (by at least the amount that will be consumed by the silicide in source and drain regions by using selective epitaxial growth of silicon on these regions, fabricating different silicide thicknesses over the gate, source and drain regions by laser melting, and the deposit of a silicon alloy (Co1-xSix, where x<0.2) to limit the amount of silicon consumed at source, drain, and gates during silicide formation.
  • [0000]
    Raised Source/Drain by Epitaxial Growth of Si:
  • [0085]
    Silicon can be added to the source and drain region selectively by selective epitaxy prior to the metal deposition. That is, the epitaxial growth of Si is performed by thickening a SOI layer in the source/drain regions through selective epitaxial growth of Si in these regions. This alternative has several disadvantages when compared to the process of the present invention.
  • [0086]
    First, the epitaxial growth must be selective, otherwise Si growth will occur on the sidewalls of the device. This condition can lead to shorting the gate to the source and the drain. To avoid this problem, the choice of the sidewall material to use is narrowed because only growth-resistant materials can be selected.
  • [0087]
    Further, the growth temperature is an important parameter in determining the selectivity of the growth. The Si epitaxial growth loses selectivity at low growth temperatures. “Low growth temperatures” depend on the growth technique, and the silicon source. The most selective source is SiCl4, but it also requires the highest deposition temperature (about 900 C. to 1200 C.). Silane (SiH4) can be used for low temperature deposition (as low as about 650 C.), but it exhibits very little selectivity, if any. Therefore, a sufficiently high growth temperature (e.g., about 900 C.) is required to guarantee selectivity. The required high growth temperature may be in excess of the thermal budget incurred in the conventional salicide process.
  • [0088]
    A further problem with producing a raised source/drain by epitaxial growth of silicon is the process robustness. Silicon epitaxy is very sensitive to surface preparation and cleaning. Different surface treatments can lead to different defects in the film. Oxide residuals (e.g., even an atomic monolayer) can prevent epitaxial growth.
  • [0089]
    Another problem with the epitaxial growth approach, known as “growth rate dependency on feature size”, can occur. In a chemical vapor deposition (CVD)-type epitaxy, the growth rate may be dependent on the topography, the dimensions of the growth area, and the ratio between the growth to non-growth areas. This may lead to a growth of different film thicknesses in devices that are embedded in different circuit layouts. This condition is an additional dimension that must be included in a manufacturing process, and hence requires additional costs. The present invention does not require epitaxy, and is therefore not limited by the difficulties imposed by epitaxy.
  • [0000]
    Deposition of Co1-xSix Alloy
  • [0090]
    Another alternative to the present invention may be the deposition of CoSi mixture. However, this method is problematic as well.
  • [0091]
    That is, the deposition of a Co film that contains silicon reduces the silicon consumption from the wafer as some of the Si needed for the silicide formation is already contained in the Co film. However, this technique is limited to a Co1-xSix mixture that has a small enough concentration of Si (x<<1) so that the deposited alloy on the oxide side-walls can be removed by selective etching. It can therefore reduce the consumption of Si from the substrate by only 10 to 15%.
  • [0092]
    The present invention can use this method to further decrease the Si consumption by depositing Co1-xSix instead of pure Co. A second advantage of Co1-xSix is the larger temperature window which is available for the formation of the metal-rich phase.
  • [0093]
    Thus, the present invention can provide an optimum structure for meeting the shallow junction requirement with the requirements associated with the silicide/Si junction position.
  • [0094]
    The invention uses conventional fabrication techniques, and does not have a throughput problem. That is, a conventional approach to siliciding uses laser melting, which is a relatively new technique that allows the fabrication of different silicide thicknesses over the gate and over the source/drain region. This technique has not been applied in a manufacturing context and therefore its usage in practice is unknown. However, the throughput of the technique may be lower than that achieved with the other techniques such as raised source/drain, deposition of CoSi alloy, etc. In laser melting, laser annealing is carried out per wafer (i.e., the wafers are processed sequentially) one at a time. Raised source/drain epitaxy and the present invention are parallel techniques in the sense that the entire wafer lot may be processed together (e.g., a single deposition is carried out on all wafers).
  • [0095]
    Additionally, it is noted that the thermal budget required by the invention is the same as in a conventional salicide process.
  • [0096]
    Thus, the present invention overcomes the above-mentioned and other problems of the conventional techniques and allows forming silicon-on-insulator (SOI) and bulk MOSFETs having ultra-thin silicon films and while preventing (or at least minimizing) the high source/drain series resistance and maintaining its efficiency. Thus, bulk or thick SOI films are unnecessary with the inventive method. Further, series parasitic resistance is minimized in order to facilitate the fabrication of high performance thin film SOI MOSFETs with the inventive method.
  • [0097]
    Further, with, for example, the second embodiment of the invention, it is further possible to obtain good control of the silicide over shallow source and drain junctions in bulk crystalline silicon structures.
  • [0098]
    It is noted that, with both embodiments, looking at the structure from the top down, the device (structure) appears the same. It is not until one examines the substrate, that a difference is found (e.g., a bulk or a buried oxide substrate). Further, since the invention is essentially a superficial process, it does not matter what is buried with regard to the method of the invention, and the process is equally applicable to both bulk and SOI substrates. The invention works equally well regardless of what is buried below the initial (first) layer of silicon where the silicide reaction is formed.
  • [0099]
    Turning to FIGS. 9A and 9B, it can be clearly seen that the inventive structure is clearly differentiated from a raised source-drain structure formed by selective epitaxy.
  • [0100]
    That is, for purposes of the present invention, “epitaxy” is defined as “the growth on a crystalline substrate of a crystalline substance that mimics the orientation of the substrate”. Keeping this definition in mind, it can be understood that a crystal grown by epitaxy would always be aligned to the underlay substrate, regardless of the orientation of a window that defines a growth region.
  • [0101]
    FIGS. 9A and 9B respectively illustrate selective epitaxial growth for two different rectangular windows 901A, 901B exposing a substrate region 910. The windows 901A, 901B are openings in a mask on which no nucleation occurs. The windows 901A, 901B are shown by a dashed line. To further simplify the discussion, only the (100) and (110) sets of planes are considered when looking at the crystal growth.
  • [0102]
    In FIG. 9A, the left window 901A defines a rectangle which is perfectly aligned along the 110 and 011 crystal orientation, whereas in FIG. 9B the right window 901B is aligned with the 010 and 100 orientations. The substrate surface in both windows is aligned with the 001 orientation. It is well known that the growth rate is strongly dependent on the crystal orientation. For the following discussion, it is assumed that the (110) plane set is slow-growing compared to the fast-growing (100) planes. This is illustrated by the coordinate system shown on the top of FIGS. 9A and 9B.
  • [0103]
    Since the growth rate is dependent on the crystal orientation, the grown crystal would exhibit facets. These faces develop into the slow-growing planes. FIG. 9B shows the grown crystal at two different growth times. At tgrowth=t1, the grown crystal shape is still close to the original window that defines the growth area. However, as the growth proceeds (tgrowth=t2), the slow growing (110) planes become dominant, and the grown crystal no longer follows the shape of the underlay window. As growth would proceed, the shape of the crystal would converge into a pyramid having a base which is oriented along the 110 and 011 orientations (as that of the left window 901B). As illustrated by FIG. 9A, the grown crystal would maintain the window shape only if the window is aligned to the slow-growing planes.
  • [0104]
    Therefore, a raised source-drain structure by epitaxy is limited to constraints imposed by the crystal orientation. The shape and the orientation of the window that defines the growth area would not necessarily be replicated to the grown crystal, since it always follows the orientations defined by the underlay crystal substrate.
  • [0105]
    However, the salicide method of the present invention does not rely on epitaxial growth, and is therefore free of crystal orientation constraints. Thus, in the invention, it does not matter what the crystallographic directions are because the invention does not rely on such directions to form the inventive structure.
  • [0106]
    Moreover, the raised source-drain formed by the inventive process does not exhibit facets and is defined by the source and drain windows. Hence, the shape that is obtained is facet-free.
  • [0107]
    While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.
  • [0108]
    The method and structure of the present invention are not limited to a specific silicide-forming metal. Further, the invention, is not limited to one particular device as described above, but can also be used in devices with a non-planar source/drain region, such as a polysilicon side-wall source drain (e.g., see P. M. Solomon, H.-S. P. Wong, “Method for Making Single and Double Gate Field Effect Transistors with Sidewall Source Drain Contacts”, U.S. Pat. No. 5,773,331, Jun. 30, 1998, incorporated herein by reference; and T. Yoshimoto et al., “Silicided Silicon-Sidewall Source and Drain Structure for High Performance 75-nm gate length pMOSFETs,” 1995 Symposium on VLSI Technology, digest p. 11).
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4443930 *Nov 30, 1982Apr 24, 1984Ncr CorporationManufacturing method of silicide gates and interconnects for integrated circuits
US4912542 *Feb 17, 1988Mar 27, 1990Kabushiki Kaisha ToshibaSemiconductor device and method of manufacturing the same
US5510295 *Oct 29, 1993Apr 23, 1996International Business Machines CorporationMethod for lowering the phase transformation temperature of a metal silicide
US5608266 *Jun 2, 1995Mar 4, 1997International Business Machines CorporationThin film for a multilayer semiconductor device for improving thermal stability and a method thereof
US5624869 *Apr 13, 1994Apr 29, 1997International Business Machines CorporationMethod of forming a film for a multilayer Semiconductor device for improving thermal stability of cobalt silicide using platinum or nitrogen
US5739890 *Feb 6, 1996Apr 14, 1998International Business Machines CorporationLiquid crystal display device and a method of fabricating same
US5773331 *Dec 17, 1996Jun 30, 1998International Business Machines CorporationMethod for making single and double gate field effect transistors with sidewall source-drain contacts
US5828131 *Jan 16, 1996Oct 27, 1998International Business Machines CorporationLow temperature formation of low resistivity titanium silicide
US5830775 *Nov 26, 1996Nov 3, 1998Sharp Microelectronics Technology, Inc.Raised silicided source/drain electrode formation with reduced substrate silicon consumption
US5864161 *Sep 11, 1995Jan 26, 1999Kabushiki Kaisha ToshibaSemiconductor device and manufacturing method thereof
US5962893 *Jan 16, 1996Oct 5, 1999Kabushiki Kaisha ToshibaSchottky tunneling device
US5994191 *Jul 9, 1998Nov 30, 1999Advanced Micro Devices, Inc.Elevated source/drain salicide CMOS technology
US5998807 *Sep 9, 1997Dec 7, 1999Siemens AktiengesellschaftIntegrated CMOS circuit arrangement and method for the manufacture thereof
US6015752 *Jun 30, 1998Jan 18, 2000Advanced Micro Devices, Inc.Elevated salicide technology
US6016181 *Oct 21, 1997Jan 18, 2000Sharp Kabushiki KaishaLiquid crystal device having column spacers with portion on each of the spacers for reflecting or absorbing visible light and method for fabricating the same
US6054386 *Aug 20, 1997Apr 25, 2000Prabhakar; VenkatramanProcess for forming silicon-on-insulator devices using a nitriding agent
US6072222 *May 18, 1998Jun 6, 2000Advanced Micro Devices, Inc.Silicon implantation into selective areas of a refractory metal to reduce consumption of silicon-based junctions during salicide formation
US6087208 *Mar 31, 1998Jul 11, 2000Advanced Micro Devices, Inc.Method for increasing gate capacitance by using both high and low dielectric gate material
US6100145 *Nov 5, 1998Aug 8, 2000Advanced Micro Devices, Inc.Silicidation with silicon buffer layer and silicon spacers
US6165903 *Nov 4, 1998Dec 26, 2000Advanced Micro Devices, Inc.Method of forming ultra-shallow junctions in a semiconductor wafer with deposited silicon layer to reduce silicon consumption during salicidation
US6169005 *May 26, 1999Jan 2, 2001Advanced Micro Devices, Inc.Formation of junctions by diffusion from a doped amorphous silicon film during silicidation
US6181406 *Sep 2, 1998Jan 30, 2001Kabushiki Kaisa ToshibaActive matrix liquid crystal display device
US6214679 *Dec 30, 1999Apr 10, 2001Intel CorporationCobalt salicidation method on a silicon germanium film
US6239492 *May 8, 1996May 29, 2001Micron Technology, Inc.Semiconductor structure with a titanium aluminum nitride layer and method for fabricating same
US6266121 *Nov 24, 1997Jul 24, 2001Sharp Kabushiki KaishaLiquid crystal display element and method of manufacturing same
US6297148 *Jan 5, 2000Oct 2, 2001Advanced Micro Devices, Inc.Method of forming a silicon bottom anti-reflective coating with reduced junction leakage during salicidation
US6323130 *Mar 6, 2000Nov 27, 2001International Business Machines CorporationMethod for self-aligned formation of silicide contacts using metal silicon alloys for limited silicon consumption and for reduction of bridging
US6413386 *Jul 19, 2000Jul 2, 2002International Business Machines CorporationReactive sputtering method for forming metal-silicon layer
US6433388 *Jun 29, 1999Aug 13, 2002Oki Electric Industry Co., LtdSemiconductor device with self-aligned areas formed using a supplemental silicon overlayer
US6444578 *Feb 21, 2001Sep 3, 2002International Business Machines CorporationSelf-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices
US6503833 *Nov 15, 2000Jan 7, 2003International Business Machines CorporationSelf-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby
US6555839 *May 16, 2001Apr 29, 2003Amberwave Systems CorporationBuried channel strained silicon FET using a supply layer created through ion implantation
US6555880 *Jun 7, 2001Apr 29, 2003International Business Machines CorporationSelf-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby
US6570639 *Sep 1, 2000May 27, 2003Kabushiki Kaisha ToshibaLiquid crystal display device including shield pattern and color filter coexist together in the vicinity of the inlet
US6674590 *Apr 30, 2001Jan 6, 2004Hitachi Global TechnologiesSystem and method for estimating a frequency of slider airbearing resonance
US6747289 *Apr 24, 2001Jun 8, 2004Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method of fabricating thereof
US6812977 *Nov 21, 2000Nov 2, 2004Minolta Co., Ltd.Liquid crystal element
US6900084 *May 9, 2000May 31, 2005Semiconductor Energy Laboratory Co., Ltd.Semiconductor device having a display device
US20010041392 *May 11, 2001Nov 15, 2001Hideomi SuzawaSemiconductor device and manufacturing method thereof
US20030180996 *Jan 7, 2003Sep 25, 2003Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and manufacturing method thereof
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7569888 *Aug 10, 2005Aug 4, 2009Toshiba America Electronic Components, Inc.Semiconductor device with close stress liner film and method of manufacturing the same
US7790527 *Feb 3, 2006Sep 7, 2010International Business Machines CorporationHigh-voltage silicon-on-insulator transistors and methods of manufacturing the same
US7923781 *Mar 27, 2008Apr 12, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for manufacturing the same
US7924630Oct 15, 2008Apr 12, 2011Micron Technology, Inc.Techniques for simultaneously driving a plurality of source lines
US7933140Oct 2, 2008Apr 26, 2011Micron Technology, Inc.Techniques for reducing a voltage swing
US7933142Apr 30, 2007Apr 26, 2011Micron Technology, Inc.Semiconductor memory cell and array using punch-through to program and read same
US7940559Feb 13, 2009May 10, 2011Micron Technology, Inc.Memory array having a programmable word length, and method of operating same
US7947543Sep 25, 2009May 24, 2011Micron Technology, Inc.Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US7957206Apr 4, 2008Jun 7, 2011Micron Technology, Inc.Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
US7969779May 18, 2009Jun 28, 2011Micron Technology, Inc.Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
US7981766Aug 12, 2008Jul 19, 2011Semiconductor Energy Laboratory Co., Ltd.Manufacturing method and manufacturing apparatus of semiconductor
US8014195Feb 6, 2009Sep 6, 2011Micron Technology, Inc.Single transistor memory cell
US8064274May 27, 2008Nov 22, 2011Micron Technology, Inc.Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US8069377Jun 22, 2007Nov 29, 2011Micron Technology, Inc.Integrated circuit having memory array including ECC and column redundancy and method of operating the same
US8085594May 30, 2008Dec 27, 2011Micron Technology, Inc.Reading technique for memory cell with electrically floating body transistor
US8134867May 9, 2011Mar 13, 2012Micron Technology, Inc.Memory array having a programmable word length, and method of operating same
US8139418Mar 16, 2010Mar 20, 2012Micron Technology, Inc.Techniques for controlling a direct injection semiconductor memory device
US8174881Nov 24, 2009May 8, 2012Micron Technology, Inc.Techniques for reducing disturbance in a semiconductor device
US8189376Feb 2, 2009May 29, 2012Micron Technology, Inc.Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same
US8194487Sep 17, 2008Jun 5, 2012Micron Technology, Inc.Refreshing data of memory cells with electrically floating body transistors
US8199595Sep 7, 2010Jun 12, 2012Micron Technology, Inc.Techniques for sensing a semiconductor memory device
US8213226Dec 7, 2009Jul 3, 2012Micron Technology, Inc.Vertical transistor memory cell and array
US8223574Oct 15, 2009Jul 17, 2012Micron Technology, Inc.Techniques for block refreshing a semiconductor memory device
US8264041 *Jan 24, 2008Sep 11, 2012Micron Technology, Inc.Semiconductor device with electrically floating body
US8268701Nov 4, 2010Sep 18, 2012Semiconductor Energy Laboratory Co., Ltd.Manufacturing of semiconductor device
US8274849May 20, 2011Sep 25, 2012Micron Technology, Inc.Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
US8295078Apr 22, 2011Oct 23, 2012Micron Technology, Inc.Semiconductor memory cell and array using punch-through to program and read same
US8310893Dec 16, 2009Nov 13, 2012Micron Technology, Inc.Techniques for reducing impact of array disturbs in a semiconductor memory device
US8315083Apr 22, 2011Nov 20, 2012Micron Technology Inc.Techniques for reducing a voltage swing
US8315099Jul 27, 2010Nov 20, 2012Micron Technology, Inc.Techniques for providing a direct injection semiconductor memory device
US8319294Jan 28, 2010Nov 27, 2012Micron Technology, Inc.Techniques for providing a source line plane
US8325515Sep 2, 2011Dec 4, 2012Micron Technology, Inc.Integrated circuit device
US8349662Dec 11, 2008Jan 8, 2013Micron Technology, Inc.Integrated circuit having memory cell array, and method of manufacturing same
US8351266Mar 20, 2012Jan 8, 2013Micron Technology, Inc.Techniques for controlling a direct injection semiconductor memory device
US8369177Mar 5, 2010Feb 5, 2013Micron Technology, Inc.Techniques for reading from and/or writing to a semiconductor memory device
US8395937Jun 22, 2011Mar 12, 2013Micron Technology, Inc.Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
US8400811Apr 27, 2010Mar 19, 2013Micron Technology, Inc.Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines
US8402326Nov 29, 2011Mar 19, 2013Micron Technology, Inc.Integrated circuit having memory array including ECC and column redundancy and method of operating same
US8411513Dec 21, 2010Apr 2, 2013Micron Technology, Inc.Techniques for providing a semiconductor memory device having hierarchical bit lines
US8411524Jan 5, 2011Apr 2, 2013Micron Technology, Inc.Techniques for refreshing a semiconductor memory device
US8416636Dec 29, 2010Apr 9, 2013Micron Technology, Inc.Techniques for controlling a semiconductor memory device
US8445359Jun 16, 2011May 21, 2013Semiconductor Energy Laboratory Co., Ltd.Manufacturing method and manufacturing apparatus of semiconductor device
US8446794May 23, 2012May 21, 2013Micron Technology, Inc.Refreshing data of memory cells with electrically floating body transistors
US8492209Jul 12, 2012Jul 23, 2013Micron Technology, Inc.Semiconductor device with electrically floating body
US8498157May 24, 2010Jul 30, 2013Micron Technology, Inc.Techniques for providing a direct injection semiconductor memory device
US8508970Apr 27, 2010Aug 13, 2013Micron Technology, Inc.Techniques for providing a direct injection semiconductor memory device
US8508994Apr 29, 2010Aug 13, 2013Micron Technology, Inc.Semiconductor device with floating gate and electrically floating body
US8518774Mar 21, 2008Aug 27, 2013Micron Technology, Inc.Manufacturing process for zero-capacitor random access memory circuits
US8531878May 17, 2011Sep 10, 2013Micron Technology, Inc.Techniques for providing a semiconductor memory device
US8536628Nov 11, 2008Sep 17, 2013Micron Technology, Inc.Integrated circuit having memory cell array including barriers, and method of manufacturing same
US8537610Jul 12, 2010Sep 17, 2013Micron Technology, Inc.Techniques for providing a semiconductor memory device
US8547738Mar 14, 2011Oct 1, 2013Micron Technology, Inc.Techniques for providing a semiconductor memory device
US8576631Mar 1, 2011Nov 5, 2013Micron Technology, Inc.Techniques for sensing a semiconductor memory device
US8587996Jul 26, 2010Nov 19, 2013Micron Technology, Inc.Techniques for providing a direct injection semiconductor memory device
US8592907Mar 30, 2011Nov 26, 2013Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for manufacturing the same
US8630126Feb 22, 2011Jan 14, 2014Micron Technology, Inc.Techniques for refreshing a semiconductor memory device
US8653568Jan 25, 2011Feb 18, 2014Semiconductor Energy Laboratory Co., Ltd.Semiconductor substrate with stripes of different crystal plane directions and semiconductor device including the same
US8659948Dec 23, 2011Feb 25, 2014Micron Technology, Inc.Techniques for reading a memory cell with electrically floating body transistor
US8659956Nov 22, 2011Feb 25, 2014Micron Technology, Inc.Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US8699289May 7, 2012Apr 15, 2014Micron Technology, Inc.Techniques for reducing disturbance in a semiconductor memory device
US8710566Mar 4, 2010Apr 29, 2014Micron Technology, Inc.Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
US8748959Mar 31, 2010Jun 10, 2014Micron Technology, Inc.Semiconductor memory device
US8760906Nov 1, 2013Jun 24, 2014Micron Technology, Inc.Techniques for reducing disturbance in a semiconductor memory device
US8772876Oct 30, 2007Jul 8, 2014International Business Machines CorporationHigh-voltage silicon-on-insulator transistors and methods of manufacturing the same
US8773933Mar 16, 2012Jul 8, 2014Micron Technology, Inc.Techniques for accessing memory cells
US8790968May 23, 2011Jul 29, 2014Micron Technology, Inc.Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US8792276Aug 12, 2013Jul 29, 2014Micron Technology, Inc.Semiconductor device with floating gate and electrically floating body
US8796770Jul 23, 2013Aug 5, 2014Micron Technology, Inc.Semiconductor device with electrically floating body
US8797819May 21, 2013Aug 5, 2014Micron Technology, Inc.Refreshing data of memory cells with electrically floating body transistors
US8817534May 21, 2013Aug 26, 2014Micron Technology, Inc.Techniques for providing a semiconductor memory device
US8861247Aug 12, 2013Oct 14, 2014Micron Technology, Inc.Techniques for providing a direct injection semiconductor memory device
US8873283Oct 5, 2009Oct 28, 2014Micron Technology, Inc.Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
US8947965Nov 19, 2012Feb 3, 2015Micron Technology Inc.Techniques for providing a direct injection semiconductor memory device
US8964461Nov 19, 2013Feb 24, 2015Micron Technology, Inc.Techniques for providing a direct injection semiconductor memory device
US8964479Nov 4, 2013Feb 24, 2015Micron Technology, Inc.Techniques for sensing a semiconductor memory device
US8982633Jul 30, 2013Mar 17, 2015Micron Technology, Inc.Techniques for providing a direct injection semiconductor memory device
US9019759Oct 1, 2013Apr 28, 2015Micron Technology, Inc.Techniques for providing a semiconductor memory device
US9019788Jul 7, 2014Apr 28, 2015Micron Technology, Inc.Techniques for accessing memory cells
US9064730Apr 28, 2014Jun 23, 2015Micron Technology, Inc.Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
US9076543Feb 1, 2010Jul 7, 2015Micron Technology, Inc.Techniques for providing a direct injection semiconductor memory device
US9093311Jun 9, 2014Jul 28, 2015Micron Technology, Inc.Techniques for providing a semiconductor memory device
US9105650Feb 21, 2014Aug 11, 2015International Business Machines CorporationLateral bipolar transistor and CMOS hybrid technology
US9142264Jan 13, 2014Sep 22, 2015Micron Technology, Inc.Techniques for refreshing a semiconductor memory device
US9240496Jul 28, 2014Jan 19, 2016Micron Technology, Inc.Semiconductor device with floating gate and electrically floating body
US9257155Feb 24, 2014Feb 9, 2016Micron Technology, Inc.Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US9263133Aug 30, 2013Feb 16, 2016Micron Technology, Inc.Techniques for providing a semiconductor memory device
US9276000Aug 26, 2013Mar 1, 2016Micron Technology, Inc.Manufacturing process for zero-capacitor random access memory circuits
US9331083Aug 13, 2014May 3, 2016Micron Technology, Inc.Techniques for providing a semiconductor memory device
US9425190Oct 1, 2014Aug 23, 2016Micron Technology, Inc.Techniques for providing a direct injection semiconductor memory device
US9524971Feb 5, 2015Dec 20, 2016Micron Technology, Inc.Techniques for providing a semiconductor memory device
US9553186Jul 28, 2014Jan 24, 2017Micron Technology, Inc.Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US9559216Jun 6, 2011Jan 31, 2017Micron Technology, Inc.Semiconductor memory device and method for biasing same
US20070034963 *Aug 10, 2005Feb 15, 2007Toshiba America Electronic Components, Inc.Semiconductor device with close stress liner film and method of manufacturing the same
US20070182030 *Feb 3, 2006Aug 9, 2007International Business Machines CorporationHigh-voltage silicon-on-insulator transistors and methods of manufacturing the same
US20070257291 *Apr 30, 2007Nov 8, 2007Serguei OkhoninSemiconductor memory cell and array using punch-through to program and read same
US20070297252 *Jun 22, 2007Dec 27, 2007Anant Pratap SinghIntegrated circuit having memory array including ECC and/or column redundancy, and method of programming, controlling and/or operating same
US20080048263 *Oct 30, 2007Feb 28, 2008IbmHigh-voltage silicon-on-insulator transistors and methods of manufacturing the same
US20080180995 *Jan 24, 2008Jul 31, 2008Serguei OkhoninSemiconductor Device With Electrically Floating Body
US20080237714 *Mar 21, 2008Oct 2, 2008Pierre FazanManufacturing Process for Zero-Capacitor Random Access Memory Circuits
US20080283958 *Mar 27, 2008Nov 20, 2008Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for manufacturing the same
US20080298139 *May 27, 2008Dec 4, 2008David FischIntegrated circuit having voltage generation circuitry for memory cell array, and method of operating and /or controlling same
US20090016101 *May 30, 2008Jan 15, 2009Serguei OkhoninReading Technique for Memory Cell With Electrically Floating Body Transistor
US20090047771 *Aug 12, 2008Feb 19, 2009Semiconductor Energy Laboratory Co., Ltd.Manufacturing method and manufacturing apparatus of semiconductor device
US20090080244 *Sep 17, 2008Mar 26, 2009Eric CarmanRefreshing Data of Memory Cells with Electrically Floating Body Transistors
US20090141550 *Feb 13, 2009Jun 4, 2009Eric CarmanMemory Array Having a Programmable Word Length, and Method of Operating Same
US20090146219 *Dec 11, 2008Jun 11, 2009Danngis LiuIntegrated circuit having memory cell array, and method of manufacturing same
US20090200612 *Feb 2, 2009Aug 13, 2009Viktor KoldiaevIntegrated Circuit Having Memory Cells Including Gate Material Having High Work Function, and Method of Manufacturing Same
US20090231898 *May 18, 2009Sep 17, 2009David FischIntegrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same
US20090251958 *Apr 4, 2008Oct 8, 2009Philippe BauserRead circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
US20100075471 *Sep 25, 2009Mar 25, 2010Innovative Silicon Isi SaRecessed Gate Silicon-On-Insulator Floating Body Device With Self-Aligned Lateral Isolation
US20100085806 *Oct 2, 2008Apr 8, 2010Ping WangTechniques for reducing a voltage swing
US20100091586 *Oct 15, 2008Apr 15, 2010Innovative Silicon Isi SaTechniques for simultaneously driving a plurality of source lines
US20100110816 *Oct 15, 2009May 6, 2010Innovative Silicon Isi SaTechniques for block refreshing a semiconductor memory device
US20100210075 *Jan 28, 2010Aug 19, 2010Innovative Silicon Isi SaTechniques for providing a source line plane
US20100224924 *Mar 4, 2010Sep 9, 2010Innovative Silicon Isi SaTechniques for forming a contact to a buried diffusion layer in a semiconductor memory device
US20100259964 *Mar 31, 2010Oct 14, 2010Innovative Silicon Isi SaTechniques for providing a semiconductor memory device
US20100271857 *Apr 27, 2010Oct 28, 2010Innovative Silicon Isi SaTechniques for providing a direct injection semiconductor memory device
US20100271858 *Apr 27, 2010Oct 28, 2010Innovative Silicon Isi SaTechniques for providing a direct injection semiconductor memory device having ganged carrier injection lines
US20100271880 *Mar 16, 2010Oct 28, 2010Innovative Silicon Isi SaTechniques for controlling a direct injection semiconductor memory device
US20100277982 *Apr 29, 2010Nov 4, 2010Innovative Silicon Isi SaSemiconductor device with floating gate and electrically floating body
US20110007578 *Jul 12, 2010Jan 13, 2011Innovative Silicon Isi SaTechniques for providing a semiconductor memory device
US20110019479 *Feb 1, 2010Jan 27, 2011Innovative Silicon Isi SaTechniques for providing a direct injection semiconductor memory device
US20110019481 *Jul 26, 2010Jan 27, 2011Innovative Silicon Isi SaTechniques for providing a direct injection semiconductor memory device
US20110019482 *Jul 27, 2010Jan 27, 2011Innovative Silicon Isi SaTechniques for providing a direct injection semiconductor memory device
US20110058436 *Sep 7, 2010Mar 10, 2011Innovative Silicon Isi SaTechniques for sensing a semiconductor memory device
US20110114998 *Jan 25, 2011May 19, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor substrate, semiconductor device, and manufacturing method thereof
US20110141836 *Dec 16, 2009Jun 16, 2011Innovative Silicon Isi SaTechniques for reducing impact of array disturbs in a semiconductor memory device
US20110175146 *Mar 30, 2011Jul 21, 2011Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and method for manufacturing the same
US20110194363 *Apr 22, 2011Aug 11, 2011Micron Technology, Inc.Semiconductor memory cell and array using punch-through to program and read same
US20110199848 *Dec 29, 2010Aug 18, 2011Innovative Silicon Isi SaTechniques for controlling a semiconductor memory device
US20110216605 *Dec 21, 2010Sep 8, 2011Innovative Silicon Isi SaTechniques for providing a semiconductor memory device having hierarchical bit lines
US20110216608 *Mar 5, 2010Sep 8, 2011Innovative Silicon Isi SaTechniques for reading from and/or writing to a semiconductor memory device
US20110216617 *Mar 1, 2011Sep 8, 2011Innovative Silicon Isi SaTechniques for sensing a semiconductor memory device
US20110223726 *May 23, 2011Sep 15, 2011Micron Technology, Inc.Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US20120168864 *Mar 13, 2012Jul 5, 2012International Business Machines CorporationSelf-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage
Classifications
U.S. Classification257/347, 257/E21.438, 257/E29.147, 257/E21.415, 257/382, 257/384, 257/E29.151, 257/E29.255
International ClassificationH01L29/786, H01L21/285, H01L29/45, H01L29/49, H01L21/28, H01L21/336, H01L29/76
Cooperative ClassificationH01L21/28518, H01L29/665, H01L29/78, H01L29/458, H01L29/66772, H01L29/4908
European ClassificationH01L29/66M6T6F15C, H01L29/66M6T6F3, H01L21/285B4A, H01L29/45S2, H01L29/49B